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https://github.com/edk2-porting/linux-next.git
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MIPS: Code formatting fixes.
Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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36be50515f
commit
03751e7924
arch/mips/kernel
@ -340,7 +340,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R2000";
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c->isa_level = MIPS_CPU_ISA_I;
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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c->options |= MIPS_CPU_FPU;
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c->tlbsize = 64;
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@ -361,7 +361,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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}
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c->isa_level = MIPS_CPU_ISA_I;
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c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
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MIPS_CPU_NOFPUEX;
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MIPS_CPU_NOFPUEX;
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if (__cpu_has_fpu())
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c->options |= MIPS_CPU_FPU;
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c->tlbsize = 64;
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@ -387,8 +387,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_WATCH | MIPS_CPU_VCE |
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MIPS_CPU_LLSC;
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MIPS_CPU_WATCH | MIPS_CPU_VCE |
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_VR41XX:
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@ -434,7 +434,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R4300";
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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break;
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case PRID_IMP_R4600:
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@ -446,7 +446,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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c->tlbsize = 48;
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break;
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#if 0
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case PRID_IMP_R4650:
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case PRID_IMP_R4650:
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/*
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* This processor doesn't have an MMU, so it's not
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* "real easy" to run Linux on it. It is left purely
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@ -455,9 +455,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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*/
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c->cputype = CPU_R4650;
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__cpu_name[cpu] = "R4650";
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c->isa_level = MIPS_CPU_ISA_III;
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
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c->tlbsize = 48;
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c->tlbsize = 48;
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break;
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#endif
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case PRID_IMP_TX39:
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@ -488,7 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R4700";
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c->isa_level = MIPS_CPU_ISA_III;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_TX49:
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@ -505,7 +505,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R5000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_R5432:
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@ -513,7 +513,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R5432";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_WATCH | MIPS_CPU_LLSC;
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MIPS_CPU_WATCH | MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_R5500:
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@ -521,7 +521,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R5500";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_WATCH | MIPS_CPU_LLSC;
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MIPS_CPU_WATCH | MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_NEVADA:
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@ -529,7 +529,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "Nevada";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
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c->tlbsize = 48;
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break;
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case PRID_IMP_R6000:
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@ -537,7 +537,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R6000";
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c->isa_level = MIPS_CPU_ISA_II;
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c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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break;
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case PRID_IMP_R6000A:
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@ -545,7 +545,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R6000A";
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c->isa_level = MIPS_CPU_ISA_II;
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c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 32;
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break;
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case PRID_IMP_RM7000:
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@ -553,7 +553,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "RM7000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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/*
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* Undocumented RM7000: Bit 29 in the info register of
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* the RM7000 v2.0 indicates if the TLB has 48 or 64
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@ -569,7 +569,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "RM9000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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/*
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* Bit 29 in the info register of the RM9000
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* indicates if the TLB has 48 or 64 entries.
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@ -584,8 +584,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "RM8000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
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break;
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case PRID_IMP_R10000:
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@ -593,9 +593,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R10000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 64;
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break;
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case PRID_IMP_R12000:
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@ -603,9 +603,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R12000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 64;
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break;
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case PRID_IMP_R14000:
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@ -613,9 +613,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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__cpu_name[cpu] = "R14000";
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c->isa_level = MIPS_CPU_ISA_IV;
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c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
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MIPS_CPU_LLSC;
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MIPS_CPU_LLSC;
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c->tlbsize = 64;
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break;
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case PRID_IMP_LOONGSON2:
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@ -739,7 +739,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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if (config3 & MIPS_CONF3_VEIC)
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c->options |= MIPS_CPU_VEIC;
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if (config3 & MIPS_CONF3_MT)
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c->ases |= MIPS_ASE_MIPSMT;
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c->ases |= MIPS_ASE_MIPSMT;
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if (config3 & MIPS_CONF3_ULRI)
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c->options |= MIPS_CPU_ULRI;
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@ -767,7 +767,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
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/* MIPS32 or MIPS64 compliant CPU. */
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c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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@ -41,27 +41,27 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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seq_printf(m, "processor\t\t: %ld\n", n);
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sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
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cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
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cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
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seq_printf(m, fmt, __cpu_name[n],
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(version >> 4) & 0x0f, version & 0x0f,
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(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
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(version >> 4) & 0x0f, version & 0x0f,
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(fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
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seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
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cpu_data[n].udelay_val / (500000/HZ),
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(cpu_data[n].udelay_val / (5000/HZ)) % 100);
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cpu_data[n].udelay_val / (500000/HZ),
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(cpu_data[n].udelay_val / (5000/HZ)) % 100);
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seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
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seq_printf(m, "microsecond timers\t: %s\n",
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cpu_has_counter ? "yes" : "no");
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cpu_has_counter ? "yes" : "no");
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seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
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seq_printf(m, "extra interrupt vector\t: %s\n",
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cpu_has_divec ? "yes" : "no");
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cpu_has_divec ? "yes" : "no");
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seq_printf(m, "hardware watchpoint\t: %s",
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cpu_has_watch ? "yes, " : "no\n");
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cpu_has_watch ? "yes, " : "no\n");
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if (cpu_has_watch) {
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seq_printf(m, "count: %d, address/irw mask: [",
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cpu_data[n].watch_reg_count);
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cpu_data[n].watch_reg_count);
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for (i = 0; i < cpu_data[n].watch_reg_count; i++)
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seq_printf(m, "%s0x%04x", i ? ", " : "" ,
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cpu_data[n].watch_reg_masks[i]);
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cpu_data[n].watch_reg_masks[i]);
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seq_printf(m, "]\n");
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}
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seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
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@ -73,13 +73,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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cpu_has_mipsmt ? " mt" : ""
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);
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seq_printf(m, "shadow register sets\t: %d\n",
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cpu_data[n].srsets);
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cpu_data[n].srsets);
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seq_printf(m, "kscratch registers\t: %d\n",
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hweight8(cpu_data[n].kscratch_mask));
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hweight8(cpu_data[n].kscratch_mask));
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seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
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sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
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cpu_has_vce ? "%u" : "not available");
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cpu_has_vce ? "%u" : "not available");
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seq_printf(m, fmt, 'D', vced_count);
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seq_printf(m, fmt, 'I', vcei_count);
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seq_printf(m, "\n");
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