renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-19 02:34:01 +08:00
Code

ARM: cache-tauros2: remove ARMv6 code

Browse Source 
When building a kernel with support for both ARMv6 and ARMv7 but
no MMU, the call from tauros2_internal_init to adjust_cr causes
a link error. While that could probably be resolved, we don't
actually support cache-tauros2 on ARMv6 any more. All PJ4 CPU
implementations support both ARMv6 and ARMv7 and we already assume
that we are using them only in ARMv7 mode.

Removing the ARMv6 code path reduces the code size and avoids
the linker error.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
This commit is contained in:
Arnd Bergmann 2014-03-11 17:41:33 +01:00
parent a1b6b737de
commit 027f3f9696
1 changed files with 1 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
arch/arm/mm/cache-tauros2.c
View File

@ -33,7 +33,7 @@
* outer cache operations into the kernel image if the kernel has been
* configured to support a pre-v7 CPU.
*/
#if __LINUX_ARM_ARCH__ < 7
#ifdef CONFIG_CPU_32v5
/*
* Low-level cache maintenance operations.
*/
@ -229,33 +229,6 @@ static void __init tauros2_internal_init(unsigned int features)
}
#endif
#ifdef CONFIG_CPU_32v6
/*
* Check whether this CPU lacks support for the v7 hierarchical
* cache ops. (PJ4 is in its v6 personality mode if the MMFR3
* register indicates no support for the v7 hierarchical cache
* ops.)
*/
if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
/*
* When Tauros2 is used in an ARMv6 system, the L2
* enable bit is in the ARMv6 ARM-mandated position
* (bit [26] of the System Control Register).
*/
if (!(get_cr() & 0x04000000)) {
printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
adjust_cr(0x04000000, 0x04000000);
}
mode = "ARMv6";
outer_cache.inv_range = tauros2_inv_range;
outer_cache.clean_range = tauros2_clean_range;
outer_cache.flush_range = tauros2_flush_range;
outer_cache.disable = tauros2_disable;
outer_cache.resume = tauros2_resume;
}
#endif
#ifdef CONFIG_CPU_32v7
/*
* Check whether this CPU has support for the v7 hierarchical