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x86: Cleanup visws interrupt handling
Remove the open coded access to irq_desc and convert to the new irq chip functions. Change the mask function of piix4_virtual_irq_type so we can use the generic irq handling function for the virtual interrupt instead of open coding it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner
parent
fe25c7fc2e
commit
020dd984d7
@ -66,10 +66,7 @@ static void __init visws_time_init(void)
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}
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/* Replaces the default init_ISA_irqs in the generic setup */
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static void __init visws_pre_intr_init(void)
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{
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init_VISWS_APIC_irqs();
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}
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static void __init visws_pre_intr_init(void);
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/* Quirk for machine specific memory setup. */
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@ -429,67 +426,34 @@ static int is_co_apic(unsigned int irq)
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/*
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* This is the SGI Cobalt (IO-)APIC:
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*/
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static void enable_cobalt_irq(unsigned int irq)
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static void enable_cobalt_irq(struct irq_data *data)
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{
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co_apic_set(is_co_apic(irq), irq);
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co_apic_set(is_co_apic(data->irq), data->irq);
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}
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static void disable_cobalt_irq(unsigned int irq)
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static void disable_cobalt_irq(struct irq_data *data)
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{
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int entry = is_co_apic(irq);
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int entry = is_co_apic(data->irq);
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co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
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co_apic_read(CO_APIC_LO(entry));
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}
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/*
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* "irq" really just serves to identify the device. Here is where we
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* map this to the Cobalt APIC entry where it's physically wired.
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* This is called via request_irq -> setup_irq -> irq_desc->startup()
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*/
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static unsigned int startup_cobalt_irq(unsigned int irq)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_to_desc(irq);
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spin_lock_irqsave(&cobalt_lock, flags);
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if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
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desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
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enable_cobalt_irq(irq);
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spin_unlock_irqrestore(&cobalt_lock, flags);
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return 0;
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}
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static void ack_cobalt_irq(unsigned int irq)
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static void ack_cobalt_irq(struct irq_data *data)
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{
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unsigned long flags;
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spin_lock_irqsave(&cobalt_lock, flags);
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disable_cobalt_irq(irq);
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disable_cobalt_irq(data);
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apic_write(APIC_EOI, APIC_EIO_ACK);
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spin_unlock_irqrestore(&cobalt_lock, flags);
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}
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static void end_cobalt_irq(unsigned int irq)
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{
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unsigned long flags;
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struct irq_desc *desc = irq_to_desc(irq);
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spin_lock_irqsave(&cobalt_lock, flags);
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if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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enable_cobalt_irq(irq);
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spin_unlock_irqrestore(&cobalt_lock, flags);
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}
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static struct irq_chip cobalt_irq_type = {
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.name = "Cobalt-APIC",
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.startup = startup_cobalt_irq,
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.shutdown = disable_cobalt_irq,
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.enable = enable_cobalt_irq,
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.disable = disable_cobalt_irq,
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.ack = ack_cobalt_irq,
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.end = end_cobalt_irq,
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.name = "Cobalt-APIC",
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.irq_enable = enable_cobalt_irq,
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.irq_disable = disable_cobalt_irq,
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.irq_ack = ack_cobalt_irq,
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};
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@ -503,35 +467,34 @@ static struct irq_chip cobalt_irq_type = {
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* interrupt controller type, and through a special virtual interrupt-
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* controller. Device drivers only see the virtual interrupt sources.
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*/
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static unsigned int startup_piix4_master_irq(unsigned int irq)
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static unsigned int startup_piix4_master_irq(struct irq_data *data)
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{
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legacy_pic->init(0);
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return startup_cobalt_irq(irq);
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enable_cobalt_irq(data);
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}
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static void end_piix4_master_irq(unsigned int irq)
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static void end_piix4_master_irq(struct irq_data *data)
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{
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unsigned long flags;
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spin_lock_irqsave(&cobalt_lock, flags);
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enable_cobalt_irq(irq);
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enable_cobalt_irq(data);
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spin_unlock_irqrestore(&cobalt_lock, flags);
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}
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static struct irq_chip piix4_master_irq_type = {
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.name = "PIIX4-master",
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.startup = startup_piix4_master_irq,
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.ack = ack_cobalt_irq,
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.end = end_piix4_master_irq,
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.name = "PIIX4-master",
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.irq_startup = startup_piix4_master_irq,
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.irq_ack = ack_cobalt_irq,
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};
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static void pii4_mask(struct irq_data *data) { }
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static struct irq_chip piix4_virtual_irq_type = {
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.name = "PIIX4-virtual",
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.name = "PIIX4-virtual",
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.mask = pii4_mask,
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};
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/*
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* PIIX4-8259 master/virtual functions to handle interrupt requests
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* from legacy devices: floppy, parallel, serial, rtc.
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@ -549,9 +512,8 @@ static struct irq_chip piix4_virtual_irq_type = {
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*/
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static irqreturn_t piix4_master_intr(int irq, void *dev_id)
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{
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int realirq;
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struct irq_desc *desc;
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unsigned long flags;
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int realirq;
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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@ -592,18 +554,10 @@ static irqreturn_t piix4_master_intr(int irq, void *dev_id)
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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desc = irq_to_desc(realirq);
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/*
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* handle this 'virtual interrupt' as a Cobalt one now.
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*/
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kstat_incr_irqs_this_cpu(realirq, desc);
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if (likely(desc->action != NULL))
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handle_IRQ_event(realirq, desc->action);
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if (!(desc->status & IRQ_DISABLED))
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legacy_pic->chip->unmask(realirq);
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generic_handle_irq(realirq);
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return IRQ_HANDLED;
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@ -624,41 +578,35 @@ static struct irqaction cascade_action = {
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static inline void set_piix4_virtual_irq_type(void)
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{
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piix4_virtual_irq_type.shutdown = i8259A_chip.mask;
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piix4_virtual_irq_type.enable = i8259A_chip.unmask;
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piix4_virtual_irq_type.disable = i8259A_chip.mask;
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piix4_virtual_irq_type.unmask = i8259A_chip.unmask;
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}
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void init_VISWS_APIC_irqs(void)
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static void __init visws_pre_intr_init(void)
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{
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int i;
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set_piix4_virtual_irq_type();
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for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
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struct irq_desc *desc = irq_to_desc(i);
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struct irq_chip *chip = NULL;
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desc->status = IRQ_DISABLED;
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desc->action = 0;
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desc->depth = 1;
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if (i == 0)
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chip = &cobalt_irq_type;
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else if (i == CO_IRQ_IDE0)
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chip = &cobalt_irq_type;
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else if (i == CO_IRQ_IDE1)
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>chip = &cobalt_irq_type;
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else if (i == CO_IRQ_8259)
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chip = &piix4_master_irq_type;
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else if (i < CO_IRQ_APIC0)
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chip = &piix4_virtual_irq_type;
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else if (IS_CO_APIC(i))
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chip = &cobalt_irq_type;
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if (i == 0) {
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desc->chip = &cobalt_irq_type;
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}
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else if (i == CO_IRQ_IDE0) {
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desc->chip = &cobalt_irq_type;
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}
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else if (i == CO_IRQ_IDE1) {
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desc->chip = &cobalt_irq_type;
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}
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else if (i == CO_IRQ_8259) {
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desc->chip = &piix4_master_irq_type;
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}
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else if (i < CO_IRQ_APIC0) {
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set_piix4_virtual_irq_type();
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desc->chip = &piix4_virtual_irq_type;
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}
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else if (IS_CO_APIC(i)) {
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desc->chip = &cobalt_irq_type;
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}
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if (chip)
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set_irq_chip(i, chip);
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}
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setup_irq(CO_IRQ_8259, &master_action);
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