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clk: renesas: r8a7743: Add r8a7744 support

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Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software
Reset support.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2018-09-11 11:12:49 +01:00 committed by Geert Uytterhoeven
parent 6ff9cb53da
commit 016f966315
3 changed files with 18 additions and 2 deletions
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2
drivers/clk/renesas/Kconfig
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@ -6,7 +6,7 @@ config CLK_RENESAS
select CLK_R7S9210 if ARCH_R7S9210
select CLK_R8A73A4 if ARCH_R8A73A4
select CLK_R8A7740 if ARCH_R8A7740
select CLK_R8A7743 if ARCH_R8A7743
select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
select CLK_R8A7745 if ARCH_R8A7745
select CLK_R8A77470 if ARCH_R8A77470
select CLK_R8A774A1 if ARCH_R8A774A1

13
drivers/clk/renesas/r8a7743-cpg-mssr.c
View File

@ -11,6 +11,7 @@
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/soc/renesas/rcar-rst.h>
#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
@ -37,7 +38,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
static struct cpg_core_clk r8a7743_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@ -238,6 +239,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
static int __init r8a7743_cpg_mssr_init(struct device *dev)
{
const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
struct device_node *np = dev->of_node;
unsigned int i;
u32 cpg_mode;
int error;
@ -247,6 +250,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev)
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {
/* RZ/G1N uses a 1/5 divider for ZG */
for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)
if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {
r8a7743_core_clks[i].div = 5;
break;
}
}
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
}

5
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@ -693,6 +693,11 @@ static const struct of_device_id cpg_mssr_match[] = {
.compatible = "renesas,r8a7743-cpg-mssr",
.data = &r8a7743_cpg_mssr_info,
},
/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
{
.compatible = "renesas,r8a7744-cpg-mssr",
.data = &r8a7743_cpg_mssr_info,
},
#endif
#ifdef CONFIG_CLK_R8A7745
{