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dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap.
All the following clock ids are now decreased by 10 to keep the numbering
right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with
IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and
all the following ids are updated accordingly.
Reported-by: Patrick Wildt <patrick@blueri.se>
Fixes: 1cf3817b
("dt-bindings: Add binding for i.MX8MQ CCM")
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
d17a718db4
commit
010d5166bb
@ -245,160 +245,160 @@
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/* USB_CORE_REF */
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#define IMX8MQ_CLK_USB_CORE_REF 152
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/* USB_PHY_REF */
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#define IMX8MQ_CLK_USB_PHY_REF 163
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#define IMX8MQ_CLK_USB_PHY_REF 153
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/* ECSPI1 */
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#define IMX8MQ_CLK_ECSPI1 164
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#define IMX8MQ_CLK_ECSPI1 154
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/* ECSPI2 */
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#define IMX8MQ_CLK_ECSPI2 165
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#define IMX8MQ_CLK_ECSPI2 155
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/* PWM1 */
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#define IMX8MQ_CLK_PWM1 166
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#define IMX8MQ_CLK_PWM1 156
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/* PWM2 */
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#define IMX8MQ_CLK_PWM2 167
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#define IMX8MQ_CLK_PWM2 157
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/* PWM3 */
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#define IMX8MQ_CLK_PWM3 168
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#define IMX8MQ_CLK_PWM3 158
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/* PWM4 */
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#define IMX8MQ_CLK_PWM4 169
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#define IMX8MQ_CLK_PWM4 159
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/* GPT1 */
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#define IMX8MQ_CLK_GPT1 170
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#define IMX8MQ_CLK_GPT1 160
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/* WDOG */
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#define IMX8MQ_CLK_WDOG 171
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#define IMX8MQ_CLK_WDOG 161
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/* WRCLK */
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#define IMX8MQ_CLK_WRCLK 172
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#define IMX8MQ_CLK_WRCLK 162
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/* DSI_CORE */
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#define IMX8MQ_CLK_DSI_CORE 173
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#define IMX8MQ_CLK_DSI_CORE 163
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/* DSI_PHY */
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#define IMX8MQ_CLK_DSI_PHY_REF 174
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#define IMX8MQ_CLK_DSI_PHY_REF 164
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/* DSI_DBI */
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#define IMX8MQ_CLK_DSI_DBI 175
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#define IMX8MQ_CLK_DSI_DBI 165
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/*DSI_ESC */
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#define IMX8MQ_CLK_DSI_ESC 176
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#define IMX8MQ_CLK_DSI_ESC 166
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/* CSI1_CORE */
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#define IMX8MQ_CLK_CSI1_CORE 177
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#define IMX8MQ_CLK_CSI1_CORE 167
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/* CSI1_PHY */
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#define IMX8MQ_CLK_CSI1_PHY_REF 178
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#define IMX8MQ_CLK_CSI1_PHY_REF 168
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/* CSI_ESC */
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#define IMX8MQ_CLK_CSI1_ESC 179
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#define IMX8MQ_CLK_CSI1_ESC 169
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/* CSI2_CORE */
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#define IMX8MQ_CLK_CSI2_CORE 170
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/* CSI2_PHY */
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#define IMX8MQ_CLK_CSI2_PHY_REF 181
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#define IMX8MQ_CLK_CSI2_PHY_REF 171
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/* CSI2_ESC */
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#define IMX8MQ_CLK_CSI2_ESC 182
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#define IMX8MQ_CLK_CSI2_ESC 172
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/* PCIE2_CTRL */
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#define IMX8MQ_CLK_PCIE2_CTRL 183
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#define IMX8MQ_CLK_PCIE2_CTRL 173
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/* PCIE2_PHY */
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#define IMX8MQ_CLK_PCIE2_PHY 184
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#define IMX8MQ_CLK_PCIE2_PHY 174
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/* PCIE2_AUX */
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#define IMX8MQ_CLK_PCIE2_AUX 185
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#define IMX8MQ_CLK_PCIE2_AUX 175
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/* ECSPI3 */
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#define IMX8MQ_CLK_ECSPI3 186
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#define IMX8MQ_CLK_ECSPI3 176
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/* CCGR clocks */
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#define IMX8MQ_CLK_A53_ROOT 187
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#define IMX8MQ_CLK_DRAM_ROOT 188
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#define IMX8MQ_CLK_ECSPI1_ROOT 189
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#define IMX8MQ_CLK_A53_ROOT 177
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#define IMX8MQ_CLK_DRAM_ROOT 178
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#define IMX8MQ_CLK_ECSPI1_ROOT 179
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#define IMX8MQ_CLK_ECSPI2_ROOT 180
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#define IMX8MQ_CLK_ECSPI3_ROOT 181
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#define IMX8MQ_CLK_ENET1_ROOT 182
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#define IMX8MQ_CLK_GPT1_ROOT 193
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#define IMX8MQ_CLK_I2C1_ROOT 194
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#define IMX8MQ_CLK_I2C2_ROOT 195
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#define IMX8MQ_CLK_I2C3_ROOT 196
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#define IMX8MQ_CLK_I2C4_ROOT 197
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#define IMX8MQ_CLK_M4_ROOT 198
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#define IMX8MQ_CLK_PCIE1_ROOT 199
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#define IMX8MQ_CLK_PCIE2_ROOT 200
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#define IMX8MQ_CLK_PWM1_ROOT 201
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#define IMX8MQ_CLK_PWM2_ROOT 202
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#define IMX8MQ_CLK_PWM3_ROOT 203
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#define IMX8MQ_CLK_PWM4_ROOT 204
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#define IMX8MQ_CLK_QSPI_ROOT 205
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#define IMX8MQ_CLK_SAI1_ROOT 206
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#define IMX8MQ_CLK_SAI2_ROOT 207
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#define IMX8MQ_CLK_SAI3_ROOT 208
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#define IMX8MQ_CLK_SAI4_ROOT 209
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#define IMX8MQ_CLK_SAI5_ROOT 210
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#define IMX8MQ_CLK_SAI6_ROOT 212
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#define IMX8MQ_CLK_UART1_ROOT 213
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#define IMX8MQ_CLK_UART2_ROOT 214
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#define IMX8MQ_CLK_UART3_ROOT 215
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#define IMX8MQ_CLK_UART4_ROOT 216
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#define IMX8MQ_CLK_USB1_CTRL_ROOT 217
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#define IMX8MQ_CLK_USB2_CTRL_ROOT 218
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#define IMX8MQ_CLK_USB1_PHY_ROOT 219
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#define IMX8MQ_CLK_USB2_PHY_ROOT 220
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#define IMX8MQ_CLK_USDHC1_ROOT 221
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#define IMX8MQ_CLK_USDHC2_ROOT 222
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#define IMX8MQ_CLK_WDOG1_ROOT 223
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#define IMX8MQ_CLK_WDOG2_ROOT 224
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#define IMX8MQ_CLK_WDOG3_ROOT 225
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#define IMX8MQ_CLK_GPU_ROOT 226
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#define IMX8MQ_CLK_HEVC_ROOT 227
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#define IMX8MQ_CLK_AVC_ROOT 228
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#define IMX8MQ_CLK_VP9_ROOT 229
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#define IMX8MQ_CLK_HEVC_INTER_ROOT 230
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#define IMX8MQ_CLK_DISP_ROOT 231
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#define IMX8MQ_CLK_HDMI_ROOT 232
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#define IMX8MQ_CLK_HDMI_PHY_ROOT 233
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#define IMX8MQ_CLK_VPU_DEC_ROOT 234
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#define IMX8MQ_CLK_CSI1_ROOT 235
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#define IMX8MQ_CLK_CSI2_ROOT 236
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#define IMX8MQ_CLK_RAWNAND_ROOT 237
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#define IMX8MQ_CLK_SDMA1_ROOT 238
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#define IMX8MQ_CLK_SDMA2_ROOT 239
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#define IMX8MQ_CLK_VPU_G1_ROOT 240
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#define IMX8MQ_CLK_VPU_G2_ROOT 241
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#define IMX8MQ_CLK_GPT1_ROOT 183
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#define IMX8MQ_CLK_I2C1_ROOT 184
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#define IMX8MQ_CLK_I2C2_ROOT 185
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#define IMX8MQ_CLK_I2C3_ROOT 186
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#define IMX8MQ_CLK_I2C4_ROOT 187
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#define IMX8MQ_CLK_M4_ROOT 188
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#define IMX8MQ_CLK_PCIE1_ROOT 189
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#define IMX8MQ_CLK_PCIE2_ROOT 190
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#define IMX8MQ_CLK_PWM1_ROOT 191
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#define IMX8MQ_CLK_PWM2_ROOT 192
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#define IMX8MQ_CLK_PWM3_ROOT 193
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#define IMX8MQ_CLK_PWM4_ROOT 194
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#define IMX8MQ_CLK_QSPI_ROOT 195
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#define IMX8MQ_CLK_SAI1_ROOT 196
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#define IMX8MQ_CLK_SAI2_ROOT 197
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#define IMX8MQ_CLK_SAI3_ROOT 198
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#define IMX8MQ_CLK_SAI4_ROOT 199
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#define IMX8MQ_CLK_SAI5_ROOT 200
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#define IMX8MQ_CLK_SAI6_ROOT 201
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#define IMX8MQ_CLK_UART1_ROOT 202
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#define IMX8MQ_CLK_UART2_ROOT 203
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#define IMX8MQ_CLK_UART3_ROOT 204
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#define IMX8MQ_CLK_UART4_ROOT 205
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#define IMX8MQ_CLK_USB1_CTRL_ROOT 206
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#define IMX8MQ_CLK_USB2_CTRL_ROOT 207
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#define IMX8MQ_CLK_USB1_PHY_ROOT 208
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#define IMX8MQ_CLK_USB2_PHY_ROOT 209
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#define IMX8MQ_CLK_USDHC1_ROOT 210
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#define IMX8MQ_CLK_USDHC2_ROOT 211
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#define IMX8MQ_CLK_WDOG1_ROOT 212
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#define IMX8MQ_CLK_WDOG2_ROOT 213
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#define IMX8MQ_CLK_WDOG3_ROOT 214
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#define IMX8MQ_CLK_GPU_ROOT 215
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#define IMX8MQ_CLK_HEVC_ROOT 216
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#define IMX8MQ_CLK_AVC_ROOT 217
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#define IMX8MQ_CLK_VP9_ROOT 218
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#define IMX8MQ_CLK_HEVC_INTER_ROOT 219
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#define IMX8MQ_CLK_DISP_ROOT 220
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#define IMX8MQ_CLK_HDMI_ROOT 221
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#define IMX8MQ_CLK_HDMI_PHY_ROOT 222
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#define IMX8MQ_CLK_VPU_DEC_ROOT 223
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#define IMX8MQ_CLK_CSI1_ROOT 224
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#define IMX8MQ_CLK_CSI2_ROOT 225
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#define IMX8MQ_CLK_RAWNAND_ROOT 226
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#define IMX8MQ_CLK_SDMA1_ROOT 227
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#define IMX8MQ_CLK_SDMA2_ROOT 228
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#define IMX8MQ_CLK_VPU_G1_ROOT 229
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#define IMX8MQ_CLK_VPU_G2_ROOT 230
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/* SCCG PLL GATE */
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#define IMX8MQ_SYS1_PLL_OUT 242
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#define IMX8MQ_SYS2_PLL_OUT 243
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#define IMX8MQ_SYS3_PLL_OUT 244
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#define IMX8MQ_DRAM_PLL_OUT 245
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#define IMX8MQ_SYS1_PLL_OUT 231
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#define IMX8MQ_SYS2_PLL_OUT 232
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#define IMX8MQ_SYS3_PLL_OUT 233
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#define IMX8MQ_DRAM_PLL_OUT 234
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#define IMX8MQ_GPT_3M_CLK 246
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#define IMX8MQ_GPT_3M_CLK 235
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#define IMX8MQ_CLK_IPG_ROOT 247
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#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248
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#define IMX8MQ_CLK_SAI1_IPG 249
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#define IMX8MQ_CLK_SAI2_IPG 250
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#define IMX8MQ_CLK_SAI3_IPG 251
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#define IMX8MQ_CLK_SAI4_IPG 252
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#define IMX8MQ_CLK_SAI5_IPG 253
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#define IMX8MQ_CLK_SAI6_IPG 254
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#define IMX8MQ_CLK_IPG_ROOT 236
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#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237
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#define IMX8MQ_CLK_SAI1_IPG 238
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#define IMX8MQ_CLK_SAI2_IPG 239
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#define IMX8MQ_CLK_SAI3_IPG 240
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#define IMX8MQ_CLK_SAI4_IPG 241
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#define IMX8MQ_CLK_SAI5_IPG 242
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#define IMX8MQ_CLK_SAI6_IPG 243
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/* DSI AHB/IPG clocks */
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/* rxesc clock */
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#define IMX8MQ_CLK_DSI_AHB 255
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#define IMX8MQ_CLK_DSI_AHB 244
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/* txesc clock */
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#define IMX8MQ_CLK_DSI_IPG_DIV 256
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#define IMX8MQ_CLK_DSI_IPG_DIV 245
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#define IMX8MQ_CLK_TMU_ROOT 257
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#define IMX8MQ_CLK_TMU_ROOT 246
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/* Display root clocks */
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#define IMX8MQ_CLK_DISP_AXI_ROOT 258
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#define IMX8MQ_CLK_DISP_APB_ROOT 259
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#define IMX8MQ_CLK_DISP_RTRM_ROOT 260
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#define IMX8MQ_CLK_DISP_AXI_ROOT 247
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#define IMX8MQ_CLK_DISP_APB_ROOT 248
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#define IMX8MQ_CLK_DISP_RTRM_ROOT 249
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#define IMX8MQ_CLK_OCOTP_ROOT 261
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#define IMX8MQ_CLK_OCOTP_ROOT 250
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#define IMX8MQ_CLK_DRAM_ALT_ROOT 262
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#define IMX8MQ_CLK_DRAM_CORE 263
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#define IMX8MQ_CLK_DRAM_ALT_ROOT 251
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#define IMX8MQ_CLK_DRAM_CORE 252
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#define IMX8MQ_CLK_MU_ROOT 264
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#define IMX8MQ_VIDEO2_PLL_OUT 265
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#define IMX8MQ_CLK_MU_ROOT 253
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#define IMX8MQ_VIDEO2_PLL_OUT 254
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#define IMX8MQ_CLK_CLKO2 266
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#define IMX8MQ_CLK_CLKO2 255
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#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 267
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#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256
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#define IMX8MQ_CLK_CLKO1 268
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#define IMX8MQ_CLK_ARM 269
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#define IMX8MQ_CLK_CLKO1 257
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#define IMX8MQ_CLK_ARM 258
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#define IMX8MQ_CLK_GPIO1_ROOT 270
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#define IMX8MQ_CLK_GPIO2_ROOT 271
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#define IMX8MQ_CLK_GPIO3_ROOT 272
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#define IMX8MQ_CLK_GPIO4_ROOT 273
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#define IMX8MQ_CLK_GPIO5_ROOT 274
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#define IMX8MQ_CLK_GPIO1_ROOT 259
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#define IMX8MQ_CLK_GPIO2_ROOT 260
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#define IMX8MQ_CLK_GPIO3_ROOT 261
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#define IMX8MQ_CLK_GPIO4_ROOT 262
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#define IMX8MQ_CLK_GPIO5_ROOT 263
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#define IMX8MQ_CLK_END 275
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#define IMX8MQ_CLK_END 264
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#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
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