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https://github.com/edk2-porting/linux-next.git
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KVM: x2apic interface to lapic
This patch implements MSR interface to local apic as defines by x2apic Intel specification. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Gleb Natapov
Avi Kivity
parent
fc61b800f9
commit
0105d1a526
@ -32,6 +32,7 @@
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#include <asm/current.h>
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#include <asm/apicdef.h>
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#include <asm/atomic.h>
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#include <asm/apicdef.h>
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#include "kvm_cache_regs.h"
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#include "irq.h"
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#include "trace.h"
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@ -158,6 +159,11 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
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apic_set_reg(apic, APIC_LVR, v);
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}
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static inline int apic_x2apic_mode(struct kvm_lapic *apic)
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{
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return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
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}
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static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
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LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
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LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
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@ -284,7 +290,12 @@ int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
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int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
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{
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int result = 0;
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u8 logical_id;
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u32 logical_id;
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if (apic_x2apic_mode(apic)) {
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logical_id = apic_get_reg(apic, APIC_LDR);
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return logical_id & mda;
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}
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logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
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@ -477,7 +488,10 @@ static void apic_send_ipi(struct kvm_lapic *apic)
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irq.level = icr_low & APIC_INT_ASSERT;
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irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
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irq.shorthand = icr_low & APIC_SHORT_MASK;
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irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
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if (apic_x2apic_mode(apic))
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irq.dest_id = icr_high;
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else
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irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
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apic_debug("icr_high 0x%x, icr_low 0x%x, "
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"short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
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@ -538,6 +552,12 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
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return 0;
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switch (offset) {
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case APIC_ID:
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if (apic_x2apic_mode(apic))
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val = kvm_apic_id(apic);
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else
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val = kvm_apic_id(apic) << 24;
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break;
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case APIC_ARBPRI:
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printk(KERN_WARNING "Access APIC ARBPRI register "
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"which is for P6\n");
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@ -564,28 +584,26 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
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return container_of(dev, struct kvm_lapic, dev);
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}
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static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
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static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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void *data)
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{
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return apic_hw_enabled(apic) &&
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addr >= apic->base_address &&
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addr < apic->base_address + LAPIC_MMIO_LENGTH;
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}
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static int apic_mmio_read(struct kvm_io_device *this,
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gpa_t address, int len, void *data)
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{
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struct kvm_lapic *apic = to_lapic(this);
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unsigned int offset = address - apic->base_address;
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unsigned char alignment = offset & 0xf;
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u32 result;
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if (!apic_mmio_in_range(apic, address))
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return -EOPNOTSUPP;
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/* this bitmask has a bit cleared for each reserver register */
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static const u64 rmask = 0x43ff01ffffffe70cULL;
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if ((alignment + len) > 4) {
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printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
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(unsigned long)address, len);
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return 0;
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printk(KERN_ERR "KVM_APIC_READ: alignment error %x %d\n",
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offset, len);
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return 1;
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}
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if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
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printk(KERN_ERR "KVM_APIC_READ: read reserved register %x\n",
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offset);
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return 1;
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}
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result = __apic_read(apic, offset & ~0xf);
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trace_kvm_apic_read(offset, result);
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@ -604,6 +622,27 @@ static int apic_mmio_read(struct kvm_io_device *this,
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return 0;
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}
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static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
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{
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return apic_hw_enabled(apic) &&
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addr >= apic->base_address &&
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addr < apic->base_address + LAPIC_MMIO_LENGTH;
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}
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static int apic_mmio_read(struct kvm_io_device *this,
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gpa_t address, int len, void *data)
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{
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struct kvm_lapic *apic = to_lapic(this);
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u32 offset = address - apic->base_address;
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if (!apic_mmio_in_range(apic, address))
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return -EOPNOTSUPP;
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apic_reg_read(apic, offset, len, data);
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return 0;
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}
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static void update_divide_count(struct kvm_lapic *apic)
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{
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u32 tmp1, tmp2, tdcr;
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@ -657,42 +696,18 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
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apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
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}
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static int apic_mmio_write(struct kvm_io_device *this,
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gpa_t address, int len, const void *data)
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static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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{
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struct kvm_lapic *apic = to_lapic(this);
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unsigned int offset = address - apic->base_address;
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unsigned char alignment = offset & 0xf;
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u32 val;
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if (!apic_mmio_in_range(apic, address))
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return -EOPNOTSUPP;
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int ret = 0;
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/*
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* APIC register must be aligned on 128-bits boundary.
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* 32/64/128 bits registers must be accessed thru 32 bits.
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* Refer SDM 8.4.1
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*/
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if (len != 4 || alignment) {
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/* Don't shout loud, $infamous_os would cause only noise. */
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apic_debug("apic write: bad size=%d %lx\n",
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len, (long)address);
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return 0;
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}
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trace_kvm_apic_write(reg, val);
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val = *(u32 *) data;
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/* too common printing */
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if (offset != APIC_EOI)
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apic_debug("%s: offset 0x%x with length 0x%x, and value is "
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"0x%x\n", __func__, offset, len, val);
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offset &= 0xff0;
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trace_kvm_apic_write(offset, val);
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switch (offset) {
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switch (reg) {
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case APIC_ID: /* Local APIC ID */
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apic_set_reg(apic, APIC_ID, val);
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if (!apic_x2apic_mode(apic))
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apic_set_reg(apic, APIC_ID, val);
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else
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ret = 1;
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break;
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case APIC_TASKPRI:
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@ -705,11 +720,17 @@ static int apic_mmio_write(struct kvm_io_device *this,
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break;
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case APIC_LDR:
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apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
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if (!apic_x2apic_mode(apic))
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apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
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else
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ret = 1;
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break;
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case APIC_DFR:
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apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
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if (!apic_x2apic_mode(apic))
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apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
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else
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ret = 1;
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break;
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case APIC_SPIV: {
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@ -739,7 +760,9 @@ static int apic_mmio_write(struct kvm_io_device *this,
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break;
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case APIC_ICR2:
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apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
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if (!apic_x2apic_mode(apic))
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val &= 0xff000000;
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apic_set_reg(apic, APIC_ICR2, val);
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break;
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case APIC_LVT0:
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@ -753,8 +776,8 @@ static int apic_mmio_write(struct kvm_io_device *this,
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if (!apic_sw_enabled(apic))
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val |= APIC_LVT_MASKED;
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val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
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apic_set_reg(apic, offset, val);
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val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
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apic_set_reg(apic, reg, val);
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break;
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@ -762,7 +785,7 @@ static int apic_mmio_write(struct kvm_io_device *this,
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hrtimer_cancel(&apic->lapic_timer.timer);
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apic_set_reg(apic, APIC_TMICT, val);
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start_apic_timer(apic);
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return 0;
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break;
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case APIC_TDCR:
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if (val & 4)
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@ -771,11 +794,58 @@ static int apic_mmio_write(struct kvm_io_device *this,
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update_divide_count(apic);
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break;
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case APIC_ESR:
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if (apic_x2apic_mode(apic) && val != 0) {
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printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
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ret = 1;
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}
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break;
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case APIC_SELF_IPI:
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if (apic_x2apic_mode(apic)) {
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apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
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} else
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ret = 1;
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break;
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default:
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apic_debug("Local APIC Write to read-only register %x\n",
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offset);
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ret = 1;
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break;
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}
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if (ret)
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apic_debug("Local APIC Write to read-only register %x\n", reg);
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return ret;
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}
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static int apic_mmio_write(struct kvm_io_device *this,
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gpa_t address, int len, const void *data)
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{
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struct kvm_lapic *apic = to_lapic(this);
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unsigned int offset = address - apic->base_address;
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u32 val;
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if (!apic_mmio_in_range(apic, address))
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return -EOPNOTSUPP;
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/*
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* APIC register must be aligned on 128-bits boundary.
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* 32/64/128 bits registers must be accessed thru 32 bits.
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* Refer SDM 8.4.1
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*/
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if (len != 4 || (offset & 0xf)) {
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/* Don't shout loud, $infamous_os would cause only noise. */
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apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
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return;
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}
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val = *(u32*)data;
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/* too common printing */
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if (offset != APIC_EOI)
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apic_debug("%s: offset 0x%x with length 0x%x, and value is "
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"0x%x\n", __func__, offset, len, val);
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apic_reg_write(apic, offset & 0xff0, val);
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return 0;
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}
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@ -834,6 +904,11 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
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value &= ~MSR_IA32_APICBASE_BSP;
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vcpu->arch.apic_base = value;
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if (apic_x2apic_mode(apic)) {
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u32 id = kvm_apic_id(apic);
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u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
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apic_set_reg(apic, APIC_LDR, ldr);
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}
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apic->base_address = apic->vcpu->arch.apic_base &
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MSR_IA32_APICBASE_BASE;
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@ -1130,3 +1205,35 @@ void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
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vcpu->arch.apic->vapic_addr = vapic_addr;
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}
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int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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u32 reg = (msr - APIC_BASE_MSR) << 4;
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if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
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return 1;
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/* if this is ICR write vector before command */
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if (msr == 0x830)
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apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
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return apic_reg_write(apic, reg, (u32)data);
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}
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int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
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if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
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return 1;
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if (apic_reg_read(apic, reg, 4, &low))
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return 1;
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if (msr == 0x830)
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apic_reg_read(apic, APIC_ICR2, 4, &high);
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*data = (((u64)high) << 32) | low;
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return 0;
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}
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@ -46,4 +46,6 @@ void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
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void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
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void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
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int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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#endif
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@ -867,6 +867,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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case MSR_IA32_APICBASE:
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kvm_set_apic_base(vcpu, data);
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break;
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case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
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return kvm_x2apic_msr_write(vcpu, msr, data);
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case MSR_IA32_MISC_ENABLE:
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vcpu->arch.ia32_misc_enable_msr = data;
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break;
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@ -1065,6 +1067,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
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case MSR_IA32_APICBASE:
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data = kvm_get_apic_base(vcpu);
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break;
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case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
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return kvm_x2apic_msr_read(vcpu, msr, pdata);
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break;
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case MSR_IA32_MISC_ENABLE:
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data = vcpu->arch.ia32_misc_enable_msr;
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break;
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@ -1469,7 +1474,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
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0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
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0 /* Reserved, DCA */ | F(XMM4_1) |
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F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
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F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
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0 /* Reserved, XSAVE, OSXSAVE */;
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/* cpuid 0x80000001.ecx */
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const u32 kvm_supported_word6_x86_features =
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