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ARM: dts: dra7xx-clocks: Add missing clocks for second PCIe PHY instance

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Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.

Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Kishon Vijay Abraham I 2014-07-14 16:12:20 +05:30 committed by Tony Lindgren
parent b700f42c86
commit 00b0af5b68
1 changed files with 24 additions and 0 deletions
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24
arch/arm/boot/dts/dra7xx-clocks.dtsi
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@ -1173,6 +1173,14 @@
ti,bit-shift = <8>;
};
optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <8>;
};
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@ -1191,6 +1199,14 @@
ti,bit-shift = <9>;
};
optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <9>;
};
optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
@ -1199,6 +1215,14 @@
ti,bit-shift = <10>;
};
optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
compatible = "ti,gate-clock";
clocks = <&optfclk_pciephy_div>;
#clock-cells = <0>;
reg = <0x13b8>;
ti,bit-shift = <10>;
};
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";