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dmaengine: fsl-edma: support little endian for edma driver
Our platforms with below registers(CHCFG0 - CHCFG15) of eDMA *-----------------------------------------------------------* | Offset | Big endian Register| Little endian Register| |--------------|--------------------|-----------------------| | 0x0 | CHCFG0 | CHCFG3 | |--------------|--------------------|-----------------------| | 0x1 | CHCFG1 | CHCFG2 | |--------------|--------------------|-----------------------| | 0x2 | CHCFG2 | CHCFG1 | |--------------|--------------------|-----------------------| | 0x3 | CHCFG3 | CHCFG0 | |--------------|--------------------|-----------------------| | ... | ...... | ...... | |--------------|--------------------|-----------------------| | 0xC | CHCFG12 | CHCFG15 | |--------------|--------------------|-----------------------| | 0xD | CHCFG13 | CHCFG14 | |--------------|--------------------|-----------------------| | 0xE | CHCFG14 | CHCFG13 | |--------------|--------------------|-----------------------| | 0xF | CHCFG15 | CHCFG12 | *-----------------------------------------------------------* Current eDMA driver does not support Little endian, so this patch is to improve edma driver to support little endian. Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -83,9 +83,14 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
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u32 ch = fsl_chan->vchan.chan.chan_id;
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void __iomem *muxaddr;
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unsigned int chans_per_mux, ch_off;
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int endian_diff[4] = {3, 1, -1, -3};
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chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
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ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
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if (!fsl_chan->edma->big_endian)
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ch_off += endian_diff[ch_off % 4];
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muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
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slot = EDMAMUX_CHCFG_SOURCE(slot);
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