ARM: mvebu: fix cpuidle implementation to work on big-endian systems
On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.
While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.
Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.
Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 20:09:25 +08:00
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/*
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* Copyright (C) 2014 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Gregory Clement <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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2014-10-30 19:39:42 +08:00
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ENTRY(armada_38x_scu_power_up)
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mrc p15, 4, r1, c15, c0 @ get SCU base address
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orr r1, r1, #0x8 @ SCU CPU Power Status Register
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ARM: mvebu: prefix coprocessor operand with p
In every other instance where mrc is used the coprocessor operand
is prefix with p (e.g. p15). Use the p prefix in this case too.
This fixes a build issue when using LLVM's integrated assembler:
arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for instruction
mrc 15, 0, r3, cr0, cr0, 5
^
arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
^
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-11 15:54:03 +08:00
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mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
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2014-10-30 19:39:42 +08:00
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and r0, r0, #15
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add r1, r1, r0
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mov r0, #0x0
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strb r0, [r1] @ switch SCU power state to Normal mode
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ret lr
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ENDPROC(armada_38x_scu_power_up)
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ARM: mvebu: fix cpuidle implementation to work on big-endian systems
On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.
While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.
Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.
Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 20:09:25 +08:00
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/*
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* This is the entry point through which CPUs exiting cpuidle deep
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* idle state are going.
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*/
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ENTRY(armada_370_xp_cpu_resume)
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ARM_BE8(setend be ) @ go BE8 if entered LE
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2014-11-22 00:00:09 +08:00
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/*
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* Disable the MMU that might have been enabled in BootROM if
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* this code is used in the resume path of a suspend/resume
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* cycle.
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*/
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mrc p15, 0, r1, c1, c0, 0
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bic r1, #1
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mcr p15, 0, r1, c1, c0, 0
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ARM: mvebu: fix cpuidle implementation to work on big-endian systems
On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.
While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.
Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.
Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 20:09:25 +08:00
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bl ll_add_cpu_to_smp_group
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bl ll_enable_coherency
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b cpu_resume
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ENDPROC(armada_370_xp_cpu_resume)
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2014-07-23 21:00:52 +08:00
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ENTRY(armada_38x_cpu_resume)
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/* do we need it for Armada 38x*/
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ARM_BE8(setend be ) @ go BE8 if entered LE
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bl v7_invalidate_l1
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2014-10-30 19:39:42 +08:00
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bl armada_38x_scu_power_up
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2014-07-23 21:00:52 +08:00
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b cpu_resume
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ENDPROC(armada_38x_cpu_resume)
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2014-07-23 21:00:40 +08:00
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.global mvebu_boot_wa_start
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.global mvebu_boot_wa_end
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/* The following code will be executed from SRAM */
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ENTRY(mvebu_boot_wa_start)
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ARM_BE8(setend be)
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adr r0, 1f
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ldr r0, [r0] @ load the address of the
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@ resume register
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ldr r0, [r0] @ load the value in the
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@ resume register
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ARM_BE8(rev r0, r0) @ the value is stored LE
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mov pc, r0 @ jump to this value
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/*
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* the last word of this piece of code will be filled by the physical
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* address of the boot address register just after being copied in SRAM
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*/
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1:
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.long .
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mvebu_boot_wa_end:
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ENDPROC(mvebu_boot_wa_end)
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