2005-04-17 06:20:36 +08:00
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/*
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* Definitions for Intel 82593 CSMA/CD Core LAN Controller
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* The definitions are taken from the 1992 users manual with Intel
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* order number 297125-001.
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*
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* /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
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*
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* Copyright 1994, Anders Klemets <klemets@it.kth.se>
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*
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* HISTORY
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* i82593.h,v
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2005-11-17 05:09:53 +08:00
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* Revision 1.4 2005/11/4 09:15:00 baroniunas
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* Modified copyright with permission of author as follows:
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*
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* "If I82539.H is the only file with my copyright statement
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* that is included in the Source Forge project, then you have
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* my approval to change the copyright statement to be a GPL
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* license, in the way you proposed on October 10."
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*
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2005-04-17 06:20:36 +08:00
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* Revision 1.1 1996/07/17 15:23:12 root
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* Initial revision
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*
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* Revision 1.3 1995/04/05 15:13:58 adj
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* Initial alpha release
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*
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* Revision 1.2 1994/06/16 23:57:31 klemets
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* Mirrored all the fields in the configuration block.
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*
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* Revision 1.1 1994/06/02 20:25:34 klemets
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* Initial revision
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*
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*
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*/
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#ifndef _I82593_H
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#define _I82593_H
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/* Intel 82593 CSMA/CD Core LAN Controller */
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/* Port 0 Command Register definitions */
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/* Execution operations */
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#define OP0_NOP 0 /* CHNL = 0 */
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#define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
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#define OP0_IA_SETUP 1
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#define OP0_CONFIGURE 2
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#define OP0_MC_SETUP 3
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#define OP0_TRANSMIT 4
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#define OP0_TDR 5
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#define OP0_DUMP 6
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#define OP0_DIAGNOSE 7
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#define OP0_TRANSMIT_NO_CRC 9
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#define OP0_RETRANSMIT 12
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#define OP0_ABORT 13
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/* Reception operations */
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#define OP0_RCV_ENABLE 8
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#define OP0_RCV_DISABLE 10
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#define OP0_STOP_RCV 11
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/* Status pointer control operations */
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#define OP0_FIX_PTR 15 /* CHNL = 1 */
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#define OP0_RLS_PTR 15 /* CHNL = 0 */
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#define OP0_RESET 14
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#define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
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#define CR0_STATUS_0 0x00
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#define CR0_STATUS_1 0x20
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#define CR0_STATUS_2 0x40
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#define CR0_STATUS_3 0x60
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#define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
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/* Port 0 Status Register definitions */
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#define SR0_NO_RESULT 0 /* dummy */
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#define SR0_EVENT_MASK 0x0f
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#define SR0_IA_SETUP_DONE 1
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#define SR0_CONFIGURE_DONE 2
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#define SR0_MC_SETUP_DONE 3
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#define SR0_TRANSMIT_DONE 4
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#define SR0_TDR_DONE 5
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#define SR0_DUMP_DONE 6
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#define SR0_DIAGNOSE_PASSED 7
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#define SR0_TRANSMIT_NO_CRC_DONE 9
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#define SR0_RETRANSMIT_DONE 12
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#define SR0_EXECUTION_ABORTED 13
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#define SR0_END_OF_FRAME 8
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#define SR0_RECEPTION_ABORTED 10
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#define SR0_DIAGNOSE_FAILED 15
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#define SR0_STOP_REG_HIT 11
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#define SR0_CHNL (1 << 4)
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#define SR0_EXECUTION (1 << 5)
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#define SR0_RECEPTION (1 << 6)
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#define SR0_INTERRUPT (1 << 7)
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#define SR0_BOTH_RX_TX (SR0_EXECUTION | SR0_RECEPTION)
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#define SR3_EXEC_STATE_MASK 0x03
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#define SR3_EXEC_IDLE 0
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#define SR3_TX_ABORT_IN_PROGRESS 1
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#define SR3_EXEC_ACTIVE 2
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#define SR3_ABORT_IN_PROGRESS 3
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#define SR3_EXEC_CHNL (1 << 2)
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#define SR3_STP_ON_NO_RSRC (1 << 3)
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#define SR3_RCVING_NO_RSRC (1 << 4)
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#define SR3_RCV_STATE_MASK 0x60
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#define SR3_RCV_IDLE 0x00
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#define SR3_RCV_READY 0x20
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#define SR3_RCV_ACTIVE 0x40
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#define SR3_RCV_STOP_IN_PROG 0x60
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#define SR3_RCV_CHNL (1 << 7)
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/* Port 1 Command Register definitions */
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#define OP1_NOP 0
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#define OP1_SWIT_TO_PORT_0 1
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#define OP1_INT_DISABLE 2
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#define OP1_INT_ENABLE 3
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#define OP1_SET_TS 5
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#define OP1_RST_TS 7
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#define OP1_POWER_DOWN 8
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#define OP1_RESET_RING_MNGMT 11
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#define OP1_RESET 14
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#define OP1_SEL_RST 15
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#define CR1_STATUS_4 0x00
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#define CR1_STATUS_5 0x20
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#define CR1_STATUS_6 0x40
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#define CR1_STOP_REG_UPDATE (1 << 7)
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/* Receive frame status bits */
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#define RX_RCLD (1 << 0)
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#define RX_IA_MATCH (1 << 1)
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#define RX_NO_AD_MATCH (1 << 2)
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#define RX_NO_SFD (1 << 3)
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#define RX_SRT_FRM (1 << 7)
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#define RX_OVRRUN (1 << 8)
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#define RX_ALG_ERR (1 << 10)
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#define RX_CRC_ERR (1 << 11)
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#define RX_LEN_ERR (1 << 12)
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#define RX_RCV_OK (1 << 13)
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#define RX_TYP_LEN (1 << 15)
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/* Transmit status bits */
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#define TX_NCOL_MASK 0x0f
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#define TX_FRTL (1 << 4)
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#define TX_MAX_COL (1 << 5)
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#define TX_HRT_BEAT (1 << 6)
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#define TX_DEFER (1 << 7)
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#define TX_UND_RUN (1 << 8)
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#define TX_LOST_CTS (1 << 9)
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#define TX_LOST_CRS (1 << 10)
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#define TX_LTCOL (1 << 11)
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#define TX_OK (1 << 13)
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#define TX_COLL (1 << 15)
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struct i82593_conf_block {
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u_char fifo_limit : 4,
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forgnesi : 1,
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fifo_32 : 1,
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d6mod : 1,
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throttle_enb : 1;
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u_char throttle : 6,
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cntrxint : 1,
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contin : 1;
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u_char addr_len : 3,
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acloc : 1,
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preamb_len : 2,
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loopback : 2;
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u_char lin_prio : 3,
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tbofstop : 1,
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exp_prio : 3,
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bof_met : 1;
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u_char : 4,
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ifrm_spc : 4;
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u_char : 5,
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slottim_low : 3;
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u_char slottim_hi : 3,
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: 1,
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max_retr : 4;
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u_char prmisc : 1,
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bc_dis : 1,
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: 1,
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crs_1 : 1,
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nocrc_ins : 1,
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crc_1632 : 1,
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: 1,
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crs_cdt : 1;
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u_char cs_filter : 3,
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crs_src : 1,
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cd_filter : 3,
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: 1;
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u_char : 2,
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min_fr_len : 6;
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u_char lng_typ : 1,
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lng_fld : 1,
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rxcrc_xf : 1,
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artx : 1,
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sarec : 1,
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tx_jabber : 1, /* why is this called max_len in the manual? */
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hash_1 : 1,
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lbpkpol : 1;
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u_char : 6,
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fdx : 1,
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: 1;
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u_char dummy_6 : 6, /* supposed to be ones */
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mult_ia : 1,
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dis_bof : 1;
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u_char dummy_1 : 1, /* supposed to be one */
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tx_ifs_retrig : 2,
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mc_all : 1,
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rcv_mon : 2,
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frag_acpt : 1,
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tstrttrs : 1;
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u_char fretx : 1,
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runt_eop : 1,
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hw_sw_pin : 1,
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big_endn : 1,
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syncrqs : 1,
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sttlen : 1,
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tx_eop : 1,
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rx_eop : 1;
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u_char rbuf_size : 5,
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rcvstop : 1,
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: 2;
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};
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#define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
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#endif /* _I82593_H */
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