2019-05-27 14:55:01 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2014-02-27 23:24:15 +08:00
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/*
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* Copyright (C) 2014 STMicroelectronics (R&D) Limited
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*/
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/*
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* Authors:
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* Stephen Gallimore <stephen.gallimore@st.com>,
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* Pankaj Dev <pankaj.dev@st.com>.
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*/
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#include <linux/slab.h>
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#include <linux/of_address.h>
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2015-06-20 06:00:46 +08:00
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#include <linux/clk.h>
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2014-02-27 23:24:15 +08:00
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#include <linux/clk-provider.h>
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2015-10-07 17:08:56 +08:00
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#include <linux/iopoll.h>
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2014-02-27 23:24:15 +08:00
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#include "clkgen.h"
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static DEFINE_SPINLOCK(clkgena_c32_odf_lock);
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2015-10-07 17:08:57 +08:00
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DEFINE_SPINLOCK(clkgen_a9_lock);
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2014-02-27 23:24:15 +08:00
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/*
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* PLL configuration register bits for PLL3200 C32
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*/
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#define C32_NDIV_MASK (0xff)
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#define C32_IDF_MASK (0x7)
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#define C32_ODF_MASK (0x3f)
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#define C32_LDF_MASK (0x7f)
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2015-10-07 17:08:57 +08:00
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#define C32_CP_MASK (0x1f)
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2014-02-27 23:24:15 +08:00
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#define C32_MAX_ODFS (4)
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2015-10-07 17:08:58 +08:00
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/*
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* PLL configuration register bits for PLL4600 C28
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*/
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#define C28_NDIV_MASK (0xff)
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#define C28_IDF_MASK (0x7)
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#define C28_ODF_MASK (0x3f)
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2014-02-27 23:24:15 +08:00
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struct clkgen_pll_data {
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struct clkgen_field pdn_status;
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2015-10-07 17:08:56 +08:00
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struct clkgen_field pdn_ctrl;
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2014-02-27 23:24:15 +08:00
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struct clkgen_field locked_status;
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struct clkgen_field mdiv;
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struct clkgen_field ndiv;
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struct clkgen_field pdiv;
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struct clkgen_field idf;
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struct clkgen_field ldf;
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2015-10-07 17:08:57 +08:00
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struct clkgen_field cp;
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2014-02-27 23:24:15 +08:00
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unsigned int num_odfs;
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struct clkgen_field odf[C32_MAX_ODFS];
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struct clkgen_field odf_gate[C32_MAX_ODFS];
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2015-10-07 17:08:57 +08:00
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bool switch2pll_en;
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struct clkgen_field switch2pll;
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spinlock_t *lock;
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2014-02-27 23:24:15 +08:00
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const struct clk_ops *ops;
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};
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static const struct clk_ops stm_pll3200c32_ops;
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2015-10-07 17:08:57 +08:00
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static const struct clk_ops stm_pll3200c32_a9_ops;
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2015-10-07 17:08:58 +08:00
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static const struct clk_ops stm_pll4600c28_ops;
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2014-02-27 23:24:15 +08:00
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2015-09-16 15:42:59 +08:00
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static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
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2014-07-15 23:20:27 +08:00
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/* 407 C0 PLL0 */
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.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
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2015-10-07 17:08:56 +08:00
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.pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
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2014-07-15 23:20:27 +08:00
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.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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2015-09-16 15:42:59 +08:00
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static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
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2014-07-15 23:20:27 +08:00
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/* 407 C0 PLL1 */
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.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
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2015-10-07 17:08:56 +08:00
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.pdn_ctrl = CLKGEN_FIELD(0x2c8, 0x1, 8),
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2014-07-15 23:20:27 +08:00
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.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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2014-07-15 23:20:29 +08:00
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static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
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/* 407 A9 */
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.pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
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2015-10-07 17:08:56 +08:00
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.pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
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2014-07-15 23:20:29 +08:00
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.locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
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.idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
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.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
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2015-10-07 17:08:57 +08:00
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.switch2pll_en = true,
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.cp = CLKGEN_FIELD(0x1a8, C32_CP_MASK, 1),
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.switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
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.lock = &clkgen_a9_lock,
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.ops = &stm_pll3200c32_a9_ops,
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2014-07-15 23:20:29 +08:00
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};
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2015-10-07 17:08:58 +08:00
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static struct clkgen_pll_data st_pll4600c28_418_a9 = {
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/* 418 A9 */
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.pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
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.pdn_ctrl = CLKGEN_FIELD(0x1a8, 0x1, 0),
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.locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
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.ndiv = CLKGEN_FIELD(0x1b0, C28_NDIV_MASK, 0),
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.idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x1b0, C28_ODF_MASK, 8) },
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.odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
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.switch2pll_en = true,
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.switch2pll = CLKGEN_FIELD(0x1a4, 0x1, 1),
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.lock = &clkgen_a9_lock,
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.ops = &stm_pll4600c28_ops,
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};
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2014-02-27 23:24:15 +08:00
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/**
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* DOC: Clock Generated by PLL, rate set and enabled by bootloader
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable/disable only ensures parent is enabled
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* rate - rate is fixed. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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/**
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* PLL clock that is integrated in the ClockGenA instances on the STiH415
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* and STiH416.
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*
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* @hw: handle between common and hardware-specific interfaces.
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* @type: PLL instance type.
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* @regs_base: base of the PLL configuration register(s).
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*
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*/
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struct clkgen_pll {
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struct clk_hw hw;
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struct clkgen_pll_data *data;
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void __iomem *regs_base;
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2015-10-07 17:08:57 +08:00
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spinlock_t *lock;
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u32 ndiv;
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u32 idf;
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u32 odf;
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u32 cp;
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2014-02-27 23:24:15 +08:00
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};
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#define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw)
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2015-10-07 17:08:57 +08:00
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struct stm_pll {
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unsigned long mdiv;
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unsigned long ndiv;
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unsigned long pdiv;
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unsigned long odf;
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unsigned long idf;
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unsigned long ldf;
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unsigned long cp;
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};
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2014-02-27 23:24:15 +08:00
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static int clkgen_pll_is_locked(struct clk_hw *hw)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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u32 locked = CLKGEN_READ(pll, locked_status);
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return !!locked;
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}
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static int clkgen_pll_is_enabled(struct clk_hw *hw)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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u32 poweroff = CLKGEN_READ(pll, pdn_status);
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return !poweroff;
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}
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2015-10-07 17:08:57 +08:00
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static int __clkgen_pll_enable(struct clk_hw *hw)
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2015-10-07 17:08:56 +08:00
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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void __iomem *base = pll->regs_base;
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struct clkgen_field *field = &pll->data->locked_status;
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int ret = 0;
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u32 reg;
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if (clkgen_pll_is_enabled(hw))
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return 0;
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CLKGEN_WRITE(pll, pdn_ctrl, 0);
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ret = readl_relaxed_poll_timeout(base + field->offset, reg,
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!!((reg >> field->shift) & field->mask), 0, 10000);
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2015-10-07 17:08:57 +08:00
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if (!ret) {
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if (pll->data->switch2pll_en)
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CLKGEN_WRITE(pll, switch2pll, 0);
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2015-10-07 17:08:56 +08:00
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pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__);
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2015-10-07 17:08:57 +08:00
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}
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2015-10-07 17:08:56 +08:00
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return ret;
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}
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2015-10-07 17:08:57 +08:00
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static int clkgen_pll_enable(struct clk_hw *hw)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long flags = 0;
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int ret = 0;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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ret = __clkgen_pll_enable(hw);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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return ret;
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}
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static void __clkgen_pll_disable(struct clk_hw *hw)
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2015-10-07 17:08:56 +08:00
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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if (!clkgen_pll_is_enabled(hw))
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return;
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2015-10-07 17:08:57 +08:00
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if (pll->data->switch2pll_en)
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CLKGEN_WRITE(pll, switch2pll, 1);
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2015-10-07 17:08:56 +08:00
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CLKGEN_WRITE(pll, pdn_ctrl, 1);
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pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__);
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}
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2015-10-07 17:08:57 +08:00
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static void clkgen_pll_disable(struct clk_hw *hw)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long flags = 0;
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if (pll->lock)
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spin_lock_irqsave(pll->lock, flags);
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__clkgen_pll_disable(hw);
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if (pll->lock)
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spin_unlock_irqrestore(pll->lock, flags);
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}
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static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
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struct stm_pll *pll)
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{
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unsigned long i, n;
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unsigned long deviation = ~0;
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unsigned long new_freq;
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long new_deviation;
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/* Charge pump table: highest ndiv value for cp=6 to 25 */
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static const unsigned char cp_table[] = {
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48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
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128, 136, 144, 152, 160, 168, 176, 184, 192
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};
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/* Output clock range: 800Mhz to 1600Mhz */
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if (output < 800000000 || output > 1600000000)
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return -EINVAL;
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input /= 1000;
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output /= 1000;
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for (i = 1; i <= 7 && deviation; i++) {
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n = i * output / (2 * input);
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/* Checks */
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if (n < 8)
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continue;
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if (n > 200)
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break;
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new_freq = (input * 2 * n) / i;
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new_deviation = abs(new_freq - output);
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if (!new_deviation || new_deviation < deviation) {
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pll->idf = i;
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pll->ndiv = n;
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deviation = new_deviation;
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}
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}
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if (deviation == ~0) /* No solution found */
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return -EINVAL;
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/* Computing recommended charge pump value */
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for (pll->cp = 6; pll->ndiv > cp_table[pll->cp-6]; (pll->cp)++)
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;
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return 0;
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}
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static int clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll,
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unsigned long *rate)
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{
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if (!pll->idf)
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pll->idf = 1;
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*rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000;
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return 0;
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}
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2015-05-02 03:45:53 +08:00
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static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
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2014-02-27 23:24:15 +08:00
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unsigned long parent_rate)
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{
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struct clkgen_pll *pll = to_clkgen_pll(hw);
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unsigned long ndiv, idf;
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unsigned long rate = 0;
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if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
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return 0;
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|
|
|
|
|
|
|
ndiv = CLKGEN_READ(pll, ndiv);
|
|
|
|
idf = CLKGEN_READ(pll, idf);
|
|
|
|
|
|
|
|
if (idf)
|
|
|
|
/* Note: input is divided to avoid overflow */
|
|
|
|
rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000;
|
|
|
|
|
2015-08-13 02:42:23 +08:00
|
|
|
pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
|
2014-02-27 23:24:15 +08:00
|
|
|
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
2015-10-07 17:08:57 +08:00
|
|
|
static long round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *prate)
|
|
|
|
{
|
|
|
|
struct stm_pll params;
|
|
|
|
|
|
|
|
if (!clk_pll3200c32_get_params(*prate, rate, ¶ms))
|
|
|
|
clk_pll3200c32_get_rate(*prate, ¶ms, &rate);
|
|
|
|
else {
|
|
|
|
pr_debug("%s: %s rate %ld Invalid\n", __func__,
|
|
|
|
__clk_get_name(hw->clk), rate);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
|
|
|
|
__func__, __clk_get_name(hw->clk),
|
|
|
|
rate, (unsigned int)params.ndiv,
|
|
|
|
(unsigned int)params.idf);
|
|
|
|
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int set_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clkgen_pll *pll = to_clkgen_pll(hw);
|
|
|
|
struct stm_pll params;
|
|
|
|
long hwrate = 0;
|
|
|
|
unsigned long flags = 0;
|
|
|
|
|
|
|
|
if (!rate || !parent_rate)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!clk_pll3200c32_get_params(parent_rate, rate, ¶ms))
|
|
|
|
clk_pll3200c32_get_rate(parent_rate, ¶ms, &hwrate);
|
|
|
|
|
|
|
|
pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
|
|
|
|
__func__, __clk_get_name(hw->clk),
|
|
|
|
hwrate, (unsigned int)params.ndiv,
|
|
|
|
(unsigned int)params.idf);
|
|
|
|
|
|
|
|
if (!hwrate)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pll->ndiv = params.ndiv;
|
|
|
|
pll->idf = params.idf;
|
|
|
|
pll->cp = params.cp;
|
|
|
|
|
|
|
|
__clkgen_pll_disable(hw);
|
|
|
|
|
|
|
|
if (pll->lock)
|
|
|
|
spin_lock_irqsave(pll->lock, flags);
|
|
|
|
|
|
|
|
CLKGEN_WRITE(pll, ndiv, pll->ndiv);
|
|
|
|
CLKGEN_WRITE(pll, idf, pll->idf);
|
|
|
|
CLKGEN_WRITE(pll, cp, pll->cp);
|
|
|
|
|
|
|
|
if (pll->lock)
|
|
|
|
spin_unlock_irqrestore(pll->lock, flags);
|
|
|
|
|
|
|
|
__clkgen_pll_enable(hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-07 17:08:58 +08:00
|
|
|
/* PLL output structure
|
|
|
|
* FVCO >> /2 >> FVCOBY2 (no output)
|
|
|
|
* |> Divider (ODF) >> PHI
|
|
|
|
*
|
|
|
|
* FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
|
|
|
|
*
|
|
|
|
* Rules:
|
|
|
|
* 4Mhz <= INFF input <= 350Mhz
|
|
|
|
* 4Mhz <= INFIN (INFF / IDF) <= 50Mhz
|
|
|
|
* 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
|
|
|
|
* 1 <= i (register/dec value for IDF) <= 7
|
|
|
|
* 8 <= n (register/dec value for NDIV) <= 246
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
|
|
|
|
struct stm_pll *pll)
|
|
|
|
{
|
|
|
|
|
|
|
|
unsigned long i, infin, n;
|
|
|
|
unsigned long deviation = ~0;
|
|
|
|
unsigned long new_freq, new_deviation;
|
|
|
|
|
|
|
|
/* Output clock range: 19Mhz to 3000Mhz */
|
|
|
|
if (output < 19000000 || output > 3000000000u)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* For better jitter, IDF should be smallest and NDIV must be maximum */
|
|
|
|
for (i = 1; i <= 7 && deviation; i++) {
|
|
|
|
/* INFIN checks */
|
|
|
|
infin = input / i;
|
|
|
|
if (infin < 4000000 || infin > 50000000)
|
|
|
|
continue; /* Invalid case */
|
|
|
|
|
|
|
|
n = output / (infin * 2);
|
|
|
|
if (n < 8 || n > 246)
|
|
|
|
continue; /* Invalid case */
|
|
|
|
if (n < 246)
|
|
|
|
n++; /* To work around 'y' when n=x.y */
|
|
|
|
|
|
|
|
for (; n >= 8 && deviation; n--) {
|
|
|
|
new_freq = infin * 2 * n;
|
|
|
|
if (new_freq < output)
|
|
|
|
break; /* Optimization: shorting loop */
|
|
|
|
|
|
|
|
new_deviation = new_freq - output;
|
|
|
|
if (!new_deviation || new_deviation < deviation) {
|
|
|
|
pll->idf = i;
|
|
|
|
pll->ndiv = n;
|
|
|
|
deviation = new_deviation;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (deviation == ~0) /* No solution found */
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll,
|
|
|
|
unsigned long *rate)
|
|
|
|
{
|
|
|
|
if (!pll->idf)
|
|
|
|
pll->idf = 1;
|
|
|
|
|
|
|
|
*rate = (input / pll->idf) * 2 * pll->ndiv;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clkgen_pll *pll = to_clkgen_pll(hw);
|
|
|
|
struct stm_pll params;
|
|
|
|
unsigned long rate;
|
|
|
|
|
|
|
|
if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
params.ndiv = CLKGEN_READ(pll, ndiv);
|
|
|
|
params.idf = CLKGEN_READ(pll, idf);
|
|
|
|
|
|
|
|
clk_pll4600c28_get_rate(parent_rate, ¶ms, &rate);
|
|
|
|
|
|
|
|
pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate);
|
|
|
|
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static long round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long *prate)
|
|
|
|
{
|
|
|
|
struct stm_pll params;
|
|
|
|
|
|
|
|
if (!clk_pll4600c28_get_params(*prate, rate, ¶ms)) {
|
|
|
|
clk_pll4600c28_get_rate(*prate, ¶ms, &rate);
|
|
|
|
} else {
|
|
|
|
pr_debug("%s: %s rate %ld Invalid\n", __func__,
|
|
|
|
__clk_get_name(hw->clk), rate);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_debug("%s: %s new rate %ld [ndiv=%u] [idf=%u]\n",
|
|
|
|
__func__, __clk_get_name(hw->clk),
|
|
|
|
rate, (unsigned int)params.ndiv,
|
|
|
|
(unsigned int)params.idf);
|
|
|
|
|
|
|
|
return rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int set_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clkgen_pll *pll = to_clkgen_pll(hw);
|
|
|
|
struct stm_pll params;
|
|
|
|
long hwrate;
|
|
|
|
unsigned long flags = 0;
|
|
|
|
|
|
|
|
if (!rate || !parent_rate)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!clk_pll4600c28_get_params(parent_rate, rate, ¶ms)) {
|
|
|
|
clk_pll4600c28_get_rate(parent_rate, ¶ms, &hwrate);
|
|
|
|
} else {
|
|
|
|
pr_debug("%s: %s rate %ld Invalid\n", __func__,
|
|
|
|
__clk_get_name(hw->clk), rate);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_debug("%s: %s new rate %ld [ndiv=0x%x] [idf=0x%x]\n",
|
|
|
|
__func__, __clk_get_name(hw->clk),
|
|
|
|
hwrate, (unsigned int)params.ndiv,
|
|
|
|
(unsigned int)params.idf);
|
|
|
|
|
|
|
|
if (!hwrate)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pll->ndiv = params.ndiv;
|
|
|
|
pll->idf = params.idf;
|
|
|
|
|
|
|
|
__clkgen_pll_disable(hw);
|
|
|
|
|
|
|
|
if (pll->lock)
|
|
|
|
spin_lock_irqsave(pll->lock, flags);
|
|
|
|
|
|
|
|
CLKGEN_WRITE(pll, ndiv, pll->ndiv);
|
|
|
|
CLKGEN_WRITE(pll, idf, pll->idf);
|
|
|
|
|
|
|
|
if (pll->lock)
|
|
|
|
spin_unlock_irqrestore(pll->lock, flags);
|
|
|
|
|
|
|
|
__clkgen_pll_enable(hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-27 23:24:15 +08:00
|
|
|
static const struct clk_ops stm_pll3200c32_ops = {
|
2015-10-07 17:08:56 +08:00
|
|
|
.enable = clkgen_pll_enable,
|
|
|
|
.disable = clkgen_pll_disable,
|
2014-02-27 23:24:15 +08:00
|
|
|
.is_enabled = clkgen_pll_is_enabled,
|
|
|
|
.recalc_rate = recalc_stm_pll3200c32,
|
|
|
|
};
|
|
|
|
|
2015-10-07 17:08:57 +08:00
|
|
|
static const struct clk_ops stm_pll3200c32_a9_ops = {
|
|
|
|
.enable = clkgen_pll_enable,
|
|
|
|
.disable = clkgen_pll_disable,
|
|
|
|
.is_enabled = clkgen_pll_is_enabled,
|
|
|
|
.recalc_rate = recalc_stm_pll3200c32,
|
|
|
|
.round_rate = round_rate_stm_pll3200c32,
|
|
|
|
.set_rate = set_rate_stm_pll3200c32,
|
|
|
|
};
|
|
|
|
|
2015-10-07 17:08:58 +08:00
|
|
|
static const struct clk_ops stm_pll4600c28_ops = {
|
|
|
|
.enable = clkgen_pll_enable,
|
|
|
|
.disable = clkgen_pll_disable,
|
|
|
|
.is_enabled = clkgen_pll_is_enabled,
|
|
|
|
.recalc_rate = recalc_stm_pll4600c28,
|
|
|
|
.round_rate = round_rate_stm_pll4600c28,
|
|
|
|
.set_rate = set_rate_stm_pll4600c28,
|
|
|
|
};
|
|
|
|
|
2014-02-27 23:24:15 +08:00
|
|
|
static struct clk * __init clkgen_pll_register(const char *parent_name,
|
|
|
|
struct clkgen_pll_data *pll_data,
|
2016-06-07 19:19:27 +08:00
|
|
|
void __iomem *reg, unsigned long pll_flags,
|
2015-10-07 17:08:57 +08:00
|
|
|
const char *clk_name, spinlock_t *lock)
|
2014-02-27 23:24:15 +08:00
|
|
|
{
|
|
|
|
struct clkgen_pll *pll;
|
|
|
|
struct clk *clk;
|
|
|
|
struct clk_init_data init;
|
|
|
|
|
|
|
|
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
|
|
|
if (!pll)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
init.name = clk_name;
|
|
|
|
init.ops = pll_data->ops;
|
|
|
|
|
2018-12-07 02:38:31 +08:00
|
|
|
init.flags = pll_flags | CLK_GET_RATE_NOCACHE;
|
2014-02-27 23:24:15 +08:00
|
|
|
init.parent_names = &parent_name;
|
|
|
|
init.num_parents = 1;
|
|
|
|
|
|
|
|
pll->data = pll_data;
|
|
|
|
pll->regs_base = reg;
|
|
|
|
pll->hw.init = &init;
|
2015-10-07 17:08:57 +08:00
|
|
|
pll->lock = lock;
|
2014-02-27 23:24:15 +08:00
|
|
|
|
|
|
|
clk = clk_register(NULL, &pll->hw);
|
|
|
|
if (IS_ERR(clk)) {
|
|
|
|
kfree(pll);
|
|
|
|
return clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_debug("%s: parent %s rate %lu\n",
|
|
|
|
__clk_get_name(clk),
|
|
|
|
__clk_get_name(clk_get_parent(clk)),
|
|
|
|
clk_get_rate(clk));
|
|
|
|
|
|
|
|
return clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __iomem * __init clkgen_get_register_base(
|
|
|
|
struct device_node *np)
|
|
|
|
{
|
|
|
|
struct device_node *pnode;
|
|
|
|
void __iomem *reg = NULL;
|
|
|
|
|
|
|
|
pnode = of_get_parent(np);
|
|
|
|
if (!pnode)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
reg = of_iomap(pnode, 0);
|
|
|
|
|
|
|
|
of_node_put(pnode);
|
|
|
|
return reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct clk * __init clkgen_odf_register(const char *parent_name,
|
2015-05-02 03:45:53 +08:00
|
|
|
void __iomem *reg,
|
2014-02-27 23:24:15 +08:00
|
|
|
struct clkgen_pll_data *pll_data,
|
2016-06-07 19:19:27 +08:00
|
|
|
unsigned long pll_flags, int odf,
|
2014-02-27 23:24:15 +08:00
|
|
|
spinlock_t *odf_lock,
|
|
|
|
const char *odf_name)
|
|
|
|
{
|
|
|
|
struct clk *clk;
|
|
|
|
unsigned long flags;
|
|
|
|
struct clk_gate *gate;
|
|
|
|
struct clk_divider *div;
|
|
|
|
|
2016-06-07 19:19:27 +08:00
|
|
|
flags = pll_flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT;
|
2014-02-27 23:24:15 +08:00
|
|
|
|
|
|
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
|
|
|
if (!gate)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
|
|
|
gate->reg = reg + pll_data->odf_gate[odf].offset;
|
|
|
|
gate->bit_idx = pll_data->odf_gate[odf].shift;
|
|
|
|
gate->lock = odf_lock;
|
|
|
|
|
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
2014-04-22 21:15:54 +08:00
|
|
|
if (!div) {
|
|
|
|
kfree(gate);
|
2014-02-27 23:24:15 +08:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2014-04-22 21:15:54 +08:00
|
|
|
}
|
2014-02-27 23:24:15 +08:00
|
|
|
|
|
|
|
div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
|
|
|
|
div->reg = reg + pll_data->odf[odf].offset;
|
|
|
|
div->shift = pll_data->odf[odf].shift;
|
|
|
|
div->width = fls(pll_data->odf[odf].mask);
|
|
|
|
div->lock = odf_lock;
|
|
|
|
|
|
|
|
clk = clk_register_composite(NULL, odf_name, &parent_name, 1,
|
|
|
|
NULL, NULL,
|
|
|
|
&div->hw, &clk_divider_ops,
|
|
|
|
&gate->hw, &clk_gate_ops,
|
|
|
|
flags);
|
|
|
|
if (IS_ERR(clk))
|
|
|
|
return clk;
|
|
|
|
|
|
|
|
pr_debug("%s: parent %s rate %lu\n",
|
|
|
|
__clk_get_name(clk),
|
|
|
|
__clk_get_name(clk_get_parent(clk)),
|
|
|
|
clk_get_rate(clk));
|
|
|
|
return clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2016-08-29 20:26:54 +08:00
|
|
|
static void __init clkgen_c32_pll_setup(struct device_node *np,
|
|
|
|
struct clkgen_pll_data *data)
|
2014-02-27 23:24:15 +08:00
|
|
|
{
|
|
|
|
struct clk *clk;
|
|
|
|
const char *parent_name, *pll_name;
|
|
|
|
void __iomem *pll_base;
|
|
|
|
int num_odfs, odf;
|
|
|
|
struct clk_onecell_data *clk_data;
|
2016-06-07 19:19:27 +08:00
|
|
|
unsigned long pll_flags = 0;
|
2014-02-27 23:24:15 +08:00
|
|
|
|
|
|
|
|
|
|
|
parent_name = of_clk_get_parent_name(np, 0);
|
|
|
|
if (!parent_name)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pll_base = clkgen_get_register_base(np);
|
|
|
|
if (!pll_base)
|
|
|
|
return;
|
|
|
|
|
2016-06-07 19:19:27 +08:00
|
|
|
of_clk_detect_critical(np, 0, &pll_flags);
|
|
|
|
|
|
|
|
clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
|
|
|
|
np->name, data->lock);
|
2014-02-27 23:24:15 +08:00
|
|
|
if (IS_ERR(clk))
|
|
|
|
return;
|
|
|
|
|
|
|
|
pll_name = __clk_get_name(clk);
|
|
|
|
|
|
|
|
num_odfs = data->num_odfs;
|
|
|
|
|
|
|
|
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
|
|
|
if (!clk_data)
|
|
|
|
return;
|
|
|
|
|
|
|
|
clk_data->clk_num = num_odfs;
|
treewide: kzalloc() -> kcalloc()
The kzalloc() function has a 2-factor argument form, kcalloc(). This
patch replaces cases of:
kzalloc(a * b, gfp)
with:
kcalloc(a * b, gfp)
as well as handling cases of:
kzalloc(a * b * c, gfp)
with:
kzalloc(array3_size(a, b, c), gfp)
as it's slightly less ugly than:
kzalloc_array(array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
kzalloc(4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
type TYPE;
expression THING, E;
@@
(
kzalloc(
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
kzalloc(
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression COUNT;
typedef u8;
typedef __u8;
@@
(
kzalloc(
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
kzalloc(
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
kzalloc(
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
kzalloc(
- sizeof(char) * COUNT
+ COUNT
, ...)
|
kzalloc(
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
identifier SIZE, COUNT;
@@
- kzalloc
+ kcalloc
(
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
kzalloc(
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kzalloc(
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kzalloc(
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kzalloc(
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kzalloc(
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
kzalloc(
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
kzalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
kzalloc(
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
kzalloc(
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
kzalloc(
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
kzalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
identifier STRIDE, SIZE, COUNT;
@@
(
kzalloc(
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kzalloc(
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
kzalloc(C1 * C2 * C3, ...)
|
kzalloc(
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
kzalloc(
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
kzalloc(
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
kzalloc(
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
kzalloc(sizeof(THING) * C2, ...)
|
kzalloc(sizeof(TYPE) * C2, ...)
|
kzalloc(C1 * C2 * C3, ...)
|
kzalloc(C1 * C2, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- kzalloc
+ kcalloc
(
- (E1) * E2
+ E1, E2
, ...)
|
- kzalloc
+ kcalloc
(
- (E1) * (E2)
+ E1, E2
, ...)
|
- kzalloc
+ kcalloc
(
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-13 05:03:40 +08:00
|
|
|
clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
|
2014-02-27 23:24:15 +08:00
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!clk_data->clks)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
for (odf = 0; odf < num_odfs; odf++) {
|
|
|
|
struct clk *clk;
|
|
|
|
const char *clk_name;
|
2016-06-07 19:19:27 +08:00
|
|
|
unsigned long odf_flags = 0;
|
2014-02-27 23:24:15 +08:00
|
|
|
|
|
|
|
if (of_property_read_string_index(np, "clock-output-names",
|
|
|
|
odf, &clk_name))
|
|
|
|
return;
|
|
|
|
|
2016-06-07 19:19:27 +08:00
|
|
|
of_clk_detect_critical(np, odf, &odf_flags);
|
|
|
|
|
|
|
|
clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags,
|
2014-02-27 23:24:15 +08:00
|
|
|
odf, &clkgena_c32_odf_lock, clk_name);
|
|
|
|
if (IS_ERR(clk))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
clk_data->clks[odf] = clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
|
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
|
|
|
kfree(pll_name);
|
|
|
|
kfree(clk_data->clks);
|
|
|
|
kfree(clk_data);
|
|
|
|
}
|
2016-08-29 20:26:54 +08:00
|
|
|
static void __init clkgen_c32_pll0_setup(struct device_node *np)
|
|
|
|
{
|
|
|
|
clkgen_c32_pll_setup(np,
|
|
|
|
(struct clkgen_pll_data *) &st_pll3200c32_cx_0);
|
|
|
|
}
|
|
|
|
CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
|
|
|
|
|
|
|
|
static void __init clkgen_c32_pll1_setup(struct device_node *np)
|
|
|
|
{
|
|
|
|
clkgen_c32_pll_setup(np,
|
|
|
|
(struct clkgen_pll_data *) &st_pll3200c32_cx_1);
|
|
|
|
}
|
|
|
|
CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
|
|
|
|
|
|
|
|
static void __init clkgen_c32_plla9_setup(struct device_node *np)
|
|
|
|
{
|
|
|
|
clkgen_c32_pll_setup(np,
|
|
|
|
(struct clkgen_pll_data *) &st_pll3200c32_407_a9);
|
|
|
|
}
|
|
|
|
CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
|
|
|
|
|
|
|
|
static void __init clkgen_c28_plla9_setup(struct device_node *np)
|
|
|
|
{
|
|
|
|
clkgen_c32_pll_setup(np,
|
|
|
|
(struct clkgen_pll_data *) &st_pll4600c28_418_a9);
|
|
|
|
}
|
|
|
|
CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
|