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48 lines
1.6 KiB
Plaintext
48 lines
1.6 KiB
Plaintext
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* STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
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The IPCC block provides a non blocking signaling mechanism to post and
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retrieve messages in an atomic way between two processors.
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It provides the signaling for N bidirectionnal channels. The number of channels
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(N) can be read from a dedicated register.
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Required properties:
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- compatible: Must be "st,stm32mp1-ipcc"
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- reg: Register address range (base address and length)
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- st,proc-id: Processor id using the mailbox (0 or 1)
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- clocks: Input clock
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- interrupt-names: List of names for the interrupts described by the interrupt
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property. Must contain the following entries:
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- "rx"
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- "tx"
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- "wakeup"
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- interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
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free" and "system wakeup".
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- #mbox-cells: Number of cells required for the mailbox specifier. Must be 1.
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The data contained in the mbox specifier of the "mboxes"
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property in the client node is the mailbox channel index.
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Optional properties:
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- wakeup-source: Flag to indicate whether this device can wake up the system
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Example:
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ipcc: mailbox@4c001000 {
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compatible = "st,stm32mp1-ipcc";
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#mbox-cells = <1>;
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reg = <0x4c001000 0x400>;
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st,proc-id = <0>;
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interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
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<&intc GIC_SPI 101 IRQ_TYPE_NONE>,
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<&aiec 62 1>;
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interrupt-names = "rx", "tx", "wakeup";
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clocks = <&rcc_clk IPCC>;
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wakeup-source;
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}
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Client:
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mbox_test {
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...
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mboxes = <&ipcc 0>, <&ipcc 1>;
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};
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