2015-06-15 19:20:47 +08:00
|
|
|
* MTK MMC controller
|
|
|
|
|
|
|
|
The MTK MSDC can act as a MMC controller
|
|
|
|
to support MMC, SD, and SDIO types of memory cards.
|
|
|
|
|
|
|
|
This file documents differences between the core properties in mmc.txt
|
|
|
|
and the properties used by the msdc driver.
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
|
|
|
|
- interrupts: Should contain MSDC interrupt number
|
|
|
|
- clocks: MSDC source clock, HCLK
|
|
|
|
- clock-names: "source", "hclk"
|
|
|
|
- pinctrl-names: should be "default", "state_uhs"
|
|
|
|
- pinctrl-0: should contain default/high speed pin ctrl
|
|
|
|
- pinctrl-1: should contain uhs mode pin ctrl
|
|
|
|
- vmmc-supply: power to the Core
|
|
|
|
- vqmmc-supply: power to the IO
|
|
|
|
|
2015-10-27 14:24:22 +08:00
|
|
|
Optional properties:
|
|
|
|
- assigned-clocks: PLL of the source clock
|
|
|
|
- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
|
|
|
|
- hs400-ds-delay: HS400 DS delay setting
|
|
|
|
|
2015-06-15 19:20:47 +08:00
|
|
|
Examples:
|
|
|
|
mmc0: mmc@11230000 {
|
|
|
|
compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
|
|
|
|
reg = <0 0x11230000 0 0x108>;
|
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
vmmc-supply = <&mt6397_vemc_3v3_reg>;
|
|
|
|
vqmmc-supply = <&mt6397_vio18_reg>;
|
2015-10-27 14:24:22 +08:00
|
|
|
clocks = <&pericfg CLK_PERI_MSDC30_0>,
|
|
|
|
<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
|
2015-06-15 19:20:47 +08:00
|
|
|
clock-names = "source", "hclk";
|
|
|
|
pinctrl-names = "default", "state_uhs";
|
|
|
|
pinctrl-0 = <&mmc0_pins_default>;
|
|
|
|
pinctrl-1 = <&mmc0_pins_uhs>;
|
2015-10-27 14:24:22 +08:00
|
|
|
assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
|
|
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
|
|
|
|
hs400-ds-delay = <0x14015>;
|
2015-06-15 19:20:47 +08:00
|
|
|
};
|