2011-11-02 18:31:15 +08:00
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/*
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* Samsung's Exynos4210 SoC device tree source
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2010-2011 Linaro Ltd.
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* www.linaro.org
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*
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* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2013-06-17 23:02:08 +08:00
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#include "exynos4.dtsi"
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#include "exynos4210-pinctrl.dtsi"
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2011-11-02 18:31:15 +08:00
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/ {
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compatible = "samsung,exynos4210";
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2012-07-14 09:45:32 +08:00
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aliases {
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2012-09-07 05:14:26 +08:00
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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2012-07-14 09:45:32 +08:00
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};
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2012-11-21 23:22:09 +08:00
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pd_lcd1: lcd1-power-domain@10023CA0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10023CA0 0x20>;
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};
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2011-11-02 18:31:15 +08:00
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gic:interrupt-controller@10490000 {
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2012-02-08 10:42:43 +08:00
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cpu-offset = <0x8000>;
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2011-11-02 18:31:15 +08:00
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};
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2012-07-13 14:25:08 +08:00
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combiner:interrupt-controller@10440000 {
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2013-04-12 21:15:58 +08:00
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samsung,combiner-nr = <16>;
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2012-07-13 14:25:08 +08:00
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interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
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<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
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<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
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<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
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};
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2013-03-09 15:12:35 +08:00
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mct@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupt-controller;
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#interrups-cells = <2>;
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interrupt-parent = <&mct_map>;
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interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
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<4 0>, <5 0>;
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2013-03-09 16:11:38 +08:00
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clocks = <&clock 3>, <&clock 344>;
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clock-names = "fin_pll", "mct";
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2013-03-09 15:12:35 +08:00
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mct_map: mct-map {
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#interrupt-cells = <2>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0x0 0 &gic 0 57 0>,
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<0x1 0 &gic 0 69 0>,
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<0x2 0 &combiner 12 6>,
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<0x3 0 &combiner 12 7>,
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<0x4 0 &gic 0 42 0>,
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<0x5 0 &gic 0 48 0>;
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};
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};
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2013-03-09 16:11:33 +08:00
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clock: clock-controller@0x10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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2012-12-12 13:04:03 +08:00
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&combiner>;
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interrupts = <2 2>, <3 2>;
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};
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2012-09-07 05:14:26 +08:00
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pinctrl_0: pinctrl@11400000 {
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2013-01-03 08:05:42 +08:00
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compatible = "samsung,exynos4210-pinctrl";
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2012-09-07 05:14:26 +08:00
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reg = <0x11400000 0x1000>;
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interrupts = <0 47 0>;
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};
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pinctrl_1: pinctrl@11000000 {
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2013-01-03 08:05:42 +08:00
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compatible = "samsung,exynos4210-pinctrl";
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2012-09-07 05:14:26 +08:00
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reg = <0x11000000 0x1000>;
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interrupts = <0 46 0>;
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wakup_eint: wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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2012-10-11 16:11:18 +08:00
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interrupts = <0 32 0>;
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2012-09-07 05:14:26 +08:00
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};
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};
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pinctrl_2: pinctrl@03860000 {
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2013-01-03 08:05:42 +08:00
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compatible = "samsung,exynos4210-pinctrl";
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2012-09-07 05:14:26 +08:00
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reg = <0x03860000 0x1000>;
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};
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2012-10-29 20:18:01 +08:00
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tmu@100C0000 {
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compatible = "samsung,exynos4210-tmu";
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interrupt-parent = <&combiner>;
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reg = <0x100C0000 0x100>;
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interrupts = <2 4>;
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2013-04-23 22:20:19 +08:00
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clocks = <&clock 383>;
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clock-names = "tmu_apbif";
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status = "disabled";
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2012-10-29 20:18:01 +08:00
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};
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2013-04-04 12:48:45 +08:00
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g2d@12800000 {
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compatible = "samsung,s5pv210-g2d";
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reg = <0x12800000 0x1000>;
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interrupts = <0 89 0>;
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2013-06-10 16:52:24 +08:00
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clocks = <&clock 177>, <&clock 277>;
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clock-names = "sclk_fimg2d", "fimg2d";
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2013-04-04 12:48:45 +08:00
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status = "disabled";
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};
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2011-11-02 18:31:15 +08:00
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};
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