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linux-next/arch/mips/kernel/probes-common.h

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MIPS: tracing: move insn_has_delay_slot to a shared header Currently both kprobes and uprobes code have definitions of the insn_has_delay_slot method. Move it to a separate header as an inline method that each probe-specific method can later use. No functional change intended, although the methods slightly varied in the constraints they set for the methods - the uprobes one was chosen as it is slightly more specific when filtering opcode fields. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14335/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-30 17:33:45 +08:00
/*
* Copyright (C) 2016 Imagination Technologies
MIPS: Update email address for Marcin Nowakowski MIPS is no longer part of Imagination Technologies and my @imgtec.com address will soon stop working. Update any files containing my address as well as the .mailmap to point to my new @mips.com address. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/17579/ Signed-off-by: James Hogan <jhogan@kernel.org>
2017-11-02 18:45:11 +08:00
* Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
MIPS: tracing: move insn_has_delay_slot to a shared header Currently both kprobes and uprobes code have definitions of the insn_has_delay_slot method. Move it to a separate header as an inline method that each probe-specific method can later use. No functional change intended, although the methods slightly varied in the constraints they set for the methods - the uprobes one was chosen as it is slightly more specific when filtering opcode fields. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14335/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-30 17:33:45 +08:00
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __PROBES_COMMON_H
#define __PROBES_COMMON_H
#include <asm/inst.h>
MIPS: tracing: disable uprobe/kprobe on compact branch instructions Current instruction decoder for uprobe/kprobe handler only handles branches with delay slots. For compact branches the behaviour is rather unpredictable - and depending on the encoding of a compact branch instruction may result in one (or more) of: - executing an instruction that follows a branch which wasn't in a delay slot and shouldn't have been executed - incorrectly emulating a branch leading to a jump to a wrong location - unexpected branching out of the single-stepped code and never reaching the breakpoint that should terminate the probe handler Results of these actions are generally unpredictable, but can end up with a probed application or kernel crash, so disable placing probes on compact branches until they are handled properly. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14336/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-30 17:33:46 +08:00
int __insn_is_compact_branch(union mips_instruction insn);
MIPS: tracing: move insn_has_delay_slot to a shared header Currently both kprobes and uprobes code have definitions of the insn_has_delay_slot method. Move it to a separate header as an inline method that each probe-specific method can later use. No functional change intended, although the methods slightly varied in the constraints they set for the methods - the uprobes one was chosen as it is slightly more specific when filtering opcode fields. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14335/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-30 17:33:45 +08:00
static inline int __insn_has_delay_slot(const union mips_instruction insn)
{
switch (insn.i_format.opcode) {
/*
* jr and jalr are in r_format format.
*/
case spec_op:
switch (insn.r_format.func) {
case jalr_op:
case jr_op:
return 1;
}
break;
/*
* This group contains:
* bltz_op, bgez_op, bltzl_op, bgezl_op,
* bltzal_op, bgezal_op, bltzall_op, bgezall_op.
*/
case bcond_op:
switch (insn.i_format.rt) {
case bltz_op:
case bltzl_op:
case bgez_op:
case bgezl_op:
case bltzal_op:
case bltzall_op:
case bgezal_op:
case bgezall_op:
case bposge32_op:
return 1;
}
break;
/*
* These are unconditional and in j_format.
*/
case jal_op:
case j_op:
case beq_op:
case beql_op:
case bne_op:
case bnel_op:
case blez_op: /* not really i_format */
case blezl_op:
case bgtz_op:
case bgtzl_op:
return 1;
/*
* And now the FPA/cp1 branch instructions.
*/
case cop1_op:
#ifdef CONFIG_CPU_CAVIUM_OCTEON
case lwc2_op: /* This is bbit0 on Octeon */
case ldc2_op: /* This is bbit032 on Octeon */
case swc2_op: /* This is bbit1 on Octeon */
case sdc2_op: /* This is bbit132 on Octeon */
#endif
return 1;
}
return 0;
}
#endif /* __PROBES_COMMON_H */
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