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linux-next/arch/arm/boot/dts/meson.dtsi

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ARM: dts: meson: update with SPDX Licence identifier While the text specifies "of the GPL or the X11 license" the actual license text matches the MIT license as specified at [0] [0] https://spdx.org/licenses/MIT.html Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-05-27 21:38:48 +08:00
// SPDX-License-Identifier: GPL-2.0 OR MIT
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
/*
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
/ {
ARM: dts: Kill off skeleton{64}.dtsi Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-01-10 00:26:14 +08:00
#address-cells = <1>;
#size-cells = <1>;
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
interrupt-parent = <&gic>;
ARM: meson: DTS: enable L2 cache This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-18 22:30:35 +08:00
L2: l2-cache-controller@c4200000 {
compatible = "arm,pl310-cache";
reg = <0xc4200000 0x1000>;
cache-unified;
cache-level = <2>;
};
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
cbus: cbus@c1100000 {
compatible = "simple-bus";
reg = <0xc1100000 0x200000>;
ARM: dts: meson: add I2C controller nodes Add nodes for I2C controllers A,B,AO, which are available in both Meson6 and Meson8. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-14 03:32:03 +08:00
#address-cells = <1>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#size-cells = <1>;
ranges = <0x0 0xc1100000 0x200000>;
ARM: dts: meson: switch the clock controller to the HHI register area The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-19 06:52:21 +08:00
hhi: system-controller@4000 {
compatible = "amlogic,meson-hhi-sysctrl",
"simple-mfd",
"syscon";
reg = <0x4000 0x400>;
};
ARM: dts: meson: add SoC information nodes The SoC type and version information is encoded in different register blocks. The SoC type information is part of the "assist" registers. The misc version information is part of the "bootrom" registers. On Meson8, Meson8b and Meson8m2 there is additionally information about the minor version. This information is stored in the "analog top" registers. Add the nodes for these register blocks so we can decode the SoC type and version information. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-09-23 22:14:03 +08:00
assist: assist@7c00 {
compatible = "amlogic,meson-mx-assist", "syscon";
reg = <0x7c00 0x200>;
};
ARM: dts: meson: add the hardware random number generator All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:49 +08:00
hwrng: rng@8100 {
compatible = "amlogic,meson-rng";
reg = <0x8100 0x8>;
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
uart_A: serial@84c0 {
ARM: dts: meson6: use stable UART bindings The UART bindings needs specifying a SoC family, use the meson6 family for the UART nodes like the other nodes. Switch to the stable UART bindings for meson6 by adding a XTAL node and using the proper compatible strings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-21 22:42:12 +08:00
compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
reg = <0x84c0 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
uart_B: serial@84dc {
ARM: dts: meson6: use stable UART bindings The UART bindings needs specifying a SoC family, use the meson6 family for the UART nodes like the other nodes. Switch to the stable UART bindings for meson6 by adding a XTAL node and using the proper compatible strings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-21 22:42:12 +08:00
compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
reg = <0x84dc 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
i2c_A: i2c@8500 {
compatible = "amlogic,meson6-i2c";
reg = <0x8500 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: move the pwm_ab and pwm_cd nodes to meson.dtsi According to the vendor kernel sources these also exist (at the same address) on Meson6 and Meson8. This can be found by running $ grep -R "define PWM_PWM_[A-D]" arch/arm/ in the Amlogic GPL kernel tree (arm-src-kernel-2015-01-15-321cfb5a46). pwm_ef does not seem to exist on older SoCs, so we keep it in meson8b.dtsi for now. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-07-12 06:20:14 +08:00
pwm_ab: pwm@8550 {
compatible = "amlogic,meson-pwm";
reg = <0x8550 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@8650 {
compatible = "amlogic,meson-pwm";
reg = <0x8650 0x10>;
#pwm-cells = <3>;
status = "disabled";
};
ARM: dts: meson: add the SAR ADC This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:47 +08:00
saradc: adc@8680 {
compatible = "amlogic,meson-saradc";
reg = <0x8680 0x34>;
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
uart_C: serial@8700 {
ARM: dts: meson6: use stable UART bindings The UART bindings needs specifying a SoC family, use the meson6 family for the UART nodes like the other nodes. Switch to the stable UART bindings for meson6 by adding a XTAL node and using the proper compatible strings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-21 22:42:12 +08:00
compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
reg = <0x8700 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
i2c_B: i2c@87c0 {
compatible = "amlogic,meson6-i2c";
reg = <0x87c0 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:50 +08:00
usb0_phy: phy@8800 {
compatible = "amlogic,meson-mx-usb2-phy";
#phy-cells = <0>;
reg = <0x8800 0x20>;
status = "disabled";
};
usb1_phy: phy@8820 {
compatible = "amlogic,meson-mx-usb2-phy";
#phy-cells = <0>;
reg = <0x8820 0x20>;
status = "disabled";
};
ARM: dts: meson: add the SDIO MMC controller Meson6, Meson8 and Meson8b are using the same MMC controller IP. This adds the MMC controller node to meson.dtsi so it can be used by all SoCs. The controller itself is a bit special, because it has multiple slots. Each slot is accessed through a sub-node of the controller. However, currently the driver for this hardware only supports one slot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-08 00:29:39 +08:00
sdio: mmc@8c20 {
compatible = "amlogic,meson-mx-sdio";
reg = <0x8c20 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
spifc: spi@8c80 {
compatible = "amlogic,meson6-spifc";
reg = <0x8c80 0x80>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: correct the sort order for the the gpio_intc node Nodes are sorted by their register start address. Move gpio_intc to the correct position. No functional changes intended. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-30 07:17:14 +08:00
gpio_intc: interrupt-controller@9880 {
compatible = "amlogic,meson-gpio-intc";
ARM: dts: meson: fix the memory region of the GPIO interrupt controller commit 200a575b68d2 ("ARM: dts: meson: organize devices in their corresponding busses") organized all peripherals in busses so that the base register offset of the bus doesn't have to be included in all child-nodes anymore. The GPIO interrupt controller however specifies the register offset without subtracting the "cbus" base address. This leads to a problem where of_iomap inside the irq-meson-gpio driver fails because it actually tries to map 0x182209880 (cbus base = 0xc1100000 + 0xc1109880 for the GPIO interrupt controller). Fix this by using 0x9880 as register offset. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-30 07:17:15 +08:00
reg = <0x9880 0x10>;
ARM: dts: meson: correct the sort order for the the gpio_intc node Nodes are sorted by their register start address. Move gpio_intc to the correct position. No functional changes intended. Fixes: 7d32bc03bcfb ("ARM: dts: meson8b: enable gpio interrupt controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-30 07:17:14 +08:00
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
status = "disabled";
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
wdt: watchdog@9900 {
compatible = "amlogic,meson6-wdt";
reg = <0x9900 0x8>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
};
ARM: dts: meson: add the clock inputs for the Meson timer The Meson Timer IP block has two clock inputs: - clk81 for using the system clock as timebase - xtal for a timebase with 1us, 10us, 100us and 1ms resolution The clocksource driver does not use these yet, but it's still a good idea to add them as this describes how the hardware actually works internally. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-17 04:42:35 +08:00
timer_abcde: timer@9940 {
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
compatible = "amlogic,meson6-timer";
reg = <0x9940 0x18>;
ARM: dts: meson: add the TIMER B/C/D interrupts The timer on Meson6/Meson8/Meson8b SoCs has four internal timer events. For each of these a separate interrupt exists. Pass these interrupts to allow using the timers other than TIMER A. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-17 04:42:34 +08:00
interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
};
ARM: dts: meson: add I2C controller nodes Add nodes for I2C controllers A,B,AO, which are available in both Meson6 and Meson8. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@caione.org>
2014-11-14 03:32:03 +08:00
};
media updates for v3.19-rc1 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUhxhbAAoJEAhfPr2O5OEV4JwP/2I7D2KGz5tdNGDAh1H8+swR hoj3tX7HLhwBmF6XIUlMYbk5L/ClDace6kcjT6OjwJ9SktrrKks6ZSsYsBjCIyOC yS7xNQArUKzWk4vV+uJVAvtF8V57LLFul8dhHk0JJwAxrkWnPvDdfJNs4PhUAkgn 1i0PPshNo5Ow/+4YMiOjEDR+q9TMSUUzaq5zkPF7AFCnykuJ1wUJwUE0qjTfGi+4 gl1yMye0TEawTYSM8h/+Lh7wosNFZYcXg85r04A6a8h6GLgg0h6KSOJjyPITmQ+j hLdtyiYs8a6XT+Y8o416zxpbSozo7KXCUTtet/N5g+lgQMqZqSd9WxE52SOY+kfd UVeob0VfWR0xdDzaJp5rLQ/MQ16RTHaHppgUidFxxGe9D5f9JM/88I0OfwNzl4uO cv2cyeNktHH6bcjfOGqxSVmZWgAm6q6qU7MN07PoN+5TcUlYTAOi1WLE5K+7HGgw CxzOZ61oxi/OO1FapaVoipq6ycjltTql2kbcARvmrRrbge0ocAqHxHqFyUbDDhNw Wn/O6VzLfpW0vGTacC6+xcUSpIhwajJ80UJAOqJP8sw0Xtmian5Lcs6gVzxwkOdU 36Po4RRGFqsG6Sq3HR+toNwKt/nHNEFkJwYcNFHdvBiXTEYYkMe6MccUxxb3i/iI KxB1s51zVy9t3PqjP+3J =i7gx -----END PGP SIGNATURE----- Merge tag 'media/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - Two new dvb frontend drivers: mn88472 and mn88473 - A new driver for some PCIe DVBSky cards - A new remote controller driver: meson-ir - One LIRC staging driver got rewritten and promoted to mainstream: igorplugusb - A new tuner driver (m88rs6000t) - The old omap2 media driver got removed from staging. This driver uses an old DMA API and it is likely broken on recent kernels. Nobody cared enough to fix it - Media bus format moved to a separate header, as DRM will also use the definitions there - mem2mem_testdev were renamed to vim2m, in order to use the same naming convention taken by the other virtual test driver (vivid) - Added a new driver for coda SoC (coda-jpeg) - The cx88 driver got converted to use videobuf2 core - Make DMABUF export buffer to work with DMA Scatter/Gather and Vmalloc cores - Lots of other fixes, improvements and cleanups on the drivers. * tag 'media/v3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (384 commits) [media] mn88473: One function call less in mn88473_init() after error [media] mn88473: Remove uneeded check before release_firmware() [media] lirc_zilog: Deletion of unnecessary checks before vfree() [media] MAINTAINERS: Add myself as img-ir maintainer [media] img-ir: Don't set driver's module owner [media] img-ir: Depend on METAG or MIPS or COMPILE_TEST [media] img-ir/hw: Drop [un]register_decoder declarations [media] img-ir/hw: Fix potential deadlock stopping timer [media] img-ir/hw: Always read data to clear buffer [media] redrat3: ensure dma is setup properly [media] ddbridge: remove unneeded check before dvb_unregister_device() [media] si2157: One function call less in si2157_init() after error [media] tuners: remove uneeded checks before release_firmware() [media] arm: omap2: rx51-peripherals: fix build warning [media] stv090x: add an extra protetion against buffer overflow [media] stv090x: Remove an unreachable code [media] stv090x: Some whitespace cleanups [media] em28xx: checkpatch cleanup: whitespaces/new lines cleanups [media] si2168: add support for firmware files in new format [media] si2168: debug printout for firmware version ...
2014-12-12 03:49:23 +08:00
ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripherals The public Meson8b (S805) datasheet describes a memory region called "A9 Periph base" which starts at 0xC4300000 and ends at 0xC430FFFF. Add a simple-bus node and move all peripherals that are part of this memory region. This makes the .dts a bit easier to read. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-24 03:53:07 +08:00
periph: bus@c4300000 {
compatible = "simple-bus";
reg = <0xc4300000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc4300000 0x10000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a9-gic";
reg = <0x1000 0x1000>,
<0x100 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
aobus: aobus@c8100000 {
compatible = "simple-bus";
reg = <0xc8100000 0x100000>;
ARM: dts: meson: add node for SPIFC This adds a node for the SPI Flash Controller to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Mark Brown <broonie@kernel.org>
2015-03-02 03:39:51 +08:00
#address-cells = <1>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#size-cells = <1>;
ranges = <0x0 0xc8100000 0x100000>;
ir_receiver: ir-receiver@480 {
compatible= "amlogic,meson6-ir";
reg = <0x480 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
uart_AO: serial@4c0 {
ARM: dts: meson6: use stable UART bindings The UART bindings needs specifying a SoC family, use the meson6 family for the UART nodes like the other nodes. Switch to the stable UART bindings for meson6 by adding a XTAL node and using the proper compatible strings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-21 22:42:12 +08:00
compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
reg = <0x4c0 0x18>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
status = "disabled";
};
i2c_AO: i2c@500 {
compatible = "amlogic,meson6-i2c";
reg = <0x500 0x20>;
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros This makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:44 +08:00
interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-04-18 05:39:37 +08:00
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ARM: dts: meson: add support for the RTC The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The RTC requires an external 32.768 kHz oscillator to work properly. Whether or not this crystal exists depends on the board, so it has to be added for each board.dts (instead of adding it somewhere in a generic .dtsi). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-14 00:34:21 +08:00
rtc: rtc@740 {
compatible = "amlogic,meson6-rtc";
reg = <0x740 0x14>;
interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
};
ARM: dts: meson: add node for SPIFC This adds a node for the SPI Flash Controller to the Amlogic Meson DTS. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Mark Brown <broonie@kernel.org>
2015-03-02 03:39:51 +08:00
};
ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02 03:45:37 +08:00
ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:50 +08:00
usb0: usb@c9040000 {
compatible = "snps,dwc2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc9040000 0x40000>;
ARM: dts: meson: fixing USB support on Meson6, Meson8 and Meson8b This patch fixes the Meson6, Meson8 and Meson8b USB controllers dts nodes which interrupts are level type instead of edge type. This avoids errors like "usb 1-1-port1: cannot reset (err = -110)" and similars on Odroid-C1+ board. Fixes: e29b1cf87473 ("ARM: dts: meson: add USB support on Meson8 and Meson8b") Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Linus Lüssing <linus.luessing@c0d3.blue> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-09-22 19:57:08 +08:00
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:50 +08:00
phys = <&usb0_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
usb1: usb@c90c0000 {
compatible = "snps,dwc2";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc90c0000 0x40000>;
ARM: dts: meson: fixing USB support on Meson6, Meson8 and Meson8b This patch fixes the Meson6, Meson8 and Meson8b USB controllers dts nodes which interrupts are level type instead of edge type. This avoids errors like "usb 1-1-port1: cannot reset (err = -110)" and similars on Odroid-C1+ board. Fixes: e29b1cf87473 ("ARM: dts: meson: add USB support on Meson8 and Meson8b") Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Linus Lüssing <linus.luessing@c0d3.blue> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-09-22 19:57:08 +08:00
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: meson: add USB support on Meson8 and Meson8b This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16 05:33:50 +08:00
phys = <&usb1_phy>;
phy-names = "usb2-phy";
dr_mode = "host";
status = "disabled";
};
ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02 03:45:37 +08:00
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
reg = <0xc9410000 0x10000
0xc1108108 0x4>;
arm: dts: meson: Fix IRQ trigger type for macirq A long running stress test on a custom board shipping an AXG SoCs and a Realtek RTL8211F PHY revealed that after a few hours the connection speed would drop drastically, from ~1000Mbps to ~3Mbps. At the same time the 'macirq' (eth0) IRQ would stop being triggered at all and as consequence the GMAC IRQs never ACKed. After a painful investigation the problem seemed to be due to a wrong defined IRQ type for the GMAC IRQ that should be LEVEL_HIGH instead of EDGE_RISING. The change in the macirq IRQ type also solved another long standing issue affecting this SoC/PHY where EEE was causing the network connection to die after stressing it with iperf3 (even though much sooner). It's now possible to remove the 'eee-broken-1000t' quirk as well. Fixes: 9c15795a4f96 ("ARM: dts: meson8b-odroidc1: ethernet support") Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-07 18:52:31 +08:00
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
ARM: dts: meson: enable Ethernet controller Add a node for the Ethernet controller to Meson DTS file and enable it on the Geniatech ATV1200 board. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
2015-03-02 03:45:37 +08:00
interrupt-names = "macirq";
status = "disabled";
};
ARM: dts: meson: add a node which describes the SRAM All 32bit Meson SoCs contain 128KiB SRAM. This SRAM is used when suspending the device (the the ARM Power Firmware on Meson8/Meson8b/Meson8m2 saves the DDR settings there) and to boot the secondary CPU cores. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-07-12 06:26:55 +08:00
ahb_sram: sram@d9000000 {
compatible = "mmio-sram";
reg = <0xd9000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd9000000 0x20000>;
};
ARM: dts: meson: add SoC information nodes The SoC type and version information is encoded in different register blocks. The SoC type information is part of the "assist" registers. The misc version information is part of the "bootrom" registers. On Meson8, Meson8b and Meson8m2 there is additionally information about the minor version. This information is stored in the "analog top" registers. Add the nodes for these register blocks so we can decode the SoC type and version information. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-09-23 22:14:03 +08:00
bootrom: bootrom@d9040000 {
compatible = "amlogic,meson-mx-bootrom", "syscon";
reg = <0xd9040000 0x10000>;
};
ARM: dts: meson: add the efuse node Meson6, Meson8 and Meson8b use a similar IP block which has access to 512 bytes of efuse data. During SoC manufacturing some calibration settings for the CVBS connector and the internal temperature sensor are written to this efuse. On some boards it additionally stores for example the MAC addresses. The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6 since we do not have a clock driver there (which is required to read data from the efuse). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-03 07:28:04 +08:00
secbus: secbus@da000000 {
compatible = "simple-bus";
reg = <0xda000000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xda000000 0x6000>;
efuse: nvmem@0 {
compatible = "amlogic,meson6-efuse";
reg = <0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS The Meson6 SoC is produced by Amlogic inc. and it is based on 2 Cortex A9 and an ARM Mali-400 GPU. This patch adds two basic DTSI for the preliminary support of Meson and Meson6 SoCs. Another DTS is also added for supporting the atv1200 board, produced by Geniatech inc. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-09-10 04:12:56 +08:00
};
}; /* end of / */
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