mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 04:03:58 +08:00
91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
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/*
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* to read io range from IOH pci conf, need to do it after mmconfig is there
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*/
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/pci_x86.h>
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#include "bus_numa.h"
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static inline void print_ioh_resources(struct pci_root_info *info)
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{
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int res_num;
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int busnum;
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int i;
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printk(KERN_DEBUG "IOH bus: [%02x, %02x]\n",
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info->bus_min, info->bus_max);
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res_num = info->res_num;
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busnum = info->bus_min;
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for (i = 0; i < res_num; i++) {
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struct resource *res;
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res = &info->res[i];
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printk(KERN_DEBUG "IOH bus: %02x index %x %s: [%llx, %llx]\n",
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busnum, i,
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(res->flags & IORESOURCE_IO) ? "io port" :
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"mmio",
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res->start, res->end);
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}
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}
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#define IOH_LIO 0x108
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#define IOH_LMMIOL 0x10c
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#define IOH_LMMIOH 0x110
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#define IOH_LMMIOH_BASEU 0x114
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#define IOH_LMMIOH_LIMITU 0x118
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#define IOH_LCFGBUS 0x11c
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static void __devinit pci_root_bus_res(struct pci_dev *dev)
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{
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u16 word;
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u32 dword;
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struct pci_root_info *info;
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u16 io_base, io_end;
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u32 mmiol_base, mmiol_end;
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u64 mmioh_base, mmioh_end;
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int bus_base, bus_end;
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if (pci_root_num >= PCI_ROOT_NR) {
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printk(KERN_DEBUG "intel_bus.c: PCI_ROOT_NR is too small\n");
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return;
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}
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info = &pci_root_info[pci_root_num];
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pci_root_num++;
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pci_read_config_word(dev, IOH_LCFGBUS, &word);
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bus_base = (word & 0xff);
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bus_end = (word & 0xff00) >> 8;
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sprintf(info->name, "PCI Bus #%02x", bus_base);
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info->bus_min = bus_base;
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info->bus_max = bus_end;
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pci_read_config_word(dev, IOH_LIO, &word);
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io_base = (word & 0xf0) << (12 - 4);
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io_end = (word & 0xf000) | 0xfff;
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update_res(info, io_base, io_end, IORESOURCE_IO, 0);
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pci_read_config_dword(dev, IOH_LMMIOL, &dword);
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mmiol_base = (dword & 0xff00) << (24 - 8);
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mmiol_end = (dword & 0xff000000) | 0xffffff;
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update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
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pci_read_config_dword(dev, IOH_LMMIOH, &dword);
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mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10);
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mmioh_end = ((u64)(dword & 0xfc000000) | 0x3ffffff);
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pci_read_config_dword(dev, IOH_LMMIOH_BASEU, &dword);
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mmioh_base |= ((u64)(dword & 0x7ffff)) << 32;
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pci_read_config_dword(dev, IOH_LMMIOH_LIMITU, &dword);
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mmioh_end |= ((u64)(dword & 0x7ffff)) << 32;
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update_res(info, mmioh_base, mmioh_end, IORESOURCE_MEM, 0);
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print_ioh_resources(info);
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}
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/* intel IOH */
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, pci_root_bus_res);
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