2017-11-03 18:28:30 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2017-04-19 19:59:27 +08:00
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/*
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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* gadget.h - DesignWare USB3 DRD Gadget Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#ifndef __DRIVERS_USB_DWC3_GADGET_H
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#define __DRIVERS_USB_DWC3_GADGET_H
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#include <linux/list.h>
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#include <linux/usb/gadget.h>
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#include "io.h"
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struct dwc3;
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#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
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#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
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2011-09-30 15:58:51 +08:00
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/* DEPCFG parameter 1 */
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2017-01-31 19:24:54 +08:00
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#define DWC3_DEPCFG_INT_NUM(n) (((n) & 0x1f) << 0)
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2017-03-30 14:46:40 +08:00
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#define DWC3_DEPCFG_XFER_COMPLETE_EN BIT(8)
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#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9)
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#define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10)
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#define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11)
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2018-07-20 07:26:24 +08:00
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#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13)
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2017-01-31 19:24:54 +08:00
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#define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16)
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2017-03-30 14:46:40 +08:00
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#define DWC3_DEPCFG_STREAM_CAPABLE BIT(24)
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2017-01-31 19:24:54 +08:00
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#define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25)
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2017-03-30 14:46:40 +08:00
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#define DWC3_DEPCFG_BULK_BASED BIT(30)
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#define DWC3_DEPCFG_FIFO_BASED BIT(31)
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2011-09-30 15:58:51 +08:00
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/* DEPCFG parameter 0 */
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2017-01-31 19:24:54 +08:00
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#define DWC3_DEPCFG_EP_TYPE(n) (((n) & 0x3) << 1)
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#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) (((n) & 0x7ff) << 3)
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#define DWC3_DEPCFG_FIFO_NUMBER(n) (((n) & 0x1f) << 17)
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#define DWC3_DEPCFG_BURST_SIZE(n) (((n) & 0xf) << 22)
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2011-09-30 15:58:51 +08:00
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#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
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2012-02-16 10:56:58 +08:00
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/* This applies for core versions earlier than 1.94a */
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2017-03-30 14:46:40 +08:00
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#define DWC3_DEPCFG_IGN_SEQ_NUM BIT(31)
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2012-02-16 10:56:58 +08:00
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/* These apply for core versions 1.94a and later */
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#define DWC3_DEPCFG_ACTION_INIT (0 << 30)
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2017-03-30 14:46:40 +08:00
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#define DWC3_DEPCFG_ACTION_RESTORE BIT(30)
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2012-02-16 10:56:58 +08:00
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#define DWC3_DEPCFG_ACTION_MODIFY (2 << 30)
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2011-09-30 15:58:51 +08:00
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/* DEPXFERCFG parameter 0 */
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#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/* -------------------------------------------------------------------------- */
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#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
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2017-04-19 19:59:27 +08:00
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/**
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* next_request - gets the next request on the given list
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* @list: the request list to operate on
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*
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* Caller should take care of locking. This function return %NULL or the first
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* request available on @list.
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*/
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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static inline struct dwc3_request *next_request(struct list_head *list)
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{
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2016-09-19 00:03:14 +08:00
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return list_first_entry_or_null(list, struct dwc3_request, list);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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}
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2017-04-19 19:59:27 +08:00
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/**
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* dwc3_gadget_move_started_request - move @req to the started_list
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* @req: the request to be moved
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*
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* Caller should take care of locking. This function will move @req from its
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* current list to the endpoint's started_list.
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*/
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2016-03-14 17:01:31 +08:00
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static inline void dwc3_gadget_move_started_request(struct dwc3_request *req)
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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{
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struct dwc3_ep *dep = req->dep;
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2019-01-11 18:57:09 +08:00
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req->status = DWC3_REQUEST_STATUS_STARTED;
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2016-03-14 17:01:31 +08:00
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list_move_tail(&req->list, &dep->started_list);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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}
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2018-08-01 18:53:29 +08:00
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/**
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* dwc3_gadget_move_cancelled_request - move @req to the cancelled_list
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* @req: the request to be moved
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*
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* Caller should take care of locking. This function will move @req from its
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* current list to the endpoint's cancelled_list.
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*/
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static inline void dwc3_gadget_move_cancelled_request(struct dwc3_request *req)
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{
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struct dwc3_ep *dep = req->dep;
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2019-01-11 18:57:09 +08:00
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req->status = DWC3_REQUEST_STATUS_CANCELLED;
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2018-08-01 18:53:29 +08:00
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list_move_tail(&req->list, &dep->cancelled_list);
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}
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
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int status);
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2011-11-04 18:32:47 +08:00
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void dwc3_ep0_interrupt(struct dwc3 *dwc,
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const struct dwc3_event_depevt *event);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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void dwc3_ep0_out_start(struct dwc3 *dwc);
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2014-09-24 23:46:46 +08:00
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int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
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2012-06-26 01:10:43 +08:00
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int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
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gfp_t gfp_flags);
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2014-09-25 03:19:52 +08:00
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int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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/**
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* dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
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2017-04-19 19:59:27 +08:00
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* @dep: dwc3 endpoint
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*
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2017-04-19 19:59:27 +08:00
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* Caller should take care of locking. Returns the transfer resource
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* index for a given endpoint.
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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*/
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2018-04-11 17:56:24 +08:00
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static inline void dwc3_gadget_ep_get_transfer_index(struct dwc3_ep *dep)
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
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|
{
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u32 res_id;
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2016-04-12 21:53:39 +08:00
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res_id = dwc3_readl(dep->regs, DWC3_DEPCMD);
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2018-04-11 17:56:24 +08:00
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dep->resource_index = DWC3_DEPCMD_GET_RSC_IDX(res_id);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
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|
}
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#endif /* __DRIVERS_USB_DWC3_GADGET_H */
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