2010-02-13 02:31:47 +08:00
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/*
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* mrst.h: Intel Moorestown platform specific setup code
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*
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* (C) Copyright 2009 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _ASM_X86_MRST_H
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#define _ASM_X86_MRST_H
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extern int pci_mrst_init(void);
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2010-05-20 03:01:24 +08:00
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extern int mrst_identify_cpu(void);
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2010-05-20 03:01:25 +08:00
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extern int mrst_timer_options __cpuinitdata;
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2010-02-12 19:37:38 +08:00
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int __init sfi_parse_mrtc(struct sfi_table_header *table);
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2010-02-13 02:31:47 +08:00
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2010-05-20 03:01:24 +08:00
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum mrst_cpu_type {
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MRST_CPU_CHIP_LINCROFT = 1,
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MRST_CPU_CHIP_PENWELL,
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};
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enum mrst_timer_options {
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MRST_TIMER_DEFAULT,
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MRST_TIMER_APBT_ONLY,
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MRST_TIMER_LAPIC_APBT,
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};
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2010-02-12 19:08:30 +08:00
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#define SFI_MTMR_MAX_NUM 8
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2010-02-12 19:37:38 +08:00
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#define SFI_MRTC_MAX 8
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2010-02-12 19:08:30 +08:00
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2010-02-13 02:31:47 +08:00
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#endif /* _ASM_X86_MRST_H */
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