2012-11-26 22:46:12 +08:00
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/*
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* Copyright 2012 Stefan Roese
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* Stefan Roese <sr@denx.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2013-03-14 03:07:37 +08:00
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/include/ "skeleton.dtsi"
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2012-11-26 22:46:12 +08:00
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/ {
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2013-03-14 03:07:37 +08:00
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interrupt-parent = <&intc>;
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cpus {
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cpu@0 {
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2013-04-19 01:41:57 +08:00
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device_type = "cpu";
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2013-03-14 03:07:37 +08:00
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compatible = "arm,cortex-a8";
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2013-04-19 01:41:57 +08:00
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reg = <0x0>;
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2013-03-14 03:07:37 +08:00
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};
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};
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2012-11-26 22:46:12 +08:00
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memory {
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reg = <0x40000000 0x80000000>;
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};
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2013-01-26 22:36:54 +08:00
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2013-03-14 03:07:37 +08:00
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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2013-04-09 21:48:04 +08:00
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clock-frequency = <24000000>;
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2013-03-14 03:07:37 +08:00
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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};
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axi_gates: axi_gates@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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};
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ahb_gates: ahb_gates@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
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"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
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"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
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"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
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"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
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"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
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"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_mp", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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};
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apb0_gates: apb0_gates@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
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"apb0_ir1", "apb0_keypad";
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};
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/* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&dummy>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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};
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apb1_gates: apb1_gates@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_can", "apb1_scr",
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"apb1_ps20", "apb1_ps21", "apb1_uart0",
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"apb1_uart1", "apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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};
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soc@01c20000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x01c20000 0x300000>;
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ranges;
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intc: interrupt-controller@01c20400 {
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2013-03-25 02:20:52 +08:00
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compatible = "allwinner,sun4i-ic";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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2013-01-28 02:26:05 +08:00
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pio: pinctrl@01c20800 {
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2013-01-26 22:36:54 +08:00
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compatible = "allwinner,sun4i-a10-pinctrl";
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reg = <0x01c20800 0x400>;
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2013-03-28 05:20:41 +08:00
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clocks = <&apb0_gates 5>;
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2013-01-28 02:26:05 +08:00
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gpio-controller;
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2013-01-26 22:36:54 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-01-28 02:26:05 +08:00
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#gpio-cells = <3>;
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2013-01-26 22:36:55 +08:00
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PB22", "PB23";
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allwinner,function = "uart0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart0_pins_b: uart0@1 {
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allwinner,pins = "PF2", "PF4";
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allwinner,function = "uart0";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart1_pins_a: uart1@0 {
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allwinner,pins = "PA10", "PA11";
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allwinner,function = "uart1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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2013-01-26 22:36:54 +08:00
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};
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2013-02-21 09:25:03 +08:00
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2013-03-14 03:07:37 +08:00
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timer@01c20c00 {
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2013-03-25 02:00:17 +08:00
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compatible = "allwinner,sun4i-timer";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20c00 0x90>;
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interrupts = <22>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@01c20c90 {
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2013-03-25 02:32:34 +08:00
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compatible = "allwinner,sun4i-wdt";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20c90 0x10>;
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};
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2013-02-21 09:25:03 +08:00
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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2013-03-28 05:20:39 +08:00
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clocks = <&apb1_gates 16>;
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2013-02-21 09:25:03 +08:00
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status = "disabled";
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};
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2013-02-21 09:38:27 +08:00
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2013-03-14 03:07:37 +08:00
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 17>;
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status = "disabled";
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};
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2013-02-21 09:38:27 +08:00
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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2013-03-28 05:20:39 +08:00
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clocks = <&apb1_gates 18>;
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2013-02-21 09:38:27 +08:00
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status = "disabled";
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};
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2013-03-14 03:07:37 +08:00
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 19>;
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status = "disabled";
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};
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2013-02-21 09:38:27 +08:00
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <17>;
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reg-shift = <2>;
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reg-io-width = <4>;
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2013-03-28 05:20:39 +08:00
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clocks = <&apb1_gates 20>;
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2013-02-21 09:38:27 +08:00
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status = "disabled";
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};
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uart5: serial@01c29400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29400 0x400>;
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interrupts = <18>;
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reg-shift = <2>;
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reg-io-width = <4>;
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2013-03-28 05:20:39 +08:00
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clocks = <&apb1_gates 21>;
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2013-02-21 09:38:27 +08:00
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status = "disabled";
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};
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uart6: serial@01c29800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29800 0x400>;
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interrupts = <19>;
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reg-shift = <2>;
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reg-io-width = <4>;
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2013-03-28 05:20:39 +08:00
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clocks = <&apb1_gates 22>;
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2013-02-21 09:38:27 +08:00
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status = "disabled";
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};
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uart7: serial@01c29c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29c00 0x400>;
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interrupts = <20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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2013-03-28 05:20:39 +08:00
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clocks = <&apb1_gates 23>;
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2013-02-21 09:38:27 +08:00
|
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|
status = "disabled";
|
|
|
|
|
};
|
2013-01-26 22:36:54 +08:00
|
|
|
};
|
2012-11-26 22:46:12 +08:00
|
|
|
};
|
