2006-08-30 06:12:40 +08:00
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/*
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* Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
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*
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* This driver is heavily based upon:
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*
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* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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* Portions Copyright (C) 2003 Red Hat Inc
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2007-08-11 01:02:15 +08:00
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* Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
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2006-08-30 06:12:40 +08:00
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*
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*
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* TODO
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* Work out best PLL policy
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_hpt3x2n"
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2007-08-11 01:02:15 +08:00
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#define DRV_VERSION "0.3.4"
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2006-08-30 06:12:40 +08:00
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enum {
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HPT_PCI_FAST = (1 << 31),
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PCI66 = (1 << 1),
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USE_DPLL = (1 << 0)
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};
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struct hpt_clock {
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u8 xfer_speed;
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u32 timing;
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};
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struct hpt_chip {
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const char *name;
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struct hpt_clock *clocks[3];
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};
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/* key for bus clock timings
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* bit
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* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
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* register access.
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* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
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* register access.
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* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
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* during task file register access.
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* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
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* xfer.
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* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
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* register access.
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* 28 UDMA enable
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* 29 DMA enable
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* 30 PIO_MST enable. if set, the chip is in bus master mode during
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* PIO.
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* 31 FIFO enable.
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*/
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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/* 66MHz DPLL clocks */
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static struct hpt_clock hpt3x2n_clocks[] = {
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{ XFER_UDMA_7, 0x1c869c62 },
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{ XFER_UDMA_6, 0x1c869c62 },
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{ XFER_UDMA_5, 0x1c8a9c62 },
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{ XFER_UDMA_4, 0x1c8a9c62 },
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{ XFER_UDMA_3, 0x1c8e9c62 },
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{ XFER_UDMA_2, 0x1c929c62 },
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{ XFER_UDMA_1, 0x1c9a9c62 },
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{ XFER_UDMA_0, 0x1c829c62 },
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{ XFER_MW_DMA_2, 0x2c829c62 },
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{ XFER_MW_DMA_1, 0x2c829c66 },
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{ XFER_MW_DMA_0, 0x2c829d2c },
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{ XFER_PIO_4, 0x0c829c62 },
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{ XFER_PIO_3, 0x0c829c84 },
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{ XFER_PIO_2, 0x0c829ca6 },
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{ XFER_PIO_1, 0x0d029d26 },
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{ XFER_PIO_0, 0x0d029d5e },
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{ 0, 0x0d029d5e }
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};
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/**
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* hpt3x2n_find_mode - reset the hpt3x2n bus
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* @ap: ATA port
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* @speed: transfer mode
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*
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* Return the 32bit register programming information for this channel
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* that matches the speed provided. For the moment the clocks table
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* is hard coded but easy to change. This will be needed if we use
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* different DPLLs
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*/
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
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{
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struct hpt_clock *clocks = hpt3x2n_clocks;
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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while(clocks->xfer_speed) {
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if (clocks->xfer_speed == speed)
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return clocks->timing;
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clocks++;
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}
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BUG();
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return 0xffffffffU; /* silence compiler warning */
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}
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/**
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2007-03-09 20:24:15 +08:00
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* hpt3x2n_cable_detect - Detect the cable type
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* @ap: ATA port to detect on
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2006-08-30 06:12:40 +08:00
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*
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2007-03-09 20:24:15 +08:00
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* Return the cable type attached to this port
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2006-08-30 06:12:40 +08:00
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*/
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2006-08-31 12:03:49 +08:00
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2007-03-09 20:24:15 +08:00
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static int hpt3x2n_cable_detect(struct ata_port *ap)
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2006-08-30 06:12:40 +08:00
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{
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u8 scr2, ata66;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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pci_read_config_byte(pdev, 0x5B, &scr2);
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pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
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2009-11-20 03:31:31 +08:00
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udelay(10); /* debounce */
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2006-08-30 06:12:40 +08:00
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/* Cable register now active */
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pci_read_config_byte(pdev, 0x5A, &ata66);
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/* Restore state */
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pci_write_config_byte(pdev, 0x5B, scr2);
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2006-08-31 12:03:49 +08:00
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2009-11-20 01:38:11 +08:00
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if (ata66 & (2 >> ap->port_no))
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2007-03-09 20:24:15 +08:00
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return ATA_CBL_PATA40;
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2006-08-30 06:12:40 +08:00
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else
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2007-03-09 20:24:15 +08:00
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return ATA_CBL_PATA80;
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}
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/**
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* hpt3x2n_pre_reset - reset the hpt3x2n bus
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2007-08-06 17:36:23 +08:00
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* @link: ATA link to reset
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2007-04-26 15:19:25 +08:00
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* @deadline: deadline jiffies for the operation
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2007-03-09 20:24:15 +08:00
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*
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* Perform the initial reset handling for the 3x2n series controllers.
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* Reset the hardware and state machine,
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*/
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2006-08-30 06:12:40 +08:00
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libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
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static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
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2007-03-09 20:24:15 +08:00
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{
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2007-08-06 17:36:23 +08:00
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struct ata_port *ap = link->ap;
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2007-03-09 20:24:15 +08:00
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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2006-08-30 06:12:40 +08:00
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/* Reset the state machine */
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2007-04-26 15:19:25 +08:00
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pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
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2006-08-30 06:12:40 +08:00
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udelay(100);
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libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 15:50:52 +08:00
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2008-04-07 21:47:16 +08:00
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return ata_sff_prereset(link, deadline);
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2006-08-30 06:12:40 +08:00
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}
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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/**
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* hpt3x2n_set_piomode - PIO setup
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* @ap: ATA interface
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* @adev: device on the interface
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*
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2006-08-31 12:03:49 +08:00
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* Perform PIO mode setup.
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2006-08-30 06:12:40 +08:00
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*/
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg;
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u32 mode;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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fast &= ~0x07;
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pci_write_config_byte(pdev, addr2, fast);
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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pci_read_config_dword(pdev, addr1, ®);
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mode = hpt3x2n_find_mode(ap, adev->pio_mode);
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mode &= ~0x8000000; /* No FIFO in PIO */
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mode &= ~0x30070000; /* Leave config bits alone */
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reg &= 0x30070000; /* Strip timing bits */
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pci_write_config_dword(pdev, addr1, reg | mode);
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}
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/**
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* hpt3x2n_set_dmamode - DMA timing setup
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* @ap: ATA interface
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* @adev: Device being configured
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*
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* Set up the channel for MWDMA or UDMA modes. Much the same as with
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* PIO, load the mode number and then set MWDMA or UDMA flag.
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*/
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 addr1, addr2;
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u32 reg;
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u32 mode;
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u8 fast;
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addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
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addr2 = 0x51 + 4 * ap->port_no;
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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/* Fast interrupt prediction disable, hold off interrupt disable */
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pci_read_config_byte(pdev, addr2, &fast);
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fast &= ~0x07;
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pci_write_config_byte(pdev, addr2, fast);
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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pci_read_config_dword(pdev, addr1, ®);
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mode = hpt3x2n_find_mode(ap, adev->dma_mode);
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mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
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mode &= ~0xC0000000; /* Leave config bits alone */
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reg &= 0xC0000000; /* Strip timing bits */
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pci_write_config_dword(pdev, addr1, reg | mode);
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}
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/**
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* hpt3x2n_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* Clean up after the HPT3x2n and later DMA engine
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*/
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int mscreg = 0x50 + 2 * ap->port_no;
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u8 bwsr_stat, msc_stat;
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2006-08-31 12:03:49 +08:00
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2006-08-30 06:12:40 +08:00
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pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
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pci_read_config_byte(pdev, mscreg, &msc_stat);
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if (bwsr_stat & (1 << ap->port_no))
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pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
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ata_bmdma_stop(qc);
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}
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/**
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* hpt3x2n_set_clock - clock control
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* @ap: ATA port
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* @source: 0x21 or 0x23 for PLL or PCI sourced clock
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*
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* Switch the ATA bus clock between the PLL and PCI clock sources
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* while correctly isolating the bus and resetting internal logic
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*
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* We must use the DPLL for
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* - writing
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|
* - second channel UDMA7 (SATA ports) or higher
|
|
|
|
* - 66MHz PCI
|
2006-08-31 12:03:49 +08:00
|
|
|
*
|
2006-08-30 06:12:40 +08:00
|
|
|
* or we will underclock the device and get reduced performance.
|
|
|
|
*/
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
static void hpt3x2n_set_clock(struct ata_port *ap, int source)
|
|
|
|
{
|
2007-02-01 14:06:36 +08:00
|
|
|
void __iomem *bmdma = ap->ioaddr.bmdma_addr;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Tristate the bus */
|
2007-02-01 14:06:36 +08:00
|
|
|
iowrite8(0x80, bmdma+0x73);
|
|
|
|
iowrite8(0x80, bmdma+0x77);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Switch clock and reset channels */
|
2007-02-01 14:06:36 +08:00
|
|
|
iowrite8(source, bmdma+0x7B);
|
|
|
|
iowrite8(0xC0, bmdma+0x79);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Reset state machines */
|
2007-02-01 14:06:36 +08:00
|
|
|
iowrite8(0x37, bmdma+0x70);
|
|
|
|
iowrite8(0x37, bmdma+0x74);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Complete reset */
|
2007-02-01 14:06:36 +08:00
|
|
|
iowrite8(0x00, bmdma+0x79);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Reconnect channels to bus */
|
2007-02-01 14:06:36 +08:00
|
|
|
iowrite8(0x00, bmdma+0x73);
|
|
|
|
iowrite8(0x00, bmdma+0x77);
|
2006-08-30 06:12:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if our partner interface is busy */
|
|
|
|
|
|
|
|
static int hpt3x2n_pair_idle(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
struct ata_host *host = ap->host;
|
|
|
|
struct ata_port *pair = host->ports[ap->port_no ^ 1];
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (pair->hsm_task_state == HSM_ST_IDLE)
|
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-01-24 19:51:38 +08:00
|
|
|
static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
long flags = (long)ap->host->private_data;
|
|
|
|
/* See if we should use the DPLL */
|
2007-01-24 19:51:38 +08:00
|
|
|
if (writing)
|
2006-08-30 06:12:40 +08:00
|
|
|
return USE_DPLL; /* Needed for write */
|
|
|
|
if (flags & PCI66)
|
|
|
|
return USE_DPLL; /* Needed at 66Mhz */
|
2006-08-31 12:03:49 +08:00
|
|
|
return 0;
|
2006-08-30 06:12:40 +08:00
|
|
|
}
|
|
|
|
|
2008-04-07 21:47:16 +08:00
|
|
|
static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
struct ata_taskfile *tf = &qc->tf;
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
int flags = (long)ap->host->private_data;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (hpt3x2n_pair_idle(ap)) {
|
|
|
|
int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
|
|
|
|
if ((flags & USE_DPLL) != dpll) {
|
|
|
|
if (dpll == 1)
|
|
|
|
hpt3x2n_set_clock(ap, 0x21);
|
|
|
|
else
|
|
|
|
hpt3x2n_set_clock(ap, 0x23);
|
|
|
|
}
|
|
|
|
}
|
2008-04-07 21:47:16 +08:00
|
|
|
return ata_sff_qc_issue(qc);
|
2006-08-30 06:12:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct scsi_host_template hpt3x2n_sht = {
|
2008-03-25 11:22:49 +08:00
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
2006-08-30 06:12:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configuration for HPT3x2n.
|
|
|
|
*/
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
static struct ata_port_operations hpt3x2n_port_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
|
|
|
.inherits = &ata_bmdma_port_ops,
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
.bmdma_stop = hpt3x2n_bmdma_stop,
|
2008-04-07 21:47:16 +08:00
|
|
|
.qc_issue = hpt3x2n_qc_issue,
|
2006-09-27 17:41:13 +08:00
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
|
|
|
.cable_detect = hpt3x2n_cable_detect,
|
|
|
|
.set_piomode = hpt3x2n_set_piomode,
|
|
|
|
.set_dmamode = hpt3x2n_set_dmamode,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
|
|
|
.prereset = hpt3x2n_pre_reset,
|
2006-08-31 12:03:49 +08:00
|
|
|
};
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
/**
|
|
|
|
* hpt3xn_calibrate_dpll - Calibrate the DPLL loop
|
2006-08-31 12:03:49 +08:00
|
|
|
* @dev: PCI device
|
2006-08-30 06:12:40 +08:00
|
|
|
*
|
|
|
|
* Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
|
|
|
|
* succeeds
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u8 reg5b;
|
|
|
|
u32 reg5c;
|
|
|
|
int tries;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
for(tries = 0; tries < 0x5000; tries++) {
|
|
|
|
udelay(50);
|
|
|
|
pci_read_config_byte(dev, 0x5b, ®5b);
|
|
|
|
if (reg5b & 0x80) {
|
|
|
|
/* See if it stays set */
|
|
|
|
for(tries = 0; tries < 0x1000; tries ++) {
|
|
|
|
pci_read_config_byte(dev, 0x5b, ®5b);
|
|
|
|
/* Failed ? */
|
|
|
|
if ((reg5b & 0x80) == 0)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
/* Turn off tuning, we have the DPLL set */
|
|
|
|
pci_read_config_dword(dev, 0x5c, ®5c);
|
|
|
|
pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Never went stable */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpt3x2n_pci_clock(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
unsigned long freq;
|
|
|
|
u32 fcnt;
|
2007-04-26 15:19:25 +08:00
|
|
|
unsigned long iobase = pci_resource_start(pdev, 4);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2007-04-26 15:19:25 +08:00
|
|
|
fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */
|
2006-08-30 06:12:40 +08:00
|
|
|
if ((fcnt >> 12) != 0xABCDE) {
|
|
|
|
printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
|
|
|
|
return 33; /* Not BIOS set */
|
|
|
|
}
|
|
|
|
fcnt &= 0x1FF;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
freq = (fcnt * 77) / 192;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Clamp to bands */
|
|
|
|
if (freq < 40)
|
|
|
|
return 33;
|
|
|
|
if (freq < 45)
|
|
|
|
return 40;
|
|
|
|
if (freq < 55)
|
|
|
|
return 50;
|
|
|
|
return 66;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* hpt3x2n_init_one - Initialise an HPT37X/302
|
|
|
|
* @dev: PCI device
|
|
|
|
* @id: Entry in match table
|
|
|
|
*
|
|
|
|
* Initialise an HPT3x2n device. There are some interesting complications
|
|
|
|
* here. Firstly the chip may report 366 and be one of several variants.
|
|
|
|
* Secondly all the timings depend on the clock for the chip which we must
|
|
|
|
* detect and look up
|
|
|
|
*
|
|
|
|
* This is the known chip mappings. It may be missing a couple of later
|
|
|
|
* releases.
|
|
|
|
*
|
|
|
|
* Chip version PCI Rev Notes
|
|
|
|
* HPT372 4 (HPT366) 5 Other driver
|
|
|
|
* HPT372N 4 (HPT366) 6 UDMA133
|
|
|
|
* HPT372 5 (HPT372) 1 Other driver
|
|
|
|
* HPT372N 5 (HPT372) 2 UDMA133
|
|
|
|
* HPT302 6 (HPT302) * Other driver
|
|
|
|
* HPT302N 6 (HPT302) > 1 UDMA133
|
|
|
|
* HPT371 7 (HPT371) * Other driver
|
|
|
|
* HPT371N 7 (HPT371) > 1 UDMA133
|
|
|
|
* HPT374 8 (HPT374) * Other driver
|
|
|
|
* HPT372N 9 (HPT372N) * UDMA133
|
|
|
|
*
|
|
|
|
* (1) UDMA133 support depends on the bus clock
|
|
|
|
*
|
|
|
|
* To pin down HPT371N
|
|
|
|
*/
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
{
|
|
|
|
/* HPT372N and friends - UDMA133 */
|
2007-05-04 18:43:58 +08:00
|
|
|
static const struct ata_port_info info = {
|
2007-05-28 18:59:48 +08:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2006-08-30 06:12:40 +08:00
|
|
|
.port_ops = &hpt3x2n_port_ops
|
|
|
|
};
|
2008-03-25 11:22:49 +08:00
|
|
|
const struct ata_port_info *ppi[] = { &info, NULL };
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
u8 irqmask;
|
|
|
|
u32 class_rev;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
unsigned int pci_mhz;
|
|
|
|
unsigned int f_low, f_high;
|
|
|
|
int adjust;
|
2007-04-26 15:19:25 +08:00
|
|
|
unsigned long iobase = pci_resource_start(dev, 4);
|
2008-03-25 11:22:49 +08:00
|
|
|
void *hpriv = NULL;
|
2008-03-25 11:22:47 +08:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = pcim_enable_device(dev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
|
|
|
|
class_rev &= 0xFF;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
switch(dev->device) {
|
|
|
|
case PCI_DEVICE_ID_TTI_HPT366:
|
|
|
|
if (class_rev < 6)
|
|
|
|
return -ENODEV;
|
|
|
|
break;
|
2007-04-26 15:19:25 +08:00
|
|
|
case PCI_DEVICE_ID_TTI_HPT371:
|
|
|
|
if (class_rev < 2)
|
|
|
|
return -ENODEV;
|
|
|
|
/* 371N if rev > 1 */
|
|
|
|
break;
|
2006-08-30 06:12:40 +08:00
|
|
|
case PCI_DEVICE_ID_TTI_HPT372:
|
2007-05-21 21:57:01 +08:00
|
|
|
/* 372N if rev >= 2*/
|
|
|
|
if (class_rev < 2)
|
2006-08-30 06:12:40 +08:00
|
|
|
return -ENODEV;
|
|
|
|
break;
|
|
|
|
case PCI_DEVICE_ID_TTI_HPT302:
|
|
|
|
if (class_rev < 2)
|
|
|
|
return -ENODEV;
|
|
|
|
break;
|
|
|
|
case PCI_DEVICE_ID_TTI_HPT372N:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Ok so this is a chip we support */
|
|
|
|
|
|
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
|
|
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
|
|
|
|
pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
|
|
|
|
pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, 0x5A, &irqmask);
|
|
|
|
irqmask &= ~0x10;
|
|
|
|
pci_write_config_byte(dev, 0x5a, irqmask);
|
|
|
|
|
2007-04-26 15:19:25 +08:00
|
|
|
/*
|
|
|
|
* HPT371 chips physically have only one channel, the secondary one,
|
|
|
|
* but the primary channel registers do exist! Go figure...
|
|
|
|
* So, we manually disable the non-existing channel here
|
|
|
|
* (if the BIOS hasn't done this already).
|
|
|
|
*/
|
|
|
|
if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
|
|
|
|
u8 mcr1;
|
|
|
|
pci_read_config_byte(dev, 0x50, &mcr1);
|
|
|
|
mcr1 &= ~0x04;
|
|
|
|
pci_write_config_byte(dev, 0x50, mcr1);
|
|
|
|
}
|
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
|
|
|
|
50 for UDMA100. Right now we always use 66 */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
pci_mhz = hpt3x2n_pci_clock(dev);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */
|
|
|
|
f_high = f_low + 2; /* Tolerance */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
|
|
|
|
/* PLL clock */
|
|
|
|
pci_write_config_byte(dev, 0x5B, 0x21);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Unlike the 37x we don't try jiggling the frequency */
|
|
|
|
for(adjust = 0; adjust < 8; adjust++) {
|
|
|
|
if (hpt3xn_calibrate_dpll(dev))
|
|
|
|
break;
|
|
|
|
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
|
|
|
|
}
|
2007-04-26 15:19:25 +08:00
|
|
|
if (adjust == 8) {
|
2007-08-11 01:02:15 +08:00
|
|
|
printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
|
2007-04-26 15:19:25 +08:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
2006-08-30 06:12:40 +08:00
|
|
|
|
2007-08-11 01:02:15 +08:00
|
|
|
printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
|
|
|
|
pci_mhz);
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Set our private data up. We only need a few flags so we use
|
|
|
|
it directly */
|
2007-04-26 15:19:25 +08:00
|
|
|
if (pci_mhz > 60) {
|
2008-03-25 11:22:49 +08:00
|
|
|
hpriv = (void *)PCI66;
|
2007-04-26 15:19:25 +08:00
|
|
|
/*
|
|
|
|
* On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
|
|
|
|
* the MISC. register to stretch the UltraDMA Tss timing.
|
|
|
|
* NOTE: This register is only writeable via I/O space.
|
|
|
|
*/
|
|
|
|
if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
|
|
|
|
outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
|
|
|
|
}
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Now kick off ATA set up */
|
2008-04-07 21:47:16 +08:00
|
|
|
return ata_pci_sff_init_one(dev, ppi, &hpt3x2n_sht, hpriv);
|
2006-08-30 06:12:40 +08:00
|
|
|
}
|
|
|
|
|
2006-09-29 08:21:59 +08:00
|
|
|
static const struct pci_device_id hpt3x2n[] = {
|
|
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
|
2007-04-26 15:19:25 +08:00
|
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
|
2006-09-29 08:21:59 +08:00
|
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
|
|
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
|
|
|
|
{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
|
|
|
|
|
|
|
|
{ },
|
2006-08-30 06:12:40 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver hpt3x2n_pci_driver = {
|
2006-09-29 08:21:59 +08:00
|
|
|
.name = DRV_NAME,
|
2006-08-30 06:12:40 +08:00
|
|
|
.id_table = hpt3x2n,
|
|
|
|
.probe = hpt3x2n_init_one,
|
|
|
|
.remove = ata_pci_remove_one
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init hpt3x2n_init(void)
|
|
|
|
{
|
|
|
|
return pci_register_driver(&hpt3x2n_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit hpt3x2n_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&hpt3x2n_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Alan Cox");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, hpt3x2n);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(hpt3x2n_init);
|
|
|
|
module_exit(hpt3x2n_exit);
|