2010-10-28 00:28:45 +08:00
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/* MN10300 CPU cache invalidation routines, using automatic purge registers
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/smp.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/irqflags.h>
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#include <asm/cacheflush.h>
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MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.
Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.
The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.
for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.
Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.
Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.
Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-19 00:54:29 +08:00
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#include "cache.inc"
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2010-10-28 00:28:45 +08:00
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#define mn10300_local_dcache_inv_range_intr_interval \
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+((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1)
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#if mn10300_local_dcache_inv_range_intr_interval > 0xff
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#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less
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#endif
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.am33_2
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#ifndef CONFIG_SMP
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.globl mn10300_icache_inv
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.globl mn10300_icache_inv_page
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.globl mn10300_icache_inv_range
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.globl mn10300_icache_inv_range2
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.globl mn10300_dcache_inv
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.globl mn10300_dcache_inv_page
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.globl mn10300_dcache_inv_range
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.globl mn10300_dcache_inv_range2
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mn10300_icache_inv = mn10300_local_icache_inv
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mn10300_icache_inv_page = mn10300_local_icache_inv_page
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mn10300_icache_inv_range = mn10300_local_icache_inv_range
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mn10300_icache_inv_range2 = mn10300_local_icache_inv_range2
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mn10300_dcache_inv = mn10300_local_dcache_inv
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mn10300_dcache_inv_page = mn10300_local_dcache_inv_page
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mn10300_dcache_inv_range = mn10300_local_dcache_inv_range
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mn10300_dcache_inv_range2 = mn10300_local_dcache_inv_range2
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#endif /* !CONFIG_SMP */
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###############################################################################
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#
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# void mn10300_local_icache_inv(void)
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# Invalidate the entire icache
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#
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###############################################################################
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ALIGN
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.globl mn10300_local_icache_inv
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.type mn10300_local_icache_inv,@function
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mn10300_local_icache_inv:
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_ICEN,d0
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beq mn10300_local_icache_inv_end
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MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.
Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.
The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.
for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.
Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.
Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.
Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-19 00:54:29 +08:00
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invalidate_icache 1
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2010-10-28 00:28:45 +08:00
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mn10300_local_icache_inv_end:
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ret [],0
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.size mn10300_local_icache_inv,.-mn10300_local_icache_inv
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###############################################################################
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#
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# void mn10300_local_dcache_inv(void)
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# Invalidate the entire dcache
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#
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###############################################################################
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ALIGN
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.globl mn10300_local_dcache_inv
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.type mn10300_local_dcache_inv,@function
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mn10300_local_dcache_inv:
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mov CHCTR,a0
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movhu (a0),d0
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btst CHCTR_DCEN,d0
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beq mn10300_local_dcache_inv_end
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MN10300: The icache invalidate functions should disable the icache first
The icache invalidate functions should disable the icache on AM33 and wait for
it to quiesce before attempting to invalidate it, and should then wait for it
to quiesce again before reenabling it, but on AM34 they should invalidate
directly. The same goes for the dcache invalidation, but this isn't used much.
Whilst we're at it, this can be wrapped in assembler macros to remove duplicate
code.
The AM33 manual states that:
An operation that invalidates the cache, switches the writing mode, or
changes the way mode must be performed after disabling the cache,
checking the busy bit, and confirming that the cache is not in
operation.
for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec
2.8.3.1.1] but the example code there suggests that it is.
Whilst the AM34 manual states that the cache must be disabled for both the
icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware
engineers say the manual is wrong and that disabling the caches for
invalidation is wrong.
Furthermore, they say that disabling the caches on the AM34 whilst running an
SMP kernel can lead to incoherency between the various CPU caches and should
thus be avoided.
Signed-off-by: David Howells <dhowells@redhat.com>
2011-03-19 00:54:29 +08:00
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invalidate_dcache 1
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2010-10-28 00:28:45 +08:00
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mn10300_local_dcache_inv_end:
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ret [],0
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.size mn10300_local_dcache_inv,.-mn10300_local_dcache_inv
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###############################################################################
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#
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# void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end)
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# void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size)
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# void mn10300_local_dcache_inv_page(unsigned long start)
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# Invalidate a range of addresses on a page in the dcache
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#
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###############################################################################
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ALIGN
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.globl mn10300_local_dcache_inv_page
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.globl mn10300_local_dcache_inv_range
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.globl mn10300_local_dcache_inv_range2
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.type mn10300_local_dcache_inv_page,@function
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.type mn10300_local_dcache_inv_range,@function
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.type mn10300_local_dcache_inv_range2,@function
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mn10300_local_dcache_inv_page:
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and ~(PAGE_SIZE-1),d0
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mov PAGE_SIZE,d1
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mn10300_local_dcache_inv_range2:
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add d0,d1
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mn10300_local_dcache_inv_range:
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# If we are in writeback mode we check the start and end alignments,
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# and if they're not cacheline-aligned, we must flush any bits outside
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# the range that share cachelines with stuff inside the range
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#ifdef CONFIG_MN10300_CACHE_WBACK
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2011-03-19 00:54:30 +08:00
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btst ~L1_CACHE_TAG_MASK,d0
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2010-10-28 00:28:45 +08:00
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bne 1f
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2011-03-19 00:54:30 +08:00
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btst ~L1_CACHE_TAG_MASK,d1
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2010-10-28 00:28:45 +08:00
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beq 2f
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1:
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bra mn10300_local_dcache_flush_inv_range
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2:
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#endif /* CONFIG_MN10300_CACHE_WBACK */
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movm [d2,d3,a2],(sp)
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mov CHCTR,a0
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movhu (a0),d2
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btst CHCTR_DCEN,d2
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beq mn10300_local_dcache_inv_range_end
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# round the addresses out to be full cachelines, unless we're in
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# writeback mode, in which case we would be in flush and invalidate by
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# now
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#ifndef CONFIG_MN10300_CACHE_WBACK
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2011-03-19 00:54:30 +08:00
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and L1_CACHE_TAG_MASK,d0 # round start addr down
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2010-10-28 00:28:45 +08:00
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mov L1_CACHE_BYTES-1,d2
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add d2,d1
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2011-03-19 00:54:30 +08:00
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and L1_CACHE_TAG_MASK,d1 # round end addr up
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2010-10-28 00:28:45 +08:00
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#endif /* !CONFIG_MN10300_CACHE_WBACK */
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sub d0,d1,d2 # calculate the total size
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mov d0,a2 # A2 = start address
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mov d1,a1 # A1 = end address
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LOCAL_CLI_SAVE(d3)
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mov DCPGCR,a0 # make sure the purger isn't busy
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setlb
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mov (a0),d0
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btst DCPGCR_DCPGBSY,d0
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lne
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# skip initial address alignment calculation if address is zero
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mov d2,d1
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cmp 0,a2
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beq 1f
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dcivloop:
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/* calculate alignsize
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*
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* alignsize = L1_CACHE_BYTES;
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* while (! start & alignsize) {
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* alignsize <<=1;
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* }
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* d1 = alignsize;
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*/
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mov L1_CACHE_BYTES,d1
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lsr 1,d1
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setlb
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add d1,d1
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mov d1,d0
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and a2,d0
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leq
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1:
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/* calculate invsize
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*
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* if (totalsize > alignsize) {
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* invsize = alignsize;
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* } else {
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* invsize = totalsize;
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* tmp = 0x80000000;
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* while (! invsize & tmp) {
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* tmp >>= 1;
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* }
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* invsize = tmp;
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* }
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* d1 = invsize
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*/
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cmp d2,d1
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bns 2f
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mov d2,d1
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mov 0x80000000,d0 # start from 31bit=1
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setlb
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lsr 1,d0
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mov d0,e0
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and d1,e0
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leq
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mov d0,d1
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2:
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/* set mask
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*
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* mask = ~(invsize-1);
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* DCPGMR = mask;
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*/
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mov d1,d0
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add -1,d0
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not d0
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mov d0,(DCPGMR)
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# invalidate area
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mov a2,d0
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or DCPGCR_DCI,d0
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mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCI
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setlb # wait for the purge to complete
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mov (a0),d0
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btst DCPGCR_DCPGBSY,d0
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lne
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sub d1,d2 # decrease size remaining
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add d1,a2 # increase next start address
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/* check invalidating of end address
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*
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* a2 = a2 + invsize
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* if (a2 < end) {
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* goto dcivloop;
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* } */
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cmp a1,a2
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bns dcivloop
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LOCAL_IRQ_RESTORE(d3)
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mn10300_local_dcache_inv_range_end:
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ret [d2,d3,a2],12
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.size mn10300_local_dcache_inv_page,.-mn10300_local_dcache_inv_page
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.size mn10300_local_dcache_inv_range,.-mn10300_local_dcache_inv_range
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.size mn10300_local_dcache_inv_range2,.-mn10300_local_dcache_inv_range2
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###############################################################################
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#
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# void mn10300_local_icache_inv_page(unsigned long start)
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# void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size)
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# void mn10300_local_icache_inv_range(unsigned long start, unsigned long end)
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# Invalidate a range of addresses on a page in the icache
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#
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###############################################################################
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ALIGN
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.globl mn10300_local_icache_inv_page
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.globl mn10300_local_icache_inv_range
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.globl mn10300_local_icache_inv_range2
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.type mn10300_local_icache_inv_page,@function
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.type mn10300_local_icache_inv_range,@function
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.type mn10300_local_icache_inv_range2,@function
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mn10300_local_icache_inv_page:
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and ~(PAGE_SIZE-1),d0
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mov PAGE_SIZE,d1
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mn10300_local_icache_inv_range2:
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add d0,d1
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mn10300_local_icache_inv_range:
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movm [d2,d3,a2],(sp)
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mov CHCTR,a0
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movhu (a0),d2
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btst CHCTR_ICEN,d2
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beq mn10300_local_icache_inv_range_reg_end
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/* calculate alignsize
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*
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* alignsize = L1_CACHE_BYTES;
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* for (i = (end - start - 1) / L1_CACHE_BYTES ; i > 0; i >>= 1) {
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* alignsize <<= 1;
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* }
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* d2 = alignsize;
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*/
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mov L1_CACHE_BYTES,d2
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sub d0,d1,d3
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add -1,d3
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lsr L1_CACHE_SHIFT,d3
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beq 2f
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1:
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add d2,d2
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lsr 1,d3
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bne 1b
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2:
|
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|
|
/* a1 = end */
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|
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mov d1,a1
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|
|
LOCAL_CLI_SAVE(d3)
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|
|
mov ICIVCR,a0
|
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|
|
/* wait for busy bit of area invalidation */
|
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|
|
setlb
|
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|
|
mov (a0),d1
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|
|
btst ICIVCR_ICIVBSY,d1
|
|
|
|
|
lne
|
|
|
|
|
|
|
|
|
|
/* set mask
|
|
|
|
|
*
|
|
|
|
|
* mask = ~(alignsize-1);
|
|
|
|
|
* ICIVMR = mask;
|
|
|
|
|
*/
|
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|
|
mov d2,d1
|
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|
|
add -1,d1
|
|
|
|
|
not d1
|
|
|
|
|
mov d1,(ICIVMR)
|
|
|
|
|
/* a2 = mask & start */
|
|
|
|
|
and d1,d0,a2
|
|
|
|
|
|
|
|
|
|
icivloop:
|
|
|
|
|
/* area invalidate
|
|
|
|
|
*
|
|
|
|
|
* ICIVCR = (mask & start) | ICIVCR_ICI
|
|
|
|
|
*/
|
|
|
|
|
mov a2,d0
|
|
|
|
|
or ICIVCR_ICI,d0
|
|
|
|
|
mov d0,(a0)
|
|
|
|
|
|
|
|
|
|
/* wait for busy bit of area invalidation */
|
|
|
|
|
setlb
|
|
|
|
|
mov (a0),d1
|
|
|
|
|
btst ICIVCR_ICIVBSY,d1
|
|
|
|
|
lne
|
|
|
|
|
|
|
|
|
|
/* check invalidating of end address
|
|
|
|
|
*
|
|
|
|
|
* a2 = a2 + alignsize
|
|
|
|
|
* if (a2 < end) {
|
|
|
|
|
* goto icivloop;
|
|
|
|
|
* } */
|
|
|
|
|
add d2,a2
|
|
|
|
|
cmp a1,a2
|
|
|
|
|
bns icivloop
|
|
|
|
|
|
|
|
|
|
LOCAL_IRQ_RESTORE(d3)
|
|
|
|
|
|
|
|
|
|
mn10300_local_icache_inv_range_reg_end:
|
|
|
|
|
ret [d2,d3,a2],12
|
|
|
|
|
.size mn10300_local_icache_inv_page,.-mn10300_local_icache_inv_page
|
|
|
|
|
.size mn10300_local_icache_inv_range,.-mn10300_local_icache_inv_range
|
|
|
|
|
.size mn10300_local_icache_inv_range2,.-mn10300_local_icache_inv_range2
|
