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51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
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/*
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* Definitions for the ST M41T00 family of i2c rtc chips.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2005, 2006 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef _M41T00_H
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#define _M41T00_H
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#define M41T00_DRV_NAME "m41t00"
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#define M41T00_I2C_ADDR 0x68
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#define M41T00_TYPE_M41T00 0
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#define M41T00_TYPE_M41T81 81
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#define M41T00_TYPE_M41T85 85
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struct m41t00_platform_data {
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u8 type;
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u8 i2c_addr;
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u8 sqw_freq;
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};
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/* SQW output disabled, this is default value by power on */
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#define M41T00_SQW_DISABLE (0)
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#define M41T00_SQW_32KHZ (1<<4) /* 32.768 KHz */
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#define M41T00_SQW_8KHZ (2<<4) /* 8.192 KHz */
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#define M41T00_SQW_4KHZ (3<<4) /* 4.096 KHz */
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#define M41T00_SQW_2KHZ (4<<4) /* 2.048 KHz */
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#define M41T00_SQW_1KHZ (5<<4) /* 1.024 KHz */
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#define M41T00_SQW_512HZ (6<<4) /* 512 Hz */
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#define M41T00_SQW_256HZ (7<<4) /* 256 Hz */
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#define M41T00_SQW_128HZ (8<<4) /* 128 Hz */
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#define M41T00_SQW_64HZ (9<<4) /* 64 Hz */
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#define M41T00_SQW_32HZ (10<<4) /* 32 Hz */
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#define M41T00_SQW_16HZ (11<<4) /* 16 Hz */
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#define M41T00_SQW_8HZ (12<<4) /* 8 Hz */
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#define M41T00_SQW_4HZ (13<<4) /* 4 Hz */
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#define M41T00_SQW_2HZ (14<<4) /* 2 Hz */
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#define M41T00_SQW_1HZ (15<<4) /* 1 Hz */
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extern ulong m41t00_get_rtc_time(void);
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extern int m41t00_set_rtc_time(ulong nowtime);
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#endif /* _M41T00_H */
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