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linux-next/include/linux/stmp_device.h

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lib: add support for stmp-style devices MX23/28 use IP cores which follow a register layout I have first seen on STMP3xxx SoCs. In this layout, every register actually has four u32: 1.) to store a value directly 2.) a SET register where every 1-bit sets the corresponding bit, others are unaffected 3.) same with a CLR register 4.) same with a TOG (toggle) register Also, the 2 MSBs in register 0 are always the same and can be used to reset the IP core. All this is strictly speaking not mach-specific (but IP core specific) and, thus, doesn't need to be in mach-mxs/include. At least mx6 also uses IP cores following this stmp-style. So: Introduce a stmp-style device, put the code and defines for that in a public place (lib/), and let drivers for stmp-style devices select that code. To avoid regressions and ease reviewing, the actual code is simply copied from mach-mxs. It definately wants updates, but those need a seperate patch series. Voila, mach dependency gone, reusable code introduced. Note that I didn't remove the duplicated code from mach-mxs yet, first the drivers have to be converted. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
2011-09-01 02:35:40 +08:00
/*
* basic functions for devices following the "stmp" style register layout
*
* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __STMP_DEVICE_H__
#define __STMP_DEVICE_H__
#define STMP_OFFSET_REG_SET 0x4
#define STMP_OFFSET_REG_CLR 0x8
#define STMP_OFFSET_REG_TOG 0xc
extern int stmp_reset_block(void __iomem *);
#endif /* __STMP_DEVICE_H__ */
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