2013-06-20 13:21:13 +08:00
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/*
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* The file intends to implement the platform dependent EEH operations on
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* powernv platform. Actually, the powernv was created in order to fully
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* hypervisor support.
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*
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* Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/atomic.h>
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2015-02-16 11:45:41 +08:00
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#include <linux/debugfs.h>
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2013-06-20 13:21:13 +08:00
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/init.h>
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2015-05-15 12:06:40 +08:00
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#include <linux/interrupt.h>
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2013-06-20 13:21:13 +08:00
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#include <linux/list.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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#include <linux/rbtree.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <asm/eeh.h>
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#include <asm/eeh_event.h>
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#include <asm/firmware.h>
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#include <asm/io.h>
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#include <asm/iommu.h>
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#include <asm/machdep.h>
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#include <asm/msi_bitmap.h>
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#include <asm/opal.h>
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#include <asm/ppc-pci.h>
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2016-05-20 14:41:39 +08:00
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#include <asm/pnv-pci.h>
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2013-06-20 13:21:13 +08:00
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#include "powernv.h"
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#include "pci.h"
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2015-05-15 12:06:40 +08:00
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static int eeh_event_irq = -EINVAL;
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2015-02-16 11:45:41 +08:00
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2017-11-09 22:00:33 +08:00
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void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
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{
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struct pci_dn *pdn = pci_get_pdn(pdev);
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if (!pdev->is_virtfn)
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return;
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/*
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* The following operations will fail if VF's sysfs files
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* aren't created or its resources aren't finalized.
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*/
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eeh_add_device_early(pdn);
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eeh_add_device_late(pdev);
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eeh_sysfs_add_device(pdev);
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}
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2015-02-16 11:45:39 +08:00
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static int pnv_eeh_init(void)
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2013-06-20 13:21:13 +08:00
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{
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2014-07-17 12:41:39 +08:00
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struct pci_controller *hose;
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struct pnv_phb *phb;
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2017-06-14 12:19:59 +08:00
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int max_diag_size = PNV_PCI_DIAG_BUF_SIZE;
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2014-07-17 12:41:39 +08:00
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2015-12-09 14:18:20 +08:00
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if (!firmware_has_feature(FW_FEATURE_OPAL)) {
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pr_warn("%s: OPAL is required !\n",
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2014-07-17 12:41:41 +08:00
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__func__);
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2013-06-20 13:21:13 +08:00
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return -EINVAL;
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}
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2014-07-17 12:41:38 +08:00
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/* Set probe mode */
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eeh_add_flag(EEH_PROBE_MODE_DEV);
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2013-06-20 13:21:13 +08:00
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2014-07-17 12:41:39 +08:00
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/*
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* P7IOC blocks PCI config access to frozen PE, but PHB3
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* doesn't do that. So we have to selectively enable I/O
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* prior to collecting error log.
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*/
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list_for_each_entry(hose, &hose_list, list_node) {
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phb = hose->private_data;
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if (phb->model == PNV_PHB_MODEL_P7IOC)
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eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
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2014-11-25 06:27:00 +08:00
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2017-06-14 12:19:59 +08:00
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if (phb->diag_data_size > max_diag_size)
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max_diag_size = phb->diag_data_size;
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2014-11-25 06:27:00 +08:00
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/*
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* PE#0 should be regarded as valid by EEH core
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* if it's not the reserved one. Currently, we
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2015-10-08 11:58:57 +08:00
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* have the reserved PE#255 and PE#127 for PHB3
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2014-11-25 06:27:00 +08:00
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* and P7IOC separately. So we should regard
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2015-10-08 11:58:57 +08:00
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* PE#0 as valid for PHB3 and P7IOC.
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2014-11-25 06:27:00 +08:00
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*/
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2016-05-03 13:41:24 +08:00
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if (phb->ioda.reserved_pe_idx != 0)
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2014-11-25 06:27:00 +08:00
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eeh_add_flag(EEH_VALID_PE_ZERO);
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2014-07-17 12:41:39 +08:00
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break;
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}
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2017-06-14 12:19:59 +08:00
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eeh_set_pe_aux_size(max_diag_size);
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2017-11-09 22:00:33 +08:00
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ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device;
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2017-06-14 12:19:59 +08:00
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2013-06-20 13:21:13 +08:00
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return 0;
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}
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2015-05-15 12:06:40 +08:00
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static irqreturn_t pnv_eeh_event(int irq, void *data)
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2015-02-16 11:45:41 +08:00
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{
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/*
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2015-05-15 12:06:40 +08:00
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* We simply send a special EEH event if EEH has been
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* enabled. We don't care about EEH events until we've
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* finished processing the outstanding ones. Event processing
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* gets unmasked in next_error() if EEH is enabled.
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2015-02-16 11:45:41 +08:00
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*/
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2015-05-15 12:06:40 +08:00
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disable_irq_nosync(irq);
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2015-02-16 11:45:41 +08:00
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if (eeh_enabled())
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eeh_send_failure_event(NULL);
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2015-05-15 12:06:40 +08:00
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return IRQ_HANDLED;
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2015-02-16 11:45:41 +08:00
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}
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#ifdef CONFIG_DEBUG_FS
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static ssize_t pnv_eeh_ei_write(struct file *filp,
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const char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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struct pci_controller *hose = filp->private_data;
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struct eeh_pe *pe;
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int pe_no, type, func;
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unsigned long addr, mask;
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char buf[50];
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int ret;
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if (!eeh_ops || !eeh_ops->err_inject)
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return -ENXIO;
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/* Copy over argument buffer */
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ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
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if (!ret)
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return -EFAULT;
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/* Retrieve parameters */
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ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
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&pe_no, &type, &func, &addr, &mask);
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if (ret != 5)
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return -EINVAL;
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/* Retrieve PE */
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2017-08-29 15:34:00 +08:00
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pe = eeh_pe_get(hose, pe_no, 0);
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2015-02-16 11:45:41 +08:00
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if (!pe)
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return -ENODEV;
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/* Do error injection */
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ret = eeh_ops->err_inject(pe, type, func, addr, mask);
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return ret < 0 ? ret : count;
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}
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static const struct file_operations pnv_eeh_ei_fops = {
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.open = simple_open,
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.llseek = no_llseek,
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.write = pnv_eeh_ei_write,
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};
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static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
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{
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struct pci_controller *hose = data;
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struct pnv_phb *phb = hose->private_data;
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out_be64(phb->regs + offset, val);
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return 0;
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}
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static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
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{
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struct pci_controller *hose = data;
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struct pnv_phb *phb = hose->private_data;
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*val = in_be64(phb->regs + offset);
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return 0;
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}
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2016-02-09 12:50:24 +08:00
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#define PNV_EEH_DBGFS_ENTRY(name, reg) \
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static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \
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{ \
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return pnv_eeh_dbgfs_set(data, reg, val); \
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} \
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\
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static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \
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{ \
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return pnv_eeh_dbgfs_get(data, reg, val); \
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} \
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\
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DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \
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pnv_eeh_dbgfs_get_##name, \
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pnv_eeh_dbgfs_set_##name, \
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"0x%llx\n")
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PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
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PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
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PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
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2015-02-16 11:45:41 +08:00
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#endif /* CONFIG_DEBUG_FS */
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2013-06-20 13:21:13 +08:00
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/**
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2015-02-16 11:45:39 +08:00
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* pnv_eeh_post_init - EEH platform dependent post initialization
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2013-06-20 13:21:13 +08:00
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*
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* EEH platform dependent post initialization on powernv. When
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* the function is called, the EEH PEs and devices should have
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* been built. If the I/O cache staff has been built, EEH is
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* ready to supply service.
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*/
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2017-09-07 14:35:44 +08:00
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int pnv_eeh_post_init(void)
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2013-06-20 13:21:13 +08:00
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{
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struct pci_controller *hose;
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struct pnv_phb *phb;
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int ret = 0;
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2017-09-07 14:35:44 +08:00
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/* Probe devices & build address cache */
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eeh_probe_devices();
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eeh_addr_cache_build();
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2015-05-15 12:06:40 +08:00
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2017-09-07 14:35:44 +08:00
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/* Register OPAL event notifier */
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eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
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if (eeh_event_irq < 0) {
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pr_err("%s: Can't register OPAL event interrupt (%d)\n",
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__func__, eeh_event_irq);
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return eeh_event_irq;
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}
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2015-02-16 11:45:41 +08:00
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2017-09-07 14:35:44 +08:00
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ret = request_irq(eeh_event_irq, pnv_eeh_event,
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IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
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if (ret < 0) {
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irq_dispose_mapping(eeh_event_irq);
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pr_err("%s: Can't request OPAL event interrupt (%d)\n",
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__func__, eeh_event_irq);
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return ret;
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2015-02-16 11:45:41 +08:00
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}
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2015-05-15 12:06:40 +08:00
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if (!eeh_enabled())
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disable_irq(eeh_event_irq);
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2013-06-20 13:21:13 +08:00
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list_for_each_entry(hose, &hose_list, list_node) {
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phb = hose->private_data;
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2015-02-16 11:45:41 +08:00
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/*
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* If EEH is enabled, we're going to rely on that.
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* Otherwise, we restore to conventional mechanism
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* to clear frozen PE during PCI config access.
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*/
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if (eeh_enabled())
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phb->flags |= PNV_PHB_FLAG_EEH;
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else
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phb->flags &= ~PNV_PHB_FLAG_EEH;
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/* Create debugfs entries */
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#ifdef CONFIG_DEBUG_FS
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if (phb->has_dbgfs || !phb->dbgfs)
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continue;
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phb->has_dbgfs = 1;
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debugfs_create_file("err_injct", 0200,
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phb->dbgfs, hose,
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&pnv_eeh_ei_fops);
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debugfs_create_file("err_injct_outbound", 0600,
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phb->dbgfs, hose,
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2016-02-09 12:50:24 +08:00
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&pnv_eeh_dbgfs_ops_outb);
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2015-02-16 11:45:41 +08:00
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debugfs_create_file("err_injct_inboundA", 0600,
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phb->dbgfs, hose,
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2016-02-09 12:50:24 +08:00
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&pnv_eeh_dbgfs_ops_inbA);
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2015-02-16 11:45:41 +08:00
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debugfs_create_file("err_injct_inboundB", 0600,
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phb->dbgfs, hose,
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2016-02-09 12:50:24 +08:00
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&pnv_eeh_dbgfs_ops_inbB);
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2015-02-16 11:45:41 +08:00
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#endif /* CONFIG_DEBUG_FS */
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2013-06-20 13:21:13 +08:00
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}
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return ret;
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}
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2015-10-08 11:58:58 +08:00
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static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
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2015-03-17 13:15:06 +08:00
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{
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2015-10-08 11:58:58 +08:00
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int pos = PCI_CAPABILITY_LIST;
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int cnt = 48; /* Maximal number of capabilities */
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u32 status, id;
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2015-03-17 13:15:06 +08:00
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if (!pdn)
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return 0;
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2015-10-08 11:58:58 +08:00
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/* Check if the device supports capabilities */
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2015-03-17 13:15:06 +08:00
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pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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while (cnt--) {
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pnv_pci_cfg_read(pdn, pos, 1, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
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if (id == 0xff)
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break;
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/* Found */
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if (id == cap)
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return pos;
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/* Next one */
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
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|
{
|
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
|
|
|
u32 header;
|
|
|
|
int pos = 256, ttl = (4096 - 256) / 8;
|
|
|
|
|
|
|
|
if (!edev || !edev->pcie_cap)
|
|
|
|
return 0;
|
|
|
|
if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
|
|
|
|
return 0;
|
|
|
|
else if (!header)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
while (ttl-- > 0) {
|
|
|
|
if (PCI_EXT_CAP_ID(header) == cap && pos)
|
|
|
|
return pos;
|
|
|
|
|
|
|
|
pos = PCI_EXT_CAP_NEXT(header);
|
|
|
|
if (pos < 256)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-20 13:21:13 +08:00
|
|
|
/**
|
2015-03-17 13:15:06 +08:00
|
|
|
* pnv_eeh_probe - Do probe on PCI device
|
|
|
|
* @pdn: PCI device node
|
|
|
|
* @data: unused
|
2013-06-20 13:21:13 +08:00
|
|
|
*
|
|
|
|
* When EEH module is installed during system boot, all PCI devices
|
|
|
|
* are checked one by one to see if it supports EEH. The function
|
|
|
|
* is introduced for the purpose. By default, EEH has been enabled
|
|
|
|
* on all PCI devices. That's to say, we only need do necessary
|
|
|
|
* initialization on the corresponding eeh device and create PE
|
|
|
|
* accordingly.
|
|
|
|
*
|
|
|
|
* It's notable that's unsafe to retrieve the EEH device through
|
|
|
|
* the corresponding PCI device. During the PCI device hotplug, which
|
|
|
|
* was possiblly triggered by EEH core, the binding between EEH device
|
|
|
|
* and the PCI device isn't built yet.
|
|
|
|
*/
|
2015-03-17 13:15:06 +08:00
|
|
|
static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
2015-03-17 13:15:06 +08:00
|
|
|
struct pci_controller *hose = pdn->phb;
|
2013-06-20 13:21:13 +08:00
|
|
|
struct pnv_phb *phb = hose->private_data;
|
2015-03-17 13:15:06 +08:00
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
|
|
|
uint32_t pcie_flags;
|
2014-06-26 14:58:47 +08:00
|
|
|
int ret;
|
2017-08-29 15:34:02 +08:00
|
|
|
int config_addr = (pdn->busno << 8) | (pdn->devfn);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* When probing the root bridge, which doesn't have any
|
|
|
|
* subordinate PCI devices. We don't have OF node for
|
|
|
|
* the root bridge. So it's not reasonable to continue
|
|
|
|
* the probing.
|
|
|
|
*/
|
2015-03-17 13:15:06 +08:00
|
|
|
if (!edev || edev->pe)
|
|
|
|
return NULL;
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
/* Skip for PCI-ISA bridge */
|
2015-03-17 13:15:06 +08:00
|
|
|
if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
|
|
|
|
return NULL;
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2017-09-07 14:35:44 +08:00
|
|
|
/* Skip if we haven't probed yet */
|
|
|
|
if (phb->ioda.pe_rmap[config_addr] == IODA_INVALID_PE)
|
|
|
|
return NULL;
|
|
|
|
|
2013-06-20 13:21:13 +08:00
|
|
|
/* Initialize eeh device */
|
2015-03-17 13:15:06 +08:00
|
|
|
edev->class_code = pdn->class_code;
|
2013-07-24 10:25:01 +08:00
|
|
|
edev->mode &= 0xFFFFFF00;
|
2015-03-17 13:15:06 +08:00
|
|
|
edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
|
|
|
|
edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
|
2016-03-04 07:53:09 +08:00
|
|
|
edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
|
2015-03-17 13:15:06 +08:00
|
|
|
edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
|
|
|
|
if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
|
2013-07-24 10:24:59 +08:00
|
|
|
edev->mode |= EEH_DEV_BRIDGE;
|
2015-03-17 13:15:06 +08:00
|
|
|
if (edev->pcie_cap) {
|
|
|
|
pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
|
|
|
|
2, &pcie_flags);
|
|
|
|
pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
|
|
|
|
if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
|
|
|
|
edev->mode |= EEH_DEV_ROOT_PORT;
|
|
|
|
else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
|
|
|
|
edev->mode |= EEH_DEV_DS_PORT;
|
|
|
|
}
|
2013-07-24 10:24:59 +08:00
|
|
|
}
|
|
|
|
|
2017-08-29 15:34:02 +08:00
|
|
|
edev->pe_config_addr = phb->ioda.pe_rmap[config_addr];
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
/* Create PE */
|
2014-06-26 14:58:47 +08:00
|
|
|
ret = eeh_add_to_parent_pe(edev);
|
|
|
|
if (ret) {
|
2016-11-16 11:02:15 +08:00
|
|
|
pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n",
|
2015-03-17 13:15:06 +08:00
|
|
|
__func__, hose->global_number, pdn->busno,
|
|
|
|
PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
|
|
|
|
return NULL;
|
2014-06-26 14:58:47 +08:00
|
|
|
}
|
|
|
|
|
2014-10-01 15:07:53 +08:00
|
|
|
/*
|
|
|
|
* If the PE contains any one of following adapters, the
|
|
|
|
* PCI config space can't be accessed when dumping EEH log.
|
|
|
|
* Otherwise, we will run into fenced PHB caused by shortage
|
|
|
|
* of outbound credits in the adapter. The PCI config access
|
|
|
|
* should be blocked until PE reset. MMIO access is dropped
|
|
|
|
* by hardware certainly. In order to drop PCI config requests,
|
|
|
|
* one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
|
|
|
|
* will be checked in the backend for PE state retrival. If
|
|
|
|
* the PE becomes frozen for the first time and the flag has
|
|
|
|
* been set for the PE, we will set EEH_PE_CFG_BLOCKED for
|
|
|
|
* that PE to block its config space.
|
|
|
|
*
|
2017-04-19 12:46:24 +08:00
|
|
|
* Broadcom BCM5718 2-ports NICs (14e4:1656)
|
2014-10-01 15:07:53 +08:00
|
|
|
* Broadcom Austin 4-ports NICs (14e4:1657)
|
2015-10-15 12:22:35 +08:00
|
|
|
* Broadcom Shiner 4-ports 1G NICs (14e4:168a)
|
2014-10-03 12:58:32 +08:00
|
|
|
* Broadcom Shiner 2-ports 10G NICs (14e4:168e)
|
2014-10-01 15:07:53 +08:00
|
|
|
*/
|
2015-03-17 13:15:06 +08:00
|
|
|
if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
|
2017-04-19 12:46:24 +08:00
|
|
|
pdn->device_id == 0x1656) ||
|
|
|
|
(pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
|
2015-03-17 13:15:06 +08:00
|
|
|
pdn->device_id == 0x1657) ||
|
2015-10-15 12:22:35 +08:00
|
|
|
(pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
|
|
|
|
pdn->device_id == 0x168a) ||
|
2015-03-17 13:15:06 +08:00
|
|
|
(pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
|
|
|
|
pdn->device_id == 0x168e))
|
2014-10-01 15:07:53 +08:00
|
|
|
edev->pe->state |= EEH_PE_CFG_RESTRICTED;
|
|
|
|
|
2014-06-26 14:58:47 +08:00
|
|
|
/*
|
|
|
|
* Cache the PE primary bus, which can't be fetched when
|
|
|
|
* full hotplug is in progress. In that case, all child
|
|
|
|
* PCI devices of the PE are expected to be removed prior
|
|
|
|
* to PE reset.
|
|
|
|
*/
|
2016-02-09 12:50:21 +08:00
|
|
|
if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
|
2015-03-17 13:15:06 +08:00
|
|
|
edev->pe->bus = pci_find_bus(hose->global_number,
|
|
|
|
pdn->busno);
|
2016-02-09 12:50:21 +08:00
|
|
|
if (edev->pe->bus)
|
|
|
|
edev->pe->state |= EEH_PE_PRI_BUS;
|
|
|
|
}
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable EEH explicitly so that we will do EEH check
|
|
|
|
* while accessing I/O stuff
|
|
|
|
*/
|
2014-07-17 12:41:38 +08:00
|
|
|
eeh_add_flag(EEH_ENABLED);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
/* Save memory bars */
|
|
|
|
eeh_save_bars(edev);
|
|
|
|
|
2015-03-17 13:15:06 +08:00
|
|
|
return NULL;
|
2013-06-20 13:21:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
|
|
|
* @option: operation to be issued
|
|
|
|
*
|
|
|
|
* The function is used to control the EEH functionality globally.
|
|
|
|
* Currently, following options are support according to PAPR:
|
|
|
|
* Enable EEH, Disable EEH, Enable MMIO and Enable DMA
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
|
|
|
struct pci_controller *hose = pe->phb;
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
2015-02-16 11:45:44 +08:00
|
|
|
bool freeze_pe = false;
|
2015-10-08 11:58:59 +08:00
|
|
|
int opt;
|
2015-02-16 11:45:44 +08:00
|
|
|
s64 rc;
|
|
|
|
|
|
|
|
switch (option) {
|
|
|
|
case EEH_OPT_DISABLE:
|
|
|
|
return -EPERM;
|
|
|
|
case EEH_OPT_ENABLE:
|
|
|
|
return 0;
|
|
|
|
case EEH_OPT_THAW_MMIO:
|
|
|
|
opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
|
|
|
|
break;
|
|
|
|
case EEH_OPT_THAW_DMA:
|
|
|
|
opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
|
|
|
|
break;
|
|
|
|
case EEH_OPT_FREEZE_PE:
|
|
|
|
freeze_pe = true;
|
|
|
|
opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_warn("%s: Invalid option %d\n", __func__, option);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-10-08 11:58:59 +08:00
|
|
|
/* Freeze master and slave PEs if PHB supports compound PEs */
|
2015-02-16 11:45:44 +08:00
|
|
|
if (freeze_pe) {
|
|
|
|
if (phb->freeze_pe) {
|
|
|
|
phb->freeze_pe(phb, pe->addr);
|
2015-10-08 11:58:59 +08:00
|
|
|
return 0;
|
2015-02-16 11:45:44 +08:00
|
|
|
}
|
2015-10-08 11:58:59 +08:00
|
|
|
|
|
|
|
rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
|
|
|
|
__func__, rc, phb->hose->global_number,
|
|
|
|
pe->addr);
|
|
|
|
return -EIO;
|
2015-02-16 11:45:44 +08:00
|
|
|
}
|
2015-10-08 11:58:59 +08:00
|
|
|
|
|
|
|
return 0;
|
2015-02-16 11:45:44 +08:00
|
|
|
}
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-10-08 11:58:59 +08:00
|
|
|
/* Unfreeze master and slave PEs if PHB supports */
|
|
|
|
if (phb->unfreeze_pe)
|
|
|
|
return phb->unfreeze_pe(phb, pe->addr, opt);
|
|
|
|
|
|
|
|
rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
|
|
|
|
__func__, rc, option, phb->hose->global_number,
|
|
|
|
pe->addr);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2013-06-20 13:21:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_get_pe_addr - Retrieve PE address
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
|
|
|
*
|
|
|
|
* Retrieve the PE address according to the given tranditional
|
|
|
|
* PCI BDF (Bus/Device/Function) address.
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
|
|
|
return pe->addr;
|
|
|
|
}
|
|
|
|
|
2015-02-16 11:45:45 +08:00
|
|
|
static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = pe->phb->private_data;
|
|
|
|
s64 rc;
|
|
|
|
|
|
|
|
rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
|
2017-06-14 12:19:59 +08:00
|
|
|
phb->diag_data_size);
|
2015-02-16 11:45:45 +08:00
|
|
|
if (rc != OPAL_SUCCESS)
|
|
|
|
pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
|
|
|
|
__func__, rc, pe->phb->global_number);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = pe->phb->private_data;
|
|
|
|
u8 fstate;
|
|
|
|
__be16 pcierr;
|
|
|
|
s64 rc;
|
|
|
|
int result = 0;
|
|
|
|
|
|
|
|
rc = opal_pci_eeh_freeze_status(phb->opal_id,
|
|
|
|
pe->addr,
|
|
|
|
&fstate,
|
|
|
|
&pcierr,
|
|
|
|
NULL);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failure %lld getting PHB#%x state\n",
|
|
|
|
__func__, rc, phb->hose->global_number);
|
|
|
|
return EEH_STATE_NOT_SUPPORT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check PHB state. If the PHB is frozen for the
|
|
|
|
* first time, to dump the PHB diag-data.
|
|
|
|
*/
|
|
|
|
if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
|
|
|
|
result = (EEH_STATE_MMIO_ACTIVE |
|
|
|
|
EEH_STATE_DMA_ACTIVE |
|
|
|
|
EEH_STATE_MMIO_ENABLED |
|
|
|
|
EEH_STATE_DMA_ENABLED);
|
|
|
|
} else if (!(pe->state & EEH_PE_ISOLATED)) {
|
|
|
|
eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
|
|
|
|
pnv_eeh_get_phb_diag(pe);
|
|
|
|
|
|
|
|
if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
|
|
|
|
pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = pe->phb->private_data;
|
|
|
|
u8 fstate;
|
|
|
|
__be16 pcierr;
|
|
|
|
s64 rc;
|
|
|
|
int result;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't clobber hardware frozen state until PE
|
|
|
|
* reset is completed. In order to keep EEH core
|
|
|
|
* moving forward, we have to return operational
|
|
|
|
* state during PE reset.
|
|
|
|
*/
|
|
|
|
if (pe->state & EEH_PE_RESET) {
|
|
|
|
result = (EEH_STATE_MMIO_ACTIVE |
|
|
|
|
EEH_STATE_DMA_ACTIVE |
|
|
|
|
EEH_STATE_MMIO_ENABLED |
|
|
|
|
EEH_STATE_DMA_ENABLED);
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fetch PE state from hardware. If the PHB
|
|
|
|
* supports compound PE, let it handle that.
|
|
|
|
*/
|
|
|
|
if (phb->get_pe_state) {
|
|
|
|
fstate = phb->get_pe_state(phb, pe->addr);
|
|
|
|
} else {
|
|
|
|
rc = opal_pci_eeh_freeze_status(phb->opal_id,
|
|
|
|
pe->addr,
|
|
|
|
&fstate,
|
|
|
|
&pcierr,
|
|
|
|
NULL);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
|
|
|
|
__func__, rc, phb->hose->global_number,
|
|
|
|
pe->addr);
|
|
|
|
return EEH_STATE_NOT_SUPPORT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Figure out state */
|
|
|
|
switch (fstate) {
|
|
|
|
case OPAL_EEH_STOPPED_NOT_FROZEN:
|
|
|
|
result = (EEH_STATE_MMIO_ACTIVE |
|
|
|
|
EEH_STATE_DMA_ACTIVE |
|
|
|
|
EEH_STATE_MMIO_ENABLED |
|
|
|
|
EEH_STATE_DMA_ENABLED);
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_STOPPED_MMIO_FREEZE:
|
|
|
|
result = (EEH_STATE_DMA_ACTIVE |
|
|
|
|
EEH_STATE_DMA_ENABLED);
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_STOPPED_DMA_FREEZE:
|
|
|
|
result = (EEH_STATE_MMIO_ACTIVE |
|
|
|
|
EEH_STATE_MMIO_ENABLED);
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
|
|
|
|
result = 0;
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_STOPPED_RESET:
|
|
|
|
result = EEH_STATE_RESET_ACTIVE;
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
|
|
|
|
result = EEH_STATE_UNAVAILABLE;
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_STOPPED_PERM_UNAVAIL:
|
|
|
|
result = EEH_STATE_NOT_SUPPORT;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
result = EEH_STATE_NOT_SUPPORT;
|
|
|
|
pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
|
|
|
|
__func__, phb->hose->global_number,
|
|
|
|
pe->addr, fstate);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If PHB supports compound PE, to freeze all
|
|
|
|
* slave PEs for consistency.
|
|
|
|
*
|
|
|
|
* If the PE is switching to frozen state for the
|
|
|
|
* first time, to dump the PHB diag-data.
|
|
|
|
*/
|
|
|
|
if (!(result & EEH_STATE_NOT_SUPPORT) &&
|
|
|
|
!(result & EEH_STATE_UNAVAILABLE) &&
|
|
|
|
!(result & EEH_STATE_MMIO_ACTIVE) &&
|
|
|
|
!(result & EEH_STATE_DMA_ACTIVE) &&
|
|
|
|
!(pe->state & EEH_PE_ISOLATED)) {
|
|
|
|
if (phb->freeze_pe)
|
|
|
|
phb->freeze_pe(phb, pe->addr);
|
|
|
|
|
|
|
|
eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
|
|
|
|
pnv_eeh_get_phb_diag(pe);
|
|
|
|
|
|
|
|
if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
|
|
|
|
pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2013-06-20 13:21:13 +08:00
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_get_state - Retrieve PE state
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
|
|
|
* @delay: delay while PE state is temporarily unavailable
|
|
|
|
*
|
|
|
|
* Retrieve the state of the specified PE. For IODA-compitable
|
|
|
|
* platform, it should be retrieved from IODA table. Therefore,
|
|
|
|
* we prefer passing down to hardware implementation to handle
|
|
|
|
* it.
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
2015-02-16 11:45:45 +08:00
|
|
|
int ret;
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-02-16 11:45:45 +08:00
|
|
|
if (pe->type & EEH_PE_PHB)
|
|
|
|
ret = pnv_eeh_get_phb_state(pe);
|
|
|
|
else
|
|
|
|
ret = pnv_eeh_get_pe_state(pe);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-02-16 11:45:45 +08:00
|
|
|
if (!delay)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the PE state is temporarily unavailable,
|
|
|
|
* to inform the EEH core delay for default
|
|
|
|
* period (1 second)
|
|
|
|
*/
|
|
|
|
*delay = 0;
|
|
|
|
if (ret & EEH_STATE_UNAVAILABLE)
|
|
|
|
*delay = 1000;
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-05-20 14:41:38 +08:00
|
|
|
static s64 pnv_eeh_poll(unsigned long id)
|
2015-02-16 11:45:47 +08:00
|
|
|
{
|
|
|
|
s64 rc = OPAL_HARDWARE;
|
|
|
|
|
|
|
|
while (1) {
|
2016-05-20 14:41:38 +08:00
|
|
|
rc = opal_pci_poll(id);
|
2015-02-16 11:45:47 +08:00
|
|
|
if (rc <= 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (system_state < SYSTEM_RUNNING)
|
|
|
|
udelay(1000 * rc);
|
|
|
|
else
|
|
|
|
msleep(rc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
|
|
|
s64 rc = OPAL_HARDWARE;
|
|
|
|
|
|
|
|
pr_debug("%s: Reset PHB#%x, option=%d\n",
|
|
|
|
__func__, hose->global_number, option);
|
|
|
|
|
|
|
|
/* Issue PHB complete reset request */
|
|
|
|
if (option == EEH_RESET_FUNDAMENTAL ||
|
|
|
|
option == EEH_RESET_HOT)
|
|
|
|
rc = opal_pci_reset(phb->opal_id,
|
|
|
|
OPAL_RESET_PHB_COMPLETE,
|
|
|
|
OPAL_ASSERT_RESET);
|
|
|
|
else if (option == EEH_RESET_DEACTIVATE)
|
|
|
|
rc = opal_pci_reset(phb->opal_id,
|
|
|
|
OPAL_RESET_PHB_COMPLETE,
|
|
|
|
OPAL_DEASSERT_RESET);
|
|
|
|
if (rc < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Poll state of the PHB until the request is done
|
|
|
|
* successfully. The PHB reset is usually PHB complete
|
|
|
|
* reset followed by hot reset on root bus. So we also
|
|
|
|
* need the PCI bus settlement delay.
|
|
|
|
*/
|
2016-06-24 14:44:19 +08:00
|
|
|
if (rc > 0)
|
|
|
|
rc = pnv_eeh_poll(phb->opal_id);
|
2015-02-16 11:45:47 +08:00
|
|
|
if (option == EEH_RESET_DEACTIVATE) {
|
|
|
|
if (system_state < SYSTEM_RUNNING)
|
|
|
|
udelay(1000 * EEH_PE_RST_SETTLE_TIME);
|
|
|
|
else
|
|
|
|
msleep(EEH_PE_RST_SETTLE_TIME);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
if (rc != OPAL_SUCCESS)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
|
|
|
s64 rc = OPAL_HARDWARE;
|
|
|
|
|
|
|
|
pr_debug("%s: Reset PHB#%x, option=%d\n",
|
|
|
|
__func__, hose->global_number, option);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* During the reset deassert time, we needn't care
|
|
|
|
* the reset scope because the firmware does nothing
|
|
|
|
* for fundamental or hot reset during deassert phase.
|
|
|
|
*/
|
|
|
|
if (option == EEH_RESET_FUNDAMENTAL)
|
|
|
|
rc = opal_pci_reset(phb->opal_id,
|
|
|
|
OPAL_RESET_PCI_FUNDAMENTAL,
|
|
|
|
OPAL_ASSERT_RESET);
|
|
|
|
else if (option == EEH_RESET_HOT)
|
|
|
|
rc = opal_pci_reset(phb->opal_id,
|
|
|
|
OPAL_RESET_PCI_HOT,
|
|
|
|
OPAL_ASSERT_RESET);
|
|
|
|
else if (option == EEH_RESET_DEACTIVATE)
|
|
|
|
rc = opal_pci_reset(phb->opal_id,
|
|
|
|
OPAL_RESET_PCI_HOT,
|
|
|
|
OPAL_DEASSERT_RESET);
|
|
|
|
if (rc < 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* Poll state of the PHB until the request is done */
|
2016-06-24 14:44:19 +08:00
|
|
|
if (rc > 0)
|
|
|
|
rc = pnv_eeh_poll(phb->opal_id);
|
2015-02-16 11:45:47 +08:00
|
|
|
if (option == EEH_RESET_DEACTIVATE)
|
|
|
|
msleep(EEH_PE_RST_SETTLE_TIME);
|
|
|
|
out:
|
|
|
|
if (rc != OPAL_SUCCESS)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-20 14:41:39 +08:00
|
|
|
static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
|
2015-02-16 11:45:47 +08:00
|
|
|
{
|
2015-03-17 13:15:07 +08:00
|
|
|
struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
|
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
2015-02-16 11:45:47 +08:00
|
|
|
int aer = edev ? edev->aer_cap : 0;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
|
|
|
|
__func__, pci_domain_nr(dev->bus),
|
|
|
|
dev->bus->number, option);
|
|
|
|
|
|
|
|
switch (option) {
|
|
|
|
case EEH_RESET_FUNDAMENTAL:
|
|
|
|
case EEH_RESET_HOT:
|
|
|
|
/* Don't report linkDown event */
|
|
|
|
if (aer) {
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
|
2015-02-16 11:45:47 +08:00
|
|
|
4, &ctrl);
|
|
|
|
ctrl |= PCI_ERR_UNC_SURPDN;
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
|
2015-02-16 11:45:47 +08:00
|
|
|
4, ctrl);
|
|
|
|
}
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
|
2015-02-16 11:45:47 +08:00
|
|
|
ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
|
2015-02-16 11:45:47 +08:00
|
|
|
|
|
|
|
msleep(EEH_PE_RST_HOLD_TIME);
|
|
|
|
break;
|
|
|
|
case EEH_RESET_DEACTIVATE:
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
|
2015-02-16 11:45:47 +08:00
|
|
|
ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
|
2015-02-16 11:45:47 +08:00
|
|
|
|
|
|
|
msleep(EEH_PE_RST_SETTLE_TIME);
|
|
|
|
|
|
|
|
/* Continue reporting linkDown event */
|
|
|
|
if (aer) {
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
|
2015-02-16 11:45:47 +08:00
|
|
|
4, &ctrl);
|
|
|
|
ctrl &= ~PCI_ERR_UNC_SURPDN;
|
2015-03-17 13:15:07 +08:00
|
|
|
eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
|
2015-02-16 11:45:47 +08:00
|
|
|
4, ctrl);
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-20 14:41:39 +08:00
|
|
|
static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
|
|
|
struct device_node *dn = pci_device_to_OF_node(pdev);
|
|
|
|
uint64_t id = PCI_SLOT_ID(phb->opal_id,
|
|
|
|
(pdev->bus->number << 8) | pdev->devfn);
|
|
|
|
uint8_t scope;
|
|
|
|
int64_t rc;
|
|
|
|
|
|
|
|
/* Hot reset to the bus if firmware cannot handle */
|
|
|
|
if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
|
|
|
|
return __pnv_eeh_bridge_reset(pdev, option);
|
|
|
|
|
|
|
|
switch (option) {
|
|
|
|
case EEH_RESET_FUNDAMENTAL:
|
|
|
|
scope = OPAL_RESET_PCI_FUNDAMENTAL;
|
|
|
|
break;
|
|
|
|
case EEH_RESET_HOT:
|
|
|
|
scope = OPAL_RESET_PCI_HOT;
|
|
|
|
break;
|
|
|
|
case EEH_RESET_DEACTIVATE:
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
|
|
|
|
__func__, option);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
|
|
|
|
if (rc <= OPAL_SUCCESS)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
rc = pnv_eeh_poll(id);
|
|
|
|
out:
|
|
|
|
return (rc == OPAL_SUCCESS) ? 0 : -EIO;
|
|
|
|
}
|
|
|
|
|
2015-02-16 11:45:47 +08:00
|
|
|
void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
|
|
|
|
{
|
2016-05-12 17:43:37 +08:00
|
|
|
struct pci_controller *hose;
|
|
|
|
|
|
|
|
if (pci_is_root_bus(dev->bus)) {
|
|
|
|
hose = pci_bus_to_host(dev->bus);
|
|
|
|
pnv_eeh_root_reset(hose, EEH_RESET_HOT);
|
|
|
|
pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
|
|
|
|
} else {
|
|
|
|
pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
|
|
|
|
pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
|
|
|
|
}
|
2015-02-16 11:45:47 +08:00
|
|
|
}
|
|
|
|
|
2016-03-04 07:53:09 +08:00
|
|
|
static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
|
|
|
|
int pos, u16 mask)
|
|
|
|
{
|
|
|
|
int i, status = 0;
|
|
|
|
|
|
|
|
/* Wait for Transaction Pending bit to be cleared */
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
eeh_ops->read_config(pdn, pos, 2, &status);
|
|
|
|
if (!(status & mask))
|
|
|
|
return;
|
|
|
|
|
|
|
|
msleep((1 << i) * 100);
|
|
|
|
}
|
|
|
|
|
|
|
|
pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
|
|
|
|
__func__, type,
|
2017-08-29 15:34:01 +08:00
|
|
|
pdn->phb->global_number, pdn->busno,
|
2016-03-04 07:53:09 +08:00
|
|
|
PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
|
|
|
|
{
|
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
|
|
|
u32 reg = 0;
|
|
|
|
|
|
|
|
if (WARN_ON(!edev->pcie_cap))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®);
|
|
|
|
if (!(reg & PCI_EXP_DEVCAP_FLR))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
switch (option) {
|
|
|
|
case EEH_RESET_HOT:
|
|
|
|
case EEH_RESET_FUNDAMENTAL:
|
|
|
|
pnv_eeh_wait_for_pending(pdn, "",
|
|
|
|
edev->pcie_cap + PCI_EXP_DEVSTA,
|
|
|
|
PCI_EXP_DEVSTA_TRPND);
|
|
|
|
eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
|
|
|
|
4, ®);
|
|
|
|
reg |= PCI_EXP_DEVCTL_BCR_FLR;
|
|
|
|
eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
|
|
|
|
4, reg);
|
|
|
|
msleep(EEH_PE_RST_HOLD_TIME);
|
|
|
|
break;
|
|
|
|
case EEH_RESET_DEACTIVATE:
|
|
|
|
eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
|
|
|
|
4, ®);
|
|
|
|
reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
|
|
|
|
eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
|
|
|
|
4, reg);
|
|
|
|
msleep(EEH_PE_RST_SETTLE_TIME);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
|
|
|
|
{
|
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
|
|
|
u32 cap = 0;
|
|
|
|
|
|
|
|
if (WARN_ON(!edev->af_cap))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
|
|
|
|
if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
switch (option) {
|
|
|
|
case EEH_RESET_HOT:
|
|
|
|
case EEH_RESET_FUNDAMENTAL:
|
|
|
|
/*
|
|
|
|
* Wait for Transaction Pending bit to clear. A word-aligned
|
|
|
|
* test is used, so we use the conrol offset rather than status
|
|
|
|
* and shift the test bit to match.
|
|
|
|
*/
|
|
|
|
pnv_eeh_wait_for_pending(pdn, "AF",
|
|
|
|
edev->af_cap + PCI_AF_CTRL,
|
|
|
|
PCI_AF_STATUS_TP << 8);
|
|
|
|
eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
|
|
|
|
1, PCI_AF_CTRL_FLR);
|
|
|
|
msleep(EEH_PE_RST_HOLD_TIME);
|
|
|
|
break;
|
|
|
|
case EEH_RESET_DEACTIVATE:
|
|
|
|
eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
|
|
|
|
msleep(EEH_PE_RST_SETTLE_TIME);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
|
|
|
|
{
|
|
|
|
struct eeh_dev *edev;
|
|
|
|
struct pci_dn *pdn;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* The VF PE should have only one child device */
|
|
|
|
edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
|
|
|
|
pdn = eeh_dev_to_pdn(edev);
|
|
|
|
if (!pdn)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
ret = pnv_eeh_do_flr(pdn, option);
|
|
|
|
if (!ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return pnv_eeh_do_af_flr(pdn, option);
|
|
|
|
}
|
|
|
|
|
2013-06-20 13:21:13 +08:00
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_reset - Reset the specified PE
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
|
|
|
* @option: reset option
|
|
|
|
*
|
2015-02-16 11:45:47 +08:00
|
|
|
* Do reset on the indicated PE. For PCI bus sensitive PE,
|
|
|
|
* we need to reset the parent p2p bridge. The PHB has to
|
|
|
|
* be reinitialized if the p2p bridge is root bridge. For
|
|
|
|
* PCI device sensitive PE, we will try to reset the device
|
|
|
|
* through FLR. For now, we don't have OPAL APIs to do HARD
|
|
|
|
* reset yet, so all reset would be SOFT (HOT) reset.
|
2013-06-20 13:21:13 +08:00
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_reset(struct eeh_pe *pe, int option)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
|
|
|
struct pci_controller *hose = pe->phb;
|
2016-05-03 13:41:44 +08:00
|
|
|
struct pnv_phb *phb;
|
2015-02-16 11:45:47 +08:00
|
|
|
struct pci_bus *bus;
|
2016-05-03 13:41:44 +08:00
|
|
|
int64_t rc;
|
2015-02-16 11:45:47 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For PHB reset, we always have complete reset. For those PEs whose
|
|
|
|
* primary bus derived from root complex (root bus) or root port
|
|
|
|
* (usually bus#1), we apply hot or fundamental reset on the root port.
|
|
|
|
* For other PEs, we always have hot reset on the PE primary bus.
|
|
|
|
*
|
|
|
|
* Here, we have different design to pHyp, which always clear the
|
|
|
|
* frozen state during PE reset. However, the good idea here from
|
|
|
|
* benh is to keep frozen state before we get PE reset done completely
|
|
|
|
* (until BAR restore). With the frozen state, HW drops illegal IO
|
|
|
|
* or MMIO access, which can incur recrusive frozen PE during PE
|
|
|
|
* reset. The side effect is that EEH core has to clear the frozen
|
|
|
|
* state explicitly after BAR restore.
|
|
|
|
*/
|
2016-05-03 13:41:44 +08:00
|
|
|
if (pe->type & EEH_PE_PHB)
|
|
|
|
return pnv_eeh_phb_reset(hose, option);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2016-05-03 13:41:44 +08:00
|
|
|
/*
|
|
|
|
* The frozen PE might be caused by PAPR error injection
|
|
|
|
* registers, which are expected to be cleared after hitting
|
|
|
|
* frozen PE as stated in the hardware spec. Unfortunately,
|
|
|
|
* that's not true on P7IOC. So we have to clear it manually
|
|
|
|
* to avoid recursive EEH errors during recovery.
|
|
|
|
*/
|
|
|
|
phb = hose->private_data;
|
|
|
|
if (phb->model == PNV_PHB_MODEL_P7IOC &&
|
|
|
|
(option == EEH_RESET_HOT ||
|
|
|
|
option == EEH_RESET_FUNDAMENTAL)) {
|
|
|
|
rc = opal_pci_reset(phb->opal_id,
|
|
|
|
OPAL_RESET_PHB_ERROR,
|
|
|
|
OPAL_ASSERT_RESET);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failure %lld clearing error injection registers\n",
|
|
|
|
__func__, rc);
|
|
|
|
return -EIO;
|
2015-02-16 11:45:47 +08:00
|
|
|
}
|
|
|
|
}
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2016-09-12 12:17:23 +08:00
|
|
|
if (pe->type & EEH_PE_VF)
|
|
|
|
return pnv_eeh_reset_vf_pe(pe, option);
|
|
|
|
|
2016-05-03 13:41:44 +08:00
|
|
|
bus = eeh_pe_bus_get(pe);
|
2016-09-12 12:17:22 +08:00
|
|
|
if (!bus) {
|
2016-11-16 11:02:15 +08:00
|
|
|
pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n",
|
2016-09-12 12:17:22 +08:00
|
|
|
__func__, pe->phb->global_number, pe->addr);
|
|
|
|
return -EIO;
|
|
|
|
}
|
2016-05-03 13:41:44 +08:00
|
|
|
|
2016-07-22 15:16:35 +08:00
|
|
|
/*
|
|
|
|
* If dealing with the root bus (or the bus underneath the
|
|
|
|
* root port), we reset the bus underneath the root port.
|
|
|
|
*
|
|
|
|
* The cxl driver depends on this behaviour for bi-modal card
|
|
|
|
* switching.
|
|
|
|
*/
|
2016-05-03 13:41:44 +08:00
|
|
|
if (pci_is_root_bus(bus) ||
|
|
|
|
pci_is_root_bus(bus->parent))
|
|
|
|
return pnv_eeh_root_reset(hose, option);
|
|
|
|
|
|
|
|
return pnv_eeh_bridge_reset(bus->self, option);
|
2013-06-20 13:21:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_wait_state - Wait for PE state
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
2015-04-27 09:25:10 +08:00
|
|
|
* @max_wait: maximal period in millisecond
|
2013-06-20 13:21:13 +08:00
|
|
|
*
|
|
|
|
* Wait for the state of associated PE. It might take some time
|
|
|
|
* to retrieve the PE's state.
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
int mwait;
|
|
|
|
|
|
|
|
while (1) {
|
2015-02-16 11:45:39 +08:00
|
|
|
ret = pnv_eeh_get_state(pe, &mwait);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If the PE's state is temporarily unavailable,
|
|
|
|
* we have to wait for the specified time. Otherwise,
|
|
|
|
* the PE's state will be returned immediately.
|
|
|
|
*/
|
|
|
|
if (ret != EEH_STATE_UNAVAILABLE)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (max_wait <= 0) {
|
2014-07-17 12:41:41 +08:00
|
|
|
pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
|
|
|
|
__func__, pe->addr, max_wait);
|
2013-06-20 13:21:13 +08:00
|
|
|
return EEH_STATE_NOT_SUPPORT;
|
|
|
|
}
|
|
|
|
|
2015-04-27 09:25:11 +08:00
|
|
|
max_wait -= mwait;
|
2013-06-20 13:21:13 +08:00
|
|
|
msleep(mwait);
|
|
|
|
}
|
|
|
|
|
|
|
|
return EEH_STATE_NOT_SUPPORT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_get_log - Retrieve error log
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
|
|
|
* @severity: temporary or permanent error log
|
|
|
|
* @drv_log: driver log to be combined with retrieved error log
|
|
|
|
* @len: length of driver log
|
|
|
|
*
|
|
|
|
* Retrieve the temporary or permanent error from the PE.
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
|
|
|
|
char *drv_log, unsigned long len)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
2015-02-16 11:45:42 +08:00
|
|
|
if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
|
|
|
|
pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-02-16 11:45:42 +08:00
|
|
|
return 0;
|
2013-06-20 13:21:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: EEH PE
|
|
|
|
*
|
|
|
|
* The function will be called to reconfigure the bridges included
|
|
|
|
* in the specified PE so that the mulfunctional PE would be recovered
|
|
|
|
* again.
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
2015-02-16 11:45:43 +08:00
|
|
|
return 0;
|
2013-06-20 13:21:13 +08:00
|
|
|
}
|
|
|
|
|
2014-09-30 10:38:56 +08:00
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_pe_err_inject - Inject specified error to the indicated PE
|
2014-09-30 10:38:56 +08:00
|
|
|
* @pe: the indicated PE
|
|
|
|
* @type: error type
|
|
|
|
* @func: specific error type
|
|
|
|
* @addr: address
|
|
|
|
* @mask: address mask
|
|
|
|
*
|
|
|
|
* The routine is called to inject specified error, which is
|
|
|
|
* determined by @type and @func, to the indicated PE for
|
|
|
|
* testing purpose.
|
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
|
|
|
|
unsigned long addr, unsigned long mask)
|
2014-09-30 10:38:56 +08:00
|
|
|
{
|
|
|
|
struct pci_controller *hose = pe->phb;
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
2015-02-16 11:45:40 +08:00
|
|
|
s64 rc;
|
|
|
|
|
|
|
|
if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
|
|
|
|
type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
|
|
|
|
pr_warn("%s: Invalid error type %d\n",
|
|
|
|
__func__, type);
|
|
|
|
return -ERANGE;
|
|
|
|
}
|
2014-09-30 10:38:56 +08:00
|
|
|
|
2015-02-16 11:45:40 +08:00
|
|
|
if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
|
|
|
|
func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
|
|
|
|
pr_warn("%s: Invalid error function %d\n",
|
|
|
|
__func__, func);
|
|
|
|
return -ERANGE;
|
|
|
|
}
|
2014-09-30 10:38:56 +08:00
|
|
|
|
2015-02-16 11:45:40 +08:00
|
|
|
/* Firmware supports error injection ? */
|
|
|
|
if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
|
|
|
|
pr_warn("%s: Firmware doesn't support error injection\n",
|
|
|
|
__func__);
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Do error injection */
|
|
|
|
rc = opal_pci_err_inject(phb->opal_id, pe->addr,
|
|
|
|
type, func, addr, mask);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failure %lld injecting error "
|
|
|
|
"%d-%d to PHB#%x-PE#%x\n",
|
|
|
|
__func__, rc, type, func,
|
|
|
|
hose->global_number, pe->addr);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2014-09-30 10:38:56 +08:00
|
|
|
}
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
|
2014-10-01 15:07:51 +08:00
|
|
|
{
|
2015-03-17 13:15:07 +08:00
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
2014-10-01 15:07:51 +08:00
|
|
|
|
|
|
|
if (!edev || !edev->pe)
|
|
|
|
return false;
|
|
|
|
|
2016-03-04 07:53:09 +08:00
|
|
|
/*
|
|
|
|
* We will issue FLR or AF FLR to all VFs, which are contained
|
|
|
|
* in VF PE. It relies on the EEH PCI config accessors. So we
|
|
|
|
* can't block them during the window.
|
|
|
|
*/
|
|
|
|
if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
|
|
|
|
return false;
|
|
|
|
|
2014-10-01 15:07:51 +08:00
|
|
|
if (edev->pe->state & EEH_PE_CFG_BLOCKED)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
static int pnv_eeh_read_config(struct pci_dn *pdn,
|
2015-02-16 11:45:39 +08:00
|
|
|
int where, int size, u32 *val)
|
2014-10-01 15:07:51 +08:00
|
|
|
{
|
2015-03-17 13:15:03 +08:00
|
|
|
if (!pdn)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
if (pnv_eeh_cfg_blocked(pdn)) {
|
2014-10-01 15:07:51 +08:00
|
|
|
*val = 0xFFFFFFFF;
|
|
|
|
return PCIBIOS_SET_FAILED;
|
|
|
|
}
|
|
|
|
|
2015-03-17 13:15:03 +08:00
|
|
|
return pnv_pci_cfg_read(pdn, where, size, val);
|
2014-10-01 15:07:51 +08:00
|
|
|
}
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
static int pnv_eeh_write_config(struct pci_dn *pdn,
|
2015-02-16 11:45:39 +08:00
|
|
|
int where, int size, u32 val)
|
2014-10-01 15:07:51 +08:00
|
|
|
{
|
2015-03-17 13:15:03 +08:00
|
|
|
if (!pdn)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
if (pnv_eeh_cfg_blocked(pdn))
|
2014-10-01 15:07:51 +08:00
|
|
|
return PCIBIOS_SET_FAILED;
|
|
|
|
|
2015-03-17 13:15:03 +08:00
|
|
|
return pnv_pci_cfg_write(pdn, where, size, val);
|
2014-10-01 15:07:51 +08:00
|
|
|
}
|
|
|
|
|
2015-02-16 11:45:46 +08:00
|
|
|
static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
|
|
|
|
{
|
|
|
|
/* GEM */
|
|
|
|
if (data->gemXfir || data->gemRfir ||
|
|
|
|
data->gemRirqfir || data->gemMask || data->gemRwof)
|
|
|
|
pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
|
|
|
|
be64_to_cpu(data->gemXfir),
|
|
|
|
be64_to_cpu(data->gemRfir),
|
|
|
|
be64_to_cpu(data->gemRirqfir),
|
|
|
|
be64_to_cpu(data->gemMask),
|
|
|
|
be64_to_cpu(data->gemRwof));
|
|
|
|
|
|
|
|
/* LEM */
|
|
|
|
if (data->lemFir || data->lemErrMask ||
|
|
|
|
data->lemAction0 || data->lemAction1 || data->lemWof)
|
|
|
|
pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
|
|
|
|
be64_to_cpu(data->lemFir),
|
|
|
|
be64_to_cpu(data->lemErrMask),
|
|
|
|
be64_to_cpu(data->lemAction0),
|
|
|
|
be64_to_cpu(data->lemAction1),
|
|
|
|
be64_to_cpu(data->lemWof));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
2017-06-14 12:19:59 +08:00
|
|
|
struct OpalIoP7IOCErrorData *data =
|
|
|
|
(struct OpalIoP7IOCErrorData*)phb->diag_data;
|
2015-02-16 11:45:46 +08:00
|
|
|
long rc;
|
|
|
|
|
|
|
|
rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
|
|
|
|
__func__, phb->hub_id, rc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-08-02 12:10:30 +08:00
|
|
|
switch (be16_to_cpu(data->type)) {
|
2015-02-16 11:45:46 +08:00
|
|
|
case OPAL_P7IOC_DIAG_TYPE_RGC:
|
|
|
|
pr_info("P7IOC diag-data for RGC\n\n");
|
|
|
|
pnv_eeh_dump_hub_diag_common(data);
|
|
|
|
if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
|
|
|
|
pr_info(" RGC: %016llx %016llx\n",
|
|
|
|
be64_to_cpu(data->rgc.rgcStatus),
|
|
|
|
be64_to_cpu(data->rgc.rgcLdcp));
|
|
|
|
break;
|
|
|
|
case OPAL_P7IOC_DIAG_TYPE_BI:
|
|
|
|
pr_info("P7IOC diag-data for BI %s\n\n",
|
|
|
|
data->bi.biDownbound ? "Downbound" : "Upbound");
|
|
|
|
pnv_eeh_dump_hub_diag_common(data);
|
|
|
|
if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
|
|
|
|
data->bi.biLdcp2 || data->bi.biFenceStatus)
|
|
|
|
pr_info(" BI: %016llx %016llx %016llx %016llx\n",
|
|
|
|
be64_to_cpu(data->bi.biLdcp0),
|
|
|
|
be64_to_cpu(data->bi.biLdcp1),
|
|
|
|
be64_to_cpu(data->bi.biLdcp2),
|
|
|
|
be64_to_cpu(data->bi.biFenceStatus));
|
|
|
|
break;
|
|
|
|
case OPAL_P7IOC_DIAG_TYPE_CI:
|
|
|
|
pr_info("P7IOC diag-data for CI Port %d\n\n",
|
|
|
|
data->ci.ciPort);
|
|
|
|
pnv_eeh_dump_hub_diag_common(data);
|
|
|
|
if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
|
|
|
|
pr_info(" CI: %016llx %016llx\n",
|
|
|
|
be64_to_cpu(data->ci.ciPortStatus),
|
|
|
|
be64_to_cpu(data->ci.ciPortLdcp));
|
|
|
|
break;
|
|
|
|
case OPAL_P7IOC_DIAG_TYPE_MISC:
|
|
|
|
pr_info("P7IOC diag-data for MISC\n\n");
|
|
|
|
pnv_eeh_dump_hub_diag_common(data);
|
|
|
|
break;
|
|
|
|
case OPAL_P7IOC_DIAG_TYPE_I2C:
|
|
|
|
pr_info("P7IOC diag-data for I2C\n\n");
|
|
|
|
pnv_eeh_dump_hub_diag_common(data);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
|
|
|
|
__func__, phb->hub_id, data->type);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pnv_eeh_get_pe(struct pci_controller *hose,
|
|
|
|
u16 pe_no, struct eeh_pe **pe)
|
|
|
|
{
|
|
|
|
struct pnv_phb *phb = hose->private_data;
|
|
|
|
struct pnv_ioda_pe *pnv_pe;
|
|
|
|
struct eeh_pe *dev_pe;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If PHB supports compound PE, to fetch
|
|
|
|
* the master PE because slave PE is invisible
|
|
|
|
* to EEH core.
|
|
|
|
*/
|
|
|
|
pnv_pe = &phb->ioda.pe_array[pe_no];
|
|
|
|
if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
|
|
|
|
pnv_pe = pnv_pe->master;
|
|
|
|
WARN_ON(!pnv_pe ||
|
|
|
|
!(pnv_pe->flags & PNV_IODA_PE_MASTER));
|
|
|
|
pe_no = pnv_pe->pe_number;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Find the PE according to PE# */
|
2017-08-29 15:34:00 +08:00
|
|
|
dev_pe = eeh_pe_get(hose, pe_no, 0);
|
2015-02-16 11:45:46 +08:00
|
|
|
if (!dev_pe)
|
|
|
|
return -EEXIST;
|
|
|
|
|
|
|
|
/* Freeze the (compound) PE */
|
|
|
|
*pe = dev_pe;
|
|
|
|
if (!(dev_pe->state & EEH_PE_ISOLATED))
|
|
|
|
phb->freeze_pe(phb, pe_no);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* At this point, we're sure the (compound) PE should
|
|
|
|
* have been frozen. However, we still need poke until
|
|
|
|
* hitting the frozen PE on top level.
|
|
|
|
*/
|
|
|
|
dev_pe = dev_pe->parent;
|
|
|
|
while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
|
|
|
|
int ret;
|
|
|
|
int active_flags = (EEH_STATE_MMIO_ACTIVE |
|
|
|
|
EEH_STATE_DMA_ACTIVE);
|
|
|
|
|
|
|
|
ret = eeh_ops->get_state(dev_pe, NULL);
|
|
|
|
if (ret <= 0 || (ret & active_flags) == active_flags) {
|
|
|
|
dev_pe = dev_pe->parent;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Frozen parent PE */
|
|
|
|
*pe = dev_pe;
|
|
|
|
if (!(dev_pe->state & EEH_PE_ISOLATED))
|
|
|
|
phb->freeze_pe(phb, dev_pe->addr);
|
|
|
|
|
|
|
|
/* Next one */
|
|
|
|
dev_pe = dev_pe->parent;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-20 13:21:13 +08:00
|
|
|
/**
|
2015-02-16 11:45:39 +08:00
|
|
|
* pnv_eeh_next_error - Retrieve next EEH error to handle
|
2013-06-20 13:21:13 +08:00
|
|
|
* @pe: Affected PE
|
|
|
|
*
|
2015-02-16 11:45:46 +08:00
|
|
|
* The function is expected to be called by EEH core while it gets
|
|
|
|
* special EEH event (without binding PE). The function calls to
|
|
|
|
* OPAL APIs for next error to handle. The informational error is
|
|
|
|
* handled internally by platform. However, the dead IOC, dead PHB,
|
|
|
|
* fenced PHB and frozen PE should be handled by EEH core eventually.
|
2013-06-20 13:21:13 +08:00
|
|
|
*/
|
2015-02-16 11:45:39 +08:00
|
|
|
static int pnv_eeh_next_error(struct eeh_pe **pe)
|
2013-06-20 13:21:13 +08:00
|
|
|
{
|
|
|
|
struct pci_controller *hose;
|
2015-02-16 11:45:46 +08:00
|
|
|
struct pnv_phb *phb;
|
|
|
|
struct eeh_pe *phb_pe, *parent_pe;
|
|
|
|
__be64 frozen_pe_no;
|
|
|
|
__be16 err_type, severity;
|
|
|
|
int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
|
|
|
|
long rc;
|
|
|
|
int state, ret = EEH_NEXT_ERR_NONE;
|
|
|
|
|
|
|
|
/*
|
2015-05-15 12:06:40 +08:00
|
|
|
* While running here, it's safe to purge the event queue. The
|
|
|
|
* event should still be masked.
|
2015-02-16 11:45:46 +08:00
|
|
|
*/
|
|
|
|
eeh_remove_event(NULL, false);
|
2013-06-20 13:21:13 +08:00
|
|
|
|
|
|
|
list_for_each_entry(hose, &hose_list, list_node) {
|
2015-02-16 11:45:46 +08:00
|
|
|
/*
|
|
|
|
* If the subordinate PCI buses of the PHB has been
|
|
|
|
* removed or is exactly under error recovery, we
|
|
|
|
* needn't take care of it any more.
|
|
|
|
*/
|
2013-06-20 13:21:13 +08:00
|
|
|
phb = hose->private_data;
|
2015-02-16 11:45:46 +08:00
|
|
|
phb_pe = eeh_phb_pe_get(hose);
|
|
|
|
if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
rc = opal_pci_next_error(phb->opal_id,
|
|
|
|
&frozen_pe_no, &err_type, &severity);
|
|
|
|
if (rc != OPAL_SUCCESS) {
|
|
|
|
pr_devel("%s: Invalid return value on "
|
|
|
|
"PHB#%x (0x%lx) from opal_pci_next_error",
|
|
|
|
__func__, hose->global_number, rc);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the PHB doesn't have error, stop processing */
|
|
|
|
if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
|
|
|
|
be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
|
|
|
|
pr_devel("%s: No error found on PHB#%x\n",
|
|
|
|
__func__, hose->global_number);
|
|
|
|
continue;
|
|
|
|
}
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-02-16 11:45:46 +08:00
|
|
|
/*
|
|
|
|
* Processing the error. We're expecting the error with
|
|
|
|
* highest priority reported upon multiple errors on the
|
|
|
|
* specific PHB.
|
|
|
|
*/
|
|
|
|
pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
|
|
|
|
__func__, be16_to_cpu(err_type),
|
|
|
|
be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
|
|
|
|
hose->global_number);
|
|
|
|
switch (be16_to_cpu(err_type)) {
|
|
|
|
case OPAL_EEH_IOC_ERROR:
|
|
|
|
if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
|
|
|
|
pr_err("EEH: dead IOC detected\n");
|
|
|
|
ret = EEH_NEXT_ERR_DEAD_IOC;
|
|
|
|
} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
|
|
|
|
pr_info("EEH: IOC informative error "
|
|
|
|
"detected\n");
|
|
|
|
pnv_eeh_get_and_dump_hub_diag(hose);
|
|
|
|
ret = EEH_NEXT_ERR_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
case OPAL_EEH_PHB_ERROR:
|
|
|
|
if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
|
|
|
|
*pe = phb_pe;
|
|
|
|
pr_err("EEH: dead PHB#%x detected, "
|
|
|
|
"location: %s\n",
|
|
|
|
hose->global_number,
|
|
|
|
eeh_pe_loc_get(phb_pe));
|
|
|
|
ret = EEH_NEXT_ERR_DEAD_PHB;
|
|
|
|
} else if (be16_to_cpu(severity) ==
|
|
|
|
OPAL_EEH_SEV_PHB_FENCED) {
|
|
|
|
*pe = phb_pe;
|
|
|
|
pr_err("EEH: Fenced PHB#%x detected, "
|
|
|
|
"location: %s\n",
|
|
|
|
hose->global_number,
|
|
|
|
eeh_pe_loc_get(phb_pe));
|
|
|
|
ret = EEH_NEXT_ERR_FENCED_PHB;
|
|
|
|
} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
|
|
|
|
pr_info("EEH: PHB#%x informative error "
|
|
|
|
"detected, location: %s\n",
|
|
|
|
hose->global_number,
|
|
|
|
eeh_pe_loc_get(phb_pe));
|
|
|
|
pnv_eeh_get_phb_diag(phb_pe);
|
|
|
|
pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
|
|
|
|
ret = EEH_NEXT_ERR_NONE;
|
|
|
|
}
|
2013-06-20 13:21:13 +08:00
|
|
|
|
2015-02-16 11:45:46 +08:00
|
|
|
break;
|
|
|
|
case OPAL_EEH_PE_ERROR:
|
|
|
|
/*
|
|
|
|
* If we can't find the corresponding PE, we
|
|
|
|
* just try to unfreeze.
|
|
|
|
*/
|
|
|
|
if (pnv_eeh_get_pe(hose,
|
|
|
|
be64_to_cpu(frozen_pe_no), pe)) {
|
|
|
|
pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
|
2015-05-12 15:05:22 +08:00
|
|
|
hose->global_number, be64_to_cpu(frozen_pe_no));
|
2015-02-16 11:45:46 +08:00
|
|
|
pr_info("EEH: PHB location: %s\n",
|
|
|
|
eeh_pe_loc_get(phb_pe));
|
2015-05-12 15:05:32 +08:00
|
|
|
|
|
|
|
/* Dump PHB diag-data */
|
|
|
|
rc = opal_pci_get_phb_diag_data2(phb->opal_id,
|
2017-06-14 12:19:59 +08:00
|
|
|
phb->diag_data, phb->diag_data_size);
|
2015-05-12 15:05:32 +08:00
|
|
|
if (rc == OPAL_SUCCESS)
|
|
|
|
pnv_pci_dump_phb_diag_data(hose,
|
2017-06-14 12:19:59 +08:00
|
|
|
phb->diag_data);
|
2015-05-12 15:05:32 +08:00
|
|
|
|
|
|
|
/* Try best to clear it */
|
2015-02-16 11:45:46 +08:00
|
|
|
opal_pci_eeh_freeze_clear(phb->opal_id,
|
2016-08-02 12:10:29 +08:00
|
|
|
be64_to_cpu(frozen_pe_no),
|
2015-02-16 11:45:46 +08:00
|
|
|
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
|
|
|
|
ret = EEH_NEXT_ERR_NONE;
|
|
|
|
} else if ((*pe)->state & EEH_PE_ISOLATED ||
|
|
|
|
eeh_pe_passed(*pe)) {
|
|
|
|
ret = EEH_NEXT_ERR_NONE;
|
|
|
|
} else {
|
|
|
|
pr_err("EEH: Frozen PE#%x "
|
|
|
|
"on PHB#%x detected\n",
|
|
|
|
(*pe)->addr,
|
|
|
|
(*pe)->phb->global_number);
|
|
|
|
pr_err("EEH: PE location: %s, "
|
|
|
|
"PHB location: %s\n",
|
|
|
|
eeh_pe_loc_get(*pe),
|
|
|
|
eeh_pe_loc_get(phb_pe));
|
|
|
|
ret = EEH_NEXT_ERR_FROZEN_PE;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_warn("%s: Unexpected error type %d\n",
|
|
|
|
__func__, be16_to_cpu(err_type));
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* EEH core will try recover from fenced PHB or
|
|
|
|
* frozen PE. In the time for frozen PE, EEH core
|
|
|
|
* enable IO path for that before collecting logs,
|
|
|
|
* but it ruins the site. So we have to dump the
|
|
|
|
* log in advance here.
|
|
|
|
*/
|
|
|
|
if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
|
|
|
|
ret == EEH_NEXT_ERR_FENCED_PHB) &&
|
|
|
|
!((*pe)->state & EEH_PE_ISOLATED)) {
|
|
|
|
eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
|
|
|
|
pnv_eeh_get_phb_diag(*pe);
|
|
|
|
|
|
|
|
if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
|
|
|
|
pnv_pci_dump_phb_diag_data((*pe)->phb,
|
|
|
|
(*pe)->data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We probably have the frozen parent PE out there and
|
|
|
|
* we need have to handle frozen parent PE firstly.
|
|
|
|
*/
|
|
|
|
if (ret == EEH_NEXT_ERR_FROZEN_PE) {
|
|
|
|
parent_pe = (*pe)->parent;
|
|
|
|
while (parent_pe) {
|
|
|
|
/* Hit the ceiling ? */
|
|
|
|
if (parent_pe->type & EEH_PE_PHB)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Frozen parent PE ? */
|
|
|
|
state = eeh_ops->get_state(parent_pe, NULL);
|
|
|
|
if (state > 0 &&
|
|
|
|
(state & active_flags) != active_flags)
|
|
|
|
*pe = parent_pe;
|
|
|
|
|
|
|
|
/* Next parent level */
|
|
|
|
parent_pe = parent_pe->parent;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We possibly migrate to another PE */
|
|
|
|
eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If we have no errors on the specific PHB or only
|
|
|
|
* informative error there, we continue poking it.
|
|
|
|
* Otherwise, we need actions to be taken by upper
|
|
|
|
* layer.
|
|
|
|
*/
|
|
|
|
if (ret > EEH_NEXT_ERR_INF)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-05-15 12:06:40 +08:00
|
|
|
/* Unmask the event */
|
2015-07-30 14:53:54 +08:00
|
|
|
if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
|
2015-05-15 12:06:40 +08:00
|
|
|
enable_irq(eeh_event_irq);
|
|
|
|
|
2015-02-16 11:45:46 +08:00
|
|
|
return ret;
|
2013-06-20 13:21:13 +08:00
|
|
|
}
|
|
|
|
|
2015-03-17 13:15:07 +08:00
|
|
|
static int pnv_eeh_restore_config(struct pci_dn *pdn)
|
2014-01-03 17:47:13 +08:00
|
|
|
{
|
2015-03-17 13:15:07 +08:00
|
|
|
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
2014-01-03 17:47:13 +08:00
|
|
|
struct pnv_phb *phb;
|
2018-01-06 00:45:46 +08:00
|
|
|
s64 ret = 0;
|
2017-08-29 15:34:02 +08:00
|
|
|
int config_addr = (pdn->busno << 8) | (pdn->devfn);
|
2014-01-03 17:47:13 +08:00
|
|
|
|
|
|
|
if (!edev)
|
|
|
|
return -EEXIST;
|
|
|
|
|
powerpc/powernv: Support PCI config restore for VFs
After PE reset, OPAL API opal_pci_reinit() is called on all devices
contained in the PE to reinitialize them. While skiboot is not aware of
VFs, we have to implement the function in kernel to reinitialize VFs after
reset on PE for VFs.
In this patch, two functions pnv_pci_fixup_vf_mps() and
pnv_eeh_restore_vf_config() both manipulate the MPS of the VF, since for a
VF it has three cases.
1. Normal creation for a VF
In this case, pnv_pci_fixup_vf_mps() is called to make the MPS a proper
value compared with its parent.
2. EEH recovery without VF removed
In this case, MPS is stored in pci_dn and pnv_eeh_restore_vf_config() is
called to restore it and reinitialize other part.
3. EEH recovery with VF removed
In this case, VF will be removed then re-created. Both functions are
called. First pnv_pci_fixup_vf_mps() is called to store the proper MPS
to pci_dn and then pnv_eeh_restore_vf_config() is called to do proper
thing.
This introduces two functions: pnv_pci_fixup_vf_mps() to fixup the VF's
MPS to make sure it is equal to parent's and store this value in pci_dn
for future use. pnv_eeh_restore_vf_config() to re-initialize on VF by
restoring MPS, disabling completion timeout, enabling SERR, etc.
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-04 07:53:10 +08:00
|
|
|
/*
|
|
|
|
* We have to restore the PCI config space after reset since the
|
|
|
|
* firmware can't see SRIOV VFs.
|
|
|
|
*
|
|
|
|
* FIXME: The MPS, error routing rules, timeout setting are worthy
|
|
|
|
* to be exported by firmware in extendible way.
|
|
|
|
*/
|
|
|
|
if (edev->physfn) {
|
2018-01-06 00:45:46 +08:00
|
|
|
ret = eeh_restore_vf_config(pdn);
|
powerpc/powernv: Support PCI config restore for VFs
After PE reset, OPAL API opal_pci_reinit() is called on all devices
contained in the PE to reinitialize them. While skiboot is not aware of
VFs, we have to implement the function in kernel to reinitialize VFs after
reset on PE for VFs.
In this patch, two functions pnv_pci_fixup_vf_mps() and
pnv_eeh_restore_vf_config() both manipulate the MPS of the VF, since for a
VF it has three cases.
1. Normal creation for a VF
In this case, pnv_pci_fixup_vf_mps() is called to make the MPS a proper
value compared with its parent.
2. EEH recovery without VF removed
In this case, MPS is stored in pci_dn and pnv_eeh_restore_vf_config() is
called to restore it and reinitialize other part.
3. EEH recovery with VF removed
In this case, VF will be removed then re-created. Both functions are
called. First pnv_pci_fixup_vf_mps() is called to store the proper MPS
to pci_dn and then pnv_eeh_restore_vf_config() is called to do proper
thing.
This introduces two functions: pnv_pci_fixup_vf_mps() to fixup the VF's
MPS to make sure it is equal to parent's and store this value in pci_dn
for future use. pnv_eeh_restore_vf_config() to re-initialize on VF by
restoring MPS, disabling completion timeout, enabling SERR, etc.
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-04 07:53:10 +08:00
|
|
|
} else {
|
2017-08-29 15:34:01 +08:00
|
|
|
phb = pdn->phb->private_data;
|
powerpc/powernv: Support PCI config restore for VFs
After PE reset, OPAL API opal_pci_reinit() is called on all devices
contained in the PE to reinitialize them. While skiboot is not aware of
VFs, we have to implement the function in kernel to reinitialize VFs after
reset on PE for VFs.
In this patch, two functions pnv_pci_fixup_vf_mps() and
pnv_eeh_restore_vf_config() both manipulate the MPS of the VF, since for a
VF it has three cases.
1. Normal creation for a VF
In this case, pnv_pci_fixup_vf_mps() is called to make the MPS a proper
value compared with its parent.
2. EEH recovery without VF removed
In this case, MPS is stored in pci_dn and pnv_eeh_restore_vf_config() is
called to restore it and reinitialize other part.
3. EEH recovery with VF removed
In this case, VF will be removed then re-created. Both functions are
called. First pnv_pci_fixup_vf_mps() is called to store the proper MPS
to pci_dn and then pnv_eeh_restore_vf_config() is called to do proper
thing.
This introduces two functions: pnv_pci_fixup_vf_mps() to fixup the VF's
MPS to make sure it is equal to parent's and store this value in pci_dn
for future use. pnv_eeh_restore_vf_config() to re-initialize on VF by
restoring MPS, disabling completion timeout, enabling SERR, etc.
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-04 07:53:10 +08:00
|
|
|
ret = opal_pci_reinit(phb->opal_id,
|
2017-08-29 15:34:02 +08:00
|
|
|
OPAL_REINIT_PCI_DEV, config_addr);
|
powerpc/powernv: Support PCI config restore for VFs
After PE reset, OPAL API opal_pci_reinit() is called on all devices
contained in the PE to reinitialize them. While skiboot is not aware of
VFs, we have to implement the function in kernel to reinitialize VFs after
reset on PE for VFs.
In this patch, two functions pnv_pci_fixup_vf_mps() and
pnv_eeh_restore_vf_config() both manipulate the MPS of the VF, since for a
VF it has three cases.
1. Normal creation for a VF
In this case, pnv_pci_fixup_vf_mps() is called to make the MPS a proper
value compared with its parent.
2. EEH recovery without VF removed
In this case, MPS is stored in pci_dn and pnv_eeh_restore_vf_config() is
called to restore it and reinitialize other part.
3. EEH recovery with VF removed
In this case, VF will be removed then re-created. Both functions are
called. First pnv_pci_fixup_vf_mps() is called to store the proper MPS
to pci_dn and then pnv_eeh_restore_vf_config() is called to do proper
thing.
This introduces two functions: pnv_pci_fixup_vf_mps() to fixup the VF's
MPS to make sure it is equal to parent's and store this value in pci_dn
for future use. pnv_eeh_restore_vf_config() to re-initialize on VF by
restoring MPS, disabling completion timeout, enabling SERR, etc.
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-04 07:53:10 +08:00
|
|
|
}
|
|
|
|
|
2014-01-03 17:47:13 +08:00
|
|
|
if (ret) {
|
|
|
|
pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
|
2017-08-29 15:34:02 +08:00
|
|
|
__func__, config_addr, ret);
|
2014-01-03 17:47:13 +08:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2018-01-06 00:45:46 +08:00
|
|
|
return ret;
|
2014-01-03 17:47:13 +08:00
|
|
|
}
|
|
|
|
|
2015-02-16 11:45:39 +08:00
|
|
|
static struct eeh_ops pnv_eeh_ops = {
|
2013-06-20 13:21:13 +08:00
|
|
|
.name = "powernv",
|
2015-02-16 11:45:39 +08:00
|
|
|
.init = pnv_eeh_init,
|
2015-03-17 13:15:06 +08:00
|
|
|
.probe = pnv_eeh_probe,
|
2015-02-16 11:45:39 +08:00
|
|
|
.set_option = pnv_eeh_set_option,
|
|
|
|
.get_pe_addr = pnv_eeh_get_pe_addr,
|
|
|
|
.get_state = pnv_eeh_get_state,
|
|
|
|
.reset = pnv_eeh_reset,
|
|
|
|
.wait_state = pnv_eeh_wait_state,
|
|
|
|
.get_log = pnv_eeh_get_log,
|
|
|
|
.configure_bridge = pnv_eeh_configure_bridge,
|
|
|
|
.err_inject = pnv_eeh_err_inject,
|
|
|
|
.read_config = pnv_eeh_read_config,
|
|
|
|
.write_config = pnv_eeh_write_config,
|
|
|
|
.next_error = pnv_eeh_next_error,
|
2018-01-06 00:45:49 +08:00
|
|
|
.restore_config = pnv_eeh_restore_config,
|
|
|
|
.notify_resume = NULL
|
2013-06-20 13:21:13 +08:00
|
|
|
};
|
|
|
|
|
powerpc/powernv: Support PCI config restore for VFs
After PE reset, OPAL API opal_pci_reinit() is called on all devices
contained in the PE to reinitialize them. While skiboot is not aware of
VFs, we have to implement the function in kernel to reinitialize VFs after
reset on PE for VFs.
In this patch, two functions pnv_pci_fixup_vf_mps() and
pnv_eeh_restore_vf_config() both manipulate the MPS of the VF, since for a
VF it has three cases.
1. Normal creation for a VF
In this case, pnv_pci_fixup_vf_mps() is called to make the MPS a proper
value compared with its parent.
2. EEH recovery without VF removed
In this case, MPS is stored in pci_dn and pnv_eeh_restore_vf_config() is
called to restore it and reinitialize other part.
3. EEH recovery with VF removed
In this case, VF will be removed then re-created. Both functions are
called. First pnv_pci_fixup_vf_mps() is called to store the proper MPS
to pci_dn and then pnv_eeh_restore_vf_config() is called to do proper
thing.
This introduces two functions: pnv_pci_fixup_vf_mps() to fixup the VF's
MPS to make sure it is equal to parent's and store this value in pci_dn
for future use. pnv_eeh_restore_vf_config() to re-initialize on VF by
restoring MPS, disabling completion timeout, enabling SERR, etc.
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2016-03-04 07:53:10 +08:00
|
|
|
#ifdef CONFIG_PCI_IOV
|
|
|
|
static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_dn *pdn = pci_get_pdn(pdev);
|
|
|
|
int parent_mps;
|
|
|
|
|
|
|
|
if (!pdev->is_virtfn)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Synchronize MPS for VF and PF */
|
|
|
|
parent_mps = pcie_get_mps(pdev->physfn);
|
|
|
|
if ((128 << pdev->pcie_mpss) >= parent_mps)
|
|
|
|
pcie_set_mps(pdev, parent_mps);
|
|
|
|
pdn->mps = pcie_get_mps(pdev);
|
|
|
|
}
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
|
|
|
|
#endif /* CONFIG_PCI_IOV */
|
|
|
|
|
2013-06-20 13:21:13 +08:00
|
|
|
/**
|
|
|
|
* eeh_powernv_init - Register platform dependent EEH operations
|
|
|
|
*
|
|
|
|
* EEH initialization on powernv platform. This function should be
|
|
|
|
* called before any EEH related functions.
|
|
|
|
*/
|
|
|
|
static int __init eeh_powernv_init(void)
|
|
|
|
{
|
|
|
|
int ret = -EINVAL;
|
|
|
|
|
2015-02-16 11:45:39 +08:00
|
|
|
ret = eeh_ops_register(&pnv_eeh_ops);
|
2013-06-20 13:21:13 +08:00
|
|
|
if (!ret)
|
|
|
|
pr_info("EEH: PowerNV platform initialized\n");
|
|
|
|
else
|
|
|
|
pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
2014-07-15 20:22:24 +08:00
|
|
|
machine_early_initcall(powernv, eeh_powernv_init);
|