2008-04-29 07:24:33 +08:00
|
|
|
/*
|
|
|
|
* cx18 System Control Block initialization
|
|
|
|
*
|
|
|
|
* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
|
2008-11-22 12:37:34 +08:00
|
|
|
* Copyright (C) 2008 Andy Walls <awalls@radix.net>
|
2008-04-29 07:24:33 +08:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
|
|
|
|
* 02111-1307 USA
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "cx18-driver.h"
|
2008-08-31 03:03:44 +08:00
|
|
|
#include "cx18-io.h"
|
2008-04-29 07:24:33 +08:00
|
|
|
#include "cx18-scb.h"
|
|
|
|
|
|
|
|
void cx18_init_scb(struct cx18 *cx)
|
|
|
|
{
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_setup_page(cx, SCB_OFFSET);
|
|
|
|
cx18_memset_io(cx, cx->scb, 0, 0x10000);
|
2008-04-29 07:24:33 +08:00
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, IRQ_APU_TO_CPU, &cx->scb->apu2cpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_CPU_TO_APU_ACK, &cx->scb->cpu2apu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_CPU, &cx->scb->hpu2cpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_CPU_TO_HPU_ACK, &cx->scb->cpu2hpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_CPU, &cx->scb->ppu2cpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_CPU_TO_PPU_ACK, &cx->scb->cpu2ppu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_CPU, &cx->scb->epu2cpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_CPU_TO_EPU_ACK, &cx->scb->cpu2epu_irq_ack);
|
2008-04-29 07:24:33 +08:00
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, IRQ_CPU_TO_APU, &cx->scb->cpu2apu_irq);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_CPU_ACK, &cx->scb->apu2cpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_APU, &cx->scb->hpu2apu_irq);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_HPU_ACK, &cx->scb->apu2hpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_APU, &cx->scb->ppu2apu_irq);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_PPU_ACK, &cx->scb->apu2ppu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_APU, &cx->scb->epu2apu_irq);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_EPU_ACK, &cx->scb->apu2epu_irq_ack);
|
2008-04-29 07:24:33 +08:00
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, IRQ_CPU_TO_HPU, &cx->scb->cpu2hpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_CPU_ACK, &cx->scb->hpu2cpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_HPU, &cx->scb->apu2hpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_APU_ACK, &cx->scb->hpu2apu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_HPU, &cx->scb->ppu2hpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_PPU_ACK, &cx->scb->hpu2ppu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_HPU, &cx->scb->epu2hpu_irq);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_EPU_ACK, &cx->scb->hpu2epu_irq_ack);
|
2008-04-29 07:24:33 +08:00
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, IRQ_CPU_TO_PPU, &cx->scb->cpu2ppu_irq);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_CPU_ACK, &cx->scb->ppu2cpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_PPU, &cx->scb->apu2ppu_irq);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_APU_ACK, &cx->scb->ppu2apu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_PPU, &cx->scb->hpu2ppu_irq);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_HPU_ACK, &cx->scb->ppu2hpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_PPU, &cx->scb->epu2ppu_irq);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_EPU_ACK, &cx->scb->ppu2epu_irq_ack);
|
2008-04-29 07:24:33 +08:00
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, IRQ_CPU_TO_EPU, &cx->scb->cpu2epu_irq);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_CPU_ACK, &cx->scb->epu2cpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_APU_TO_EPU, &cx->scb->apu2epu_irq);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_APU_ACK, &cx->scb->epu2apu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_HPU_TO_EPU, &cx->scb->hpu2epu_irq);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_HPU_ACK, &cx->scb->epu2hpu_irq_ack);
|
|
|
|
cx18_writel(cx, IRQ_PPU_TO_EPU, &cx->scb->ppu2epu_irq);
|
|
|
|
cx18_writel(cx, IRQ_EPU_TO_PPU_ACK, &cx->scb->epu2ppu_irq_ack);
|
2008-04-29 07:24:33 +08:00
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2cpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->apu2cpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2cpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->hpu2cpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2cpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->ppu2cpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2cpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->epu2cpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2apu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->cpu2apu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2apu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->hpu2apu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2apu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->ppu2apu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2apu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->epu2apu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2hpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->cpu2hpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2hpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->apu2hpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2hpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->ppu2hpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2hpu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->epu2hpu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2ppu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->cpu2ppu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2ppu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->apu2ppu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2ppu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->hpu2ppu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2ppu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->epu2ppu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2epu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->cpu2epu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2epu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->apu2epu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2epu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->hpu2epu_mb_offset);
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2epu_mb),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->ppu2epu_mb_offset);
|
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu_state),
|
2008-04-29 07:24:33 +08:00
|
|
|
&cx->scb->ipc_offset);
|
|
|
|
|
2008-08-31 03:03:44 +08:00
|
|
|
cx18_writel(cx, 1, &cx->scb->epu_state);
|
2008-04-29 07:24:33 +08:00
|
|
|
}
|