2012-09-21 16:07:49 +08:00
|
|
|
/*
|
|
|
|
|
* Copyright 2005-2009 Freescale Semiconductor, Inc.
|
|
|
|
|
*
|
|
|
|
|
* The code contained herein is licensed under the GNU Lesser General
|
|
|
|
|
* Public License. You may obtain a copy of the GNU Lesser General
|
|
|
|
|
* Public License Version 2.1 or later at the following locations:
|
|
|
|
|
*
|
|
|
|
|
* http://www.opensource.org/licenses/lgpl-license.html
|
|
|
|
|
* http://www.gnu.org/copyleft/lgpl.html
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef __DRM_IPU_H__
|
|
|
|
|
#define __DRM_IPU_H__
|
|
|
|
|
|
|
|
|
|
#include <linux/types.h>
|
|
|
|
|
#include <linux/videodev2.h>
|
|
|
|
|
#include <linux/bitmap.h>
|
|
|
|
|
#include <linux/fb.h>
|
2016-05-12 21:00:44 +08:00
|
|
|
#include <linux/of.h>
|
2014-08-20 01:52:40 +08:00
|
|
|
#include <media/v4l2-mediabus.h>
|
2014-12-19 10:00:20 +08:00
|
|
|
#include <video/videomode.h>
|
2012-09-21 16:07:49 +08:00
|
|
|
|
|
|
|
|
struct ipu_soc;
|
|
|
|
|
|
|
|
|
|
enum ipuv3_type {
|
|
|
|
|
IPUV3EX,
|
|
|
|
|
IPUV3M,
|
|
|
|
|
IPUV3H,
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-25 19:43:41 +08:00
|
|
|
#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
|
|
|
|
|
|
2012-09-21 16:07:49 +08:00
|
|
|
/*
|
|
|
|
|
* Bitfield of Display Interface signal polarities.
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_di_signal_cfg {
|
|
|
|
|
unsigned data_pol:1; /* true = inverted */
|
|
|
|
|
unsigned clk_pol:1; /* true = rising edge */
|
|
|
|
|
unsigned enable_pol:1;
|
|
|
|
|
|
2014-12-19 10:00:25 +08:00
|
|
|
struct videomode mode;
|
|
|
|
|
|
2015-02-03 00:25:59 +08:00
|
|
|
u32 bus_format;
|
2012-09-21 16:07:49 +08:00
|
|
|
u32 v_to_h_sync;
|
2014-12-19 10:00:25 +08:00
|
|
|
|
2012-09-21 16:07:49 +08:00
|
|
|
#define IPU_DI_CLKMODE_SYNC (1 << 0)
|
|
|
|
|
#define IPU_DI_CLKMODE_EXT (1 << 1)
|
|
|
|
|
unsigned long clkflags;
|
2013-04-09 00:04:35 +08:00
|
|
|
|
|
|
|
|
u8 hsync_pin;
|
|
|
|
|
u8 vsync_pin;
|
2012-09-21 16:07:49 +08:00
|
|
|
};
|
|
|
|
|
|
2014-08-20 01:52:40 +08:00
|
|
|
/*
|
|
|
|
|
* Enumeration of CSI destinations
|
|
|
|
|
*/
|
|
|
|
|
enum ipu_csi_dest {
|
|
|
|
|
IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
|
|
|
|
|
IPU_CSI_DEST_IC, /* to Image Converter */
|
|
|
|
|
IPU_CSI_DEST_VDIC, /* to VDIC */
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-11 19:04:50 +08:00
|
|
|
/*
|
|
|
|
|
* Enumeration of IPU rotation modes
|
|
|
|
|
*/
|
2016-09-18 03:33:57 +08:00
|
|
|
#define IPU_ROT_BIT_VFLIP (1 << 0)
|
|
|
|
|
#define IPU_ROT_BIT_HFLIP (1 << 1)
|
|
|
|
|
#define IPU_ROT_BIT_90 (1 << 2)
|
|
|
|
|
|
2014-08-11 19:04:50 +08:00
|
|
|
enum ipu_rotate_mode {
|
|
|
|
|
IPU_ROTATE_NONE = 0,
|
2016-09-18 03:33:57 +08:00
|
|
|
IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
|
|
|
|
|
IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
|
|
|
|
|
IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
|
|
|
|
|
IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
|
|
|
|
|
IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
|
|
|
|
|
IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
|
|
|
|
|
IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
|
|
|
|
|
IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
|
2014-08-11 19:04:50 +08:00
|
|
|
};
|
|
|
|
|
|
2016-09-18 03:33:57 +08:00
|
|
|
/* 90-degree rotations require the IRT unit */
|
|
|
|
|
#define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
|
|
|
|
|
|
2012-09-21 16:07:49 +08:00
|
|
|
enum ipu_color_space {
|
|
|
|
|
IPUV3_COLORSPACE_RGB,
|
|
|
|
|
IPUV3_COLORSPACE_YUV,
|
|
|
|
|
IPUV3_COLORSPACE_UNKNOWN,
|
|
|
|
|
};
|
|
|
|
|
|
2016-08-18 08:50:16 +08:00
|
|
|
/*
|
|
|
|
|
* Enumeration of VDI MOTION select
|
|
|
|
|
*/
|
|
|
|
|
enum ipu_motion_sel {
|
|
|
|
|
MOTION_NONE = 0,
|
|
|
|
|
LOW_MOTION,
|
|
|
|
|
MED_MOTION,
|
|
|
|
|
HIGH_MOTION,
|
|
|
|
|
};
|
|
|
|
|
|
2012-09-21 16:07:49 +08:00
|
|
|
struct ipuv3_channel;
|
|
|
|
|
|
|
|
|
|
enum ipu_channel_irq {
|
|
|
|
|
IPU_IRQ_EOF = 0,
|
|
|
|
|
IPU_IRQ_NFACK = 64,
|
|
|
|
|
IPU_IRQ_NFB4EOF = 128,
|
|
|
|
|
IPU_IRQ_EOS = 192,
|
|
|
|
|
};
|
|
|
|
|
|
2014-06-26 09:05:39 +08:00
|
|
|
/*
|
|
|
|
|
* Enumeration of IDMAC channels
|
|
|
|
|
*/
|
|
|
|
|
#define IPUV3_CHANNEL_CSI0 0
|
|
|
|
|
#define IPUV3_CHANNEL_CSI1 1
|
|
|
|
|
#define IPUV3_CHANNEL_CSI2 2
|
|
|
|
|
#define IPUV3_CHANNEL_CSI3 3
|
|
|
|
|
#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
|
2016-08-18 08:50:17 +08:00
|
|
|
/*
|
|
|
|
|
* NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
|
|
|
|
|
* but the direct CSI->VDI linking is handled the same way as IDMAC
|
|
|
|
|
* channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
|
|
|
|
|
* these channel names are used to support the direct CSI->VDI link.
|
|
|
|
|
*/
|
|
|
|
|
#define IPUV3_CHANNEL_CSI_DIRECT 6
|
|
|
|
|
#define IPUV3_CHANNEL_CSI_VDI_PREV 7
|
2016-07-20 09:11:05 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_VDI_PREV 8
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_VDI_CUR 9
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_VDI_NEXT 10
|
2014-06-26 09:05:39 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_IC_PP 11
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
|
2014-07-30 20:10:51 +08:00
|
|
|
#define IPUV3_CHANNEL_VDI_MEM_RECENT 13
|
2014-06-26 09:05:39 +08:00
|
|
|
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
|
|
|
|
|
#define IPUV3_CHANNEL_G_MEM_IC_PP 15
|
2014-07-30 20:10:51 +08:00
|
|
|
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
|
|
|
|
|
#define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA 18
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
|
2014-06-26 09:05:39 +08:00
|
|
|
#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
|
|
|
|
|
#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
|
|
|
|
|
#define IPUV3_CHANNEL_IC_PP_MEM 22
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_BG_SYNC 23
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
|
2014-07-30 20:10:51 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB 25
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB 26
|
2014-06-26 09:05:39 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_FG_SYNC 27
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_DC_SYNC 28
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
|
2014-07-30 20:10:51 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA 33
|
|
|
|
|
#define IPUV3_CHANNEL_DC_MEM_READ 40
|
2014-06-26 09:05:39 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
|
2014-07-30 20:10:51 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_DC_COMMAND 42
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_DC_COMMAND2 43
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK 44
|
2014-06-26 09:05:39 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_ROT_ENC 45
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_ROT_VF 46
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_ROT_PP 47
|
|
|
|
|
#define IPUV3_CHANNEL_ROT_ENC_MEM 48
|
|
|
|
|
#define IPUV3_CHANNEL_ROT_VF_MEM 49
|
|
|
|
|
#define IPUV3_CHANNEL_ROT_PP_MEM 50
|
|
|
|
|
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
|
2014-07-30 20:10:51 +08:00
|
|
|
#define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA 52
|
2016-08-18 08:50:17 +08:00
|
|
|
#define IPUV3_NUM_CHANNELS 64
|
2014-06-26 09:05:39 +08:00
|
|
|
|
2015-01-09 18:03:13 +08:00
|
|
|
static inline int ipu_channel_alpha_channel(int ch_num)
|
|
|
|
|
{
|
|
|
|
|
switch (ch_num) {
|
|
|
|
|
case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
|
|
|
|
|
return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
|
|
|
|
|
case IPUV3_CHANNEL_G_MEM_IC_PP:
|
|
|
|
|
return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
|
|
|
|
|
case IPUV3_CHANNEL_MEM_FG_SYNC:
|
|
|
|
|
return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
|
|
|
|
|
case IPUV3_CHANNEL_MEM_FG_ASYNC:
|
|
|
|
|
return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
|
|
|
|
|
case IPUV3_CHANNEL_MEM_BG_SYNC:
|
|
|
|
|
return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
|
|
|
|
|
case IPUV3_CHANNEL_MEM_BG_ASYNC:
|
|
|
|
|
return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
|
|
|
|
|
case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
|
|
|
|
|
return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2014-04-15 05:53:16 +08:00
|
|
|
int ipu_map_irq(struct ipu_soc *ipu, int irq);
|
2012-09-21 16:07:49 +08:00
|
|
|
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
|
|
|
|
|
enum ipu_channel_irq irq);
|
|
|
|
|
|
|
|
|
|
#define IPU_IRQ_DP_SF_START (448 + 2)
|
|
|
|
|
#define IPU_IRQ_DP_SF_END (448 + 3)
|
|
|
|
|
#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
|
|
|
|
|
#define IPU_IRQ_DC_FC_0 (448 + 8)
|
|
|
|
|
#define IPU_IRQ_DC_FC_1 (448 + 9)
|
|
|
|
|
#define IPU_IRQ_DC_FC_2 (448 + 10)
|
|
|
|
|
#define IPU_IRQ_DC_FC_3 (448 + 11)
|
|
|
|
|
#define IPU_IRQ_DC_FC_4 (448 + 12)
|
|
|
|
|
#define IPU_IRQ_DC_FC_6 (448 + 13)
|
|
|
|
|
#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
|
|
|
|
|
#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
|
|
|
|
|
|
2014-06-26 09:05:30 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Common functions
|
|
|
|
|
*/
|
2016-07-20 09:11:02 +08:00
|
|
|
int ipu_get_num(struct ipu_soc *ipu);
|
2014-06-26 09:05:30 +08:00
|
|
|
void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
|
|
|
|
|
void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
|
2014-06-26 09:05:55 +08:00
|
|
|
void ipu_dump(struct ipu_soc *ipu);
|
2014-06-26 09:05:30 +08:00
|
|
|
|
2012-09-21 16:07:49 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Image DMA Controller (idmac) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
|
|
|
|
|
void ipu_idmac_put(struct ipuv3_channel *);
|
|
|
|
|
|
|
|
|
|
int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
|
|
|
|
|
int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
|
2014-06-26 09:05:44 +08:00
|
|
|
void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
|
2014-06-26 09:05:45 +08:00
|
|
|
int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
|
2013-10-10 22:18:41 +08:00
|
|
|
int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
|
2012-09-21 16:07:49 +08:00
|
|
|
|
|
|
|
|
void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
|
|
|
|
|
bool doublebuffer);
|
2012-05-16 23:28:29 +08:00
|
|
|
int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
|
2014-06-26 09:05:40 +08:00
|
|
|
bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
|
2012-09-21 16:07:49 +08:00
|
|
|
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
|
2014-06-26 09:05:41 +08:00
|
|
|
void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
|
2016-08-18 08:50:17 +08:00
|
|
|
int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
|
|
|
|
|
int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
|
|
|
|
|
int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
|
|
|
|
|
int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
|
2012-09-21 16:07:49 +08:00
|
|
|
|
2014-06-26 09:05:47 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Channel Parameter Memory (cpmem) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_rgb {
|
|
|
|
|
struct fb_bitfield red;
|
|
|
|
|
struct fb_bitfield green;
|
|
|
|
|
struct fb_bitfield blue;
|
|
|
|
|
struct fb_bitfield transp;
|
|
|
|
|
int bits_per_pixel;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct ipu_image {
|
|
|
|
|
struct v4l2_pix_format pix;
|
|
|
|
|
struct v4l2_rect rect;
|
2014-06-26 09:05:52 +08:00
|
|
|
dma_addr_t phys0;
|
|
|
|
|
dma_addr_t phys1;
|
2018-10-07 05:45:48 +08:00
|
|
|
/* chroma plane offset overrides */
|
|
|
|
|
u32 u_offset;
|
|
|
|
|
u32 v_offset;
|
2014-06-26 09:05:47 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void ipu_cpmem_zero(struct ipuv3_channel *ch);
|
|
|
|
|
void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
|
2014-09-17 21:44:54 +08:00
|
|
|
void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
|
2014-06-26 09:05:47 +08:00
|
|
|
void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
|
|
|
|
|
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
|
|
|
|
|
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
|
2016-07-20 09:11:00 +08:00
|
|
|
void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
|
2014-06-26 09:05:47 +08:00
|
|
|
void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
|
2014-06-26 09:05:50 +08:00
|
|
|
void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
|
2016-07-20 09:11:01 +08:00
|
|
|
int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
|
2014-06-26 09:05:47 +08:00
|
|
|
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
|
2014-06-26 09:05:49 +08:00
|
|
|
void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
|
2014-06-26 09:05:51 +08:00
|
|
|
void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
|
|
|
|
|
enum ipu_rotate_mode rot);
|
2014-06-26 09:05:47 +08:00
|
|
|
int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
|
|
|
|
|
const struct ipu_rgb *rgb);
|
|
|
|
|
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
|
|
|
|
|
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
|
|
|
|
|
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
|
2016-02-23 17:22:50 +08:00
|
|
|
unsigned int uv_stride,
|
|
|
|
|
unsigned int u_offset,
|
|
|
|
|
unsigned int v_offset);
|
2014-06-26 09:05:47 +08:00
|
|
|
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
|
|
|
|
|
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
|
2014-06-26 09:05:54 +08:00
|
|
|
void ipu_cpmem_dump(struct ipuv3_channel *ch);
|
2014-06-26 09:05:47 +08:00
|
|
|
|
2012-09-21 16:07:49 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Display Controller (dc) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_dc;
|
|
|
|
|
struct ipu_di;
|
|
|
|
|
struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
|
|
|
|
|
void ipu_dc_put(struct ipu_dc *dc);
|
|
|
|
|
int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
|
|
|
|
|
u32 pixel_fmt, u32 width);
|
2014-04-15 05:53:23 +08:00
|
|
|
void ipu_dc_enable(struct ipu_soc *ipu);
|
2012-09-21 16:07:49 +08:00
|
|
|
void ipu_dc_enable_channel(struct ipu_dc *dc);
|
|
|
|
|
void ipu_dc_disable_channel(struct ipu_dc *dc);
|
2014-04-15 05:53:23 +08:00
|
|
|
void ipu_dc_disable(struct ipu_soc *ipu);
|
2012-09-21 16:07:49 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IPU Display Interface (di) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
|
|
|
|
|
void ipu_di_put(struct ipu_di *);
|
|
|
|
|
int ipu_di_disable(struct ipu_di *);
|
|
|
|
|
int ipu_di_enable(struct ipu_di *);
|
|
|
|
|
int ipu_di_get_num(struct ipu_di *);
|
2014-12-19 10:00:20 +08:00
|
|
|
int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
|
2012-09-21 16:07:49 +08:00
|
|
|
int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IPU Display Multi FIFO Controller (dmfc) functions
|
|
|
|
|
*/
|
|
|
|
|
struct dmfc_channel;
|
|
|
|
|
int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
|
|
|
|
|
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
|
2016-03-14 16:10:10 +08:00
|
|
|
void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
|
2012-09-21 16:07:49 +08:00
|
|
|
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
|
|
|
|
|
void ipu_dmfc_put(struct dmfc_channel *dmfc);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IPU Display Processor (dp) functions
|
|
|
|
|
*/
|
|
|
|
|
#define IPU_DP_FLOW_SYNC_BG 0
|
|
|
|
|
#define IPU_DP_FLOW_SYNC_FG 1
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC0_BG 2
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC0_FG 3
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC1_BG 4
|
|
|
|
|
#define IPU_DP_FLOW_ASYNC1_FG 5
|
|
|
|
|
|
|
|
|
|
struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
|
|
|
|
|
void ipu_dp_put(struct ipu_dp *);
|
2014-04-15 05:53:20 +08:00
|
|
|
int ipu_dp_enable(struct ipu_soc *ipu);
|
2012-09-21 16:07:49 +08:00
|
|
|
int ipu_dp_enable_channel(struct ipu_dp *dp);
|
2017-02-25 01:23:55 +08:00
|
|
|
void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
|
2014-04-15 05:53:20 +08:00
|
|
|
void ipu_dp_disable(struct ipu_soc *ipu);
|
2012-09-21 16:07:49 +08:00
|
|
|
int ipu_dp_setup_channel(struct ipu_dp *dp,
|
|
|
|
|
enum ipu_color_space in, enum ipu_color_space out);
|
|
|
|
|
int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
|
|
|
|
|
int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
|
|
|
|
|
bool bg_chan);
|
|
|
|
|
|
2017-03-08 19:13:16 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Prefetch Resolve Gasket (prg) functions
|
|
|
|
|
*/
|
|
|
|
|
int ipu_prg_max_active_channels(void);
|
|
|
|
|
bool ipu_prg_present(struct ipu_soc *ipu);
|
|
|
|
|
bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
|
|
|
|
|
uint64_t modifier);
|
|
|
|
|
int ipu_prg_enable(struct ipu_soc *ipu);
|
|
|
|
|
void ipu_prg_disable(struct ipu_soc *ipu);
|
|
|
|
|
void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
|
|
|
|
|
int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
|
|
|
|
|
unsigned int axi_id, unsigned int width,
|
|
|
|
|
unsigned int height, unsigned int stride,
|
2017-11-11 00:09:59 +08:00
|
|
|
u32 format, uint64_t modifier, unsigned long *eba);
|
2017-03-08 19:13:16 +08:00
|
|
|
|
2012-05-22 23:08:48 +08:00
|
|
|
/*
|
|
|
|
|
* IPU CMOS Sensor Interface (csi) functions
|
|
|
|
|
*/
|
2014-08-20 01:52:40 +08:00
|
|
|
struct ipu_csi;
|
|
|
|
|
int ipu_csi_init_interface(struct ipu_csi *csi,
|
|
|
|
|
struct v4l2_mbus_config *mbus_cfg,
|
|
|
|
|
struct v4l2_mbus_framefmt *mbus_fmt);
|
|
|
|
|
bool ipu_csi_is_interlaced(struct ipu_csi *csi);
|
|
|
|
|
void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
|
|
|
|
|
void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
|
2016-10-05 23:33:45 +08:00
|
|
|
void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
|
2014-08-20 01:52:40 +08:00
|
|
|
void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
|
|
|
|
|
u32 r_value, u32 g_value, u32 b_value,
|
|
|
|
|
u32 pix_clk);
|
|
|
|
|
int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
|
|
|
|
|
struct v4l2_mbus_framefmt *mbus_fmt);
|
|
|
|
|
int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
|
|
|
|
|
u32 max_ratio, u32 id);
|
|
|
|
|
int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
|
|
|
|
|
int ipu_csi_enable(struct ipu_csi *csi);
|
|
|
|
|
int ipu_csi_disable(struct ipu_csi *csi);
|
|
|
|
|
struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
|
|
|
|
|
void ipu_csi_put(struct ipu_csi *csi);
|
|
|
|
|
void ipu_csi_dump(struct ipu_csi *csi);
|
2012-05-22 23:08:48 +08:00
|
|
|
|
2014-08-11 19:04:50 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Image Converter (ic) functions
|
|
|
|
|
*/
|
|
|
|
|
enum ipu_ic_task {
|
|
|
|
|
IC_TASK_ENCODER,
|
|
|
|
|
IC_TASK_VIEWFINDER,
|
|
|
|
|
IC_TASK_POST_PROCESSOR,
|
|
|
|
|
IC_NUM_TASKS,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct ipu_ic;
|
|
|
|
|
int ipu_ic_task_init(struct ipu_ic *ic,
|
|
|
|
|
int in_width, int in_height,
|
|
|
|
|
int out_width, int out_height,
|
|
|
|
|
enum ipu_color_space in_cs,
|
|
|
|
|
enum ipu_color_space out_cs);
|
2018-09-18 17:34:08 +08:00
|
|
|
int ipu_ic_task_init_rsc(struct ipu_ic *ic,
|
|
|
|
|
int in_width, int in_height,
|
|
|
|
|
int out_width, int out_height,
|
|
|
|
|
enum ipu_color_space in_cs,
|
|
|
|
|
enum ipu_color_space out_cs,
|
|
|
|
|
u32 rsc);
|
2014-08-11 19:04:50 +08:00
|
|
|
int ipu_ic_task_graphics_init(struct ipu_ic *ic,
|
|
|
|
|
enum ipu_color_space in_g_cs,
|
|
|
|
|
bool galpha_en, u32 galpha,
|
|
|
|
|
bool colorkey_en, u32 colorkey);
|
|
|
|
|
void ipu_ic_task_enable(struct ipu_ic *ic);
|
|
|
|
|
void ipu_ic_task_disable(struct ipu_ic *ic);
|
|
|
|
|
int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
|
|
|
|
|
u32 width, u32 height, int burst_size,
|
|
|
|
|
enum ipu_rotate_mode rot);
|
|
|
|
|
int ipu_ic_enable(struct ipu_ic *ic);
|
|
|
|
|
int ipu_ic_disable(struct ipu_ic *ic);
|
|
|
|
|
struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
|
|
|
|
|
void ipu_ic_put(struct ipu_ic *ic);
|
|
|
|
|
void ipu_ic_dump(struct ipu_ic *ic);
|
|
|
|
|
|
2016-08-18 08:50:16 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Video De-Interlacer (vdi) functions
|
|
|
|
|
*/
|
|
|
|
|
struct ipu_vdi;
|
|
|
|
|
void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
|
|
|
|
|
void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
|
|
|
|
|
void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
|
|
|
|
|
void ipu_vdi_unsetup(struct ipu_vdi *vdi);
|
|
|
|
|
int ipu_vdi_enable(struct ipu_vdi *vdi);
|
|
|
|
|
int ipu_vdi_disable(struct ipu_vdi *vdi);
|
|
|
|
|
struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
|
|
|
|
|
void ipu_vdi_put(struct ipu_vdi *vdi);
|
|
|
|
|
|
2012-05-09 22:59:01 +08:00
|
|
|
/*
|
|
|
|
|
* IPU Sensor Multiple FIFO Controller (SMFC) functions
|
|
|
|
|
*/
|
2014-06-26 09:05:34 +08:00
|
|
|
struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
|
|
|
|
|
void ipu_smfc_put(struct ipu_smfc *smfc);
|
|
|
|
|
int ipu_smfc_enable(struct ipu_smfc *smfc);
|
|
|
|
|
int ipu_smfc_disable(struct ipu_smfc *smfc);
|
|
|
|
|
int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
|
|
|
|
|
int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
|
2014-06-26 09:05:35 +08:00
|
|
|
int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
|
2012-05-09 22:59:01 +08:00
|
|
|
|
2013-10-10 22:18:38 +08:00
|
|
|
enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
|
2012-09-21 16:07:49 +08:00
|
|
|
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
|
2014-06-26 09:05:36 +08:00
|
|
|
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
|
2014-06-26 09:05:43 +08:00
|
|
|
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
|
2014-06-26 09:05:38 +08:00
|
|
|
bool ipu_pixelformat_is_planar(u32 pixelformat);
|
2014-06-26 09:05:37 +08:00
|
|
|
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
|
|
|
|
|
bool hflip, bool vflip);
|
|
|
|
|
int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
|
|
|
|
|
bool hflip, bool vflip);
|
2012-09-21 16:07:49 +08:00
|
|
|
|
|
|
|
|
struct ipu_client_platformdata {
|
2012-05-23 23:08:19 +08:00
|
|
|
int csi;
|
2012-09-21 16:07:49 +08:00
|
|
|
int di;
|
|
|
|
|
int dc;
|
|
|
|
|
int dp;
|
|
|
|
|
int dma[2];
|
2016-05-12 21:00:44 +08:00
|
|
|
struct device_node *of_node;
|
2012-09-21 16:07:49 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#endif /* __DRM_IPU_H__ */
|
