2009-12-11 17:24:15 +08:00
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/*
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* Copyright 2007 Dave Airlied
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors: Dave Airlied <airlied@linux.ie>
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* Ben Skeggs <darktama@iinet.net.au>
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* Jeremy Kolb <jkolb@brandeis.edu>
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*/
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2014-08-10 02:10:23 +08:00
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#include <linux/dma-mapping.h>
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2013-02-02 02:44:33 +08:00
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#include <linux/swiotlb.h>
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2009-12-11 17:24:15 +08:00
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2016-05-20 07:22:55 +08:00
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#include "nouveau_drv.h"
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2009-12-11 17:24:15 +08:00
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#include "nouveau_dma.h"
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2012-04-30 11:30:00 +08:00
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#include "nouveau_fence.h"
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2009-12-11 17:24:15 +08:00
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2012-07-20 06:17:34 +08:00
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#include "nouveau_bo.h"
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#include "nouveau_ttm.h"
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#include "nouveau_gem.h"
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2017-11-01 01:56:19 +08:00
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#include "nouveau_mem.h"
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2017-11-01 01:56:19 +08:00
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#include "nouveau_vmm.h"
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2009-12-27 04:46:36 +08:00
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2012-07-19 15:54:21 +08:00
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/*
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* NV10-NV40 tiling helpers
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*/
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static void
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2012-07-20 06:17:34 +08:00
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nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
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u32 addr, u32 size, u32 pitch, u32 flags)
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2012-07-19 15:54:21 +08:00
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{
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2012-07-31 14:16:21 +08:00
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struct nouveau_drm *drm = nouveau_drm(dev);
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2012-07-20 06:17:34 +08:00
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int i = reg - drm->tile.reg;
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2016-05-18 11:57:42 +08:00
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struct nvkm_device *device = nvxx_device(&drm->client.device);
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2015-08-20 12:54:22 +08:00
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struct nvkm_fb *fb = device->fb;
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2015-08-20 12:54:06 +08:00
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struct nvkm_fb_tile *tile = &fb->tile.region[i];
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2012-07-19 15:54:21 +08:00
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2012-07-20 06:17:34 +08:00
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nouveau_fence_unref(®->fence);
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2012-07-19 15:54:21 +08:00
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if (tile->pitch)
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2015-08-20 12:54:20 +08:00
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nvkm_fb_tile_fini(fb, i, tile);
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2012-07-19 15:54:21 +08:00
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if (pitch)
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2015-08-20 12:54:20 +08:00
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nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
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2012-07-19 15:54:21 +08:00
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2015-08-20 12:54:20 +08:00
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nvkm_fb_tile_prog(fb, i, tile);
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2012-07-19 15:54:21 +08:00
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}
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2012-07-20 06:17:34 +08:00
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static struct nouveau_drm_tile *
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2012-07-19 15:54:21 +08:00
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nv10_bo_get_tile_region(struct drm_device *dev, int i)
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{
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2012-07-31 14:16:21 +08:00
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struct nouveau_drm *drm = nouveau_drm(dev);
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2012-07-20 06:17:34 +08:00
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struct nouveau_drm_tile *tile = &drm->tile.reg[i];
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2012-07-19 15:54:21 +08:00
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2012-07-20 06:17:34 +08:00
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spin_lock(&drm->tile.lock);
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2012-07-19 15:54:21 +08:00
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if (!tile->used &&
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(!tile->fence || nouveau_fence_done(tile->fence)))
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tile->used = true;
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else
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tile = NULL;
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2012-07-20 06:17:34 +08:00
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spin_unlock(&drm->tile.lock);
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2012-07-19 15:54:21 +08:00
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return tile;
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}
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static void
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2012-07-20 06:17:34 +08:00
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nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
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2016-10-25 20:00:45 +08:00
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struct dma_fence *fence)
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2012-07-19 15:54:21 +08:00
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{
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2012-07-31 14:16:21 +08:00
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struct nouveau_drm *drm = nouveau_drm(dev);
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2012-07-19 15:54:21 +08:00
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if (tile) {
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2012-07-20 06:17:34 +08:00
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spin_lock(&drm->tile.lock);
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2016-10-25 20:00:45 +08:00
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tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
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2012-07-19 15:54:21 +08:00
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tile->used = false;
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2012-07-20 06:17:34 +08:00
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spin_unlock(&drm->tile.lock);
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2012-07-19 15:54:21 +08:00
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}
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}
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2012-07-20 06:17:34 +08:00
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static struct nouveau_drm_tile *
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nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
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2017-11-01 01:56:19 +08:00
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u32 size, u32 pitch, u32 zeta)
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2012-07-19 15:54:21 +08:00
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{
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2012-07-31 14:16:21 +08:00
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struct nouveau_drm *drm = nouveau_drm(dev);
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2016-05-18 11:57:42 +08:00
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struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
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2012-07-20 06:17:34 +08:00
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struct nouveau_drm_tile *tile, *found = NULL;
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2012-07-19 15:54:21 +08:00
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int i;
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2015-08-20 12:54:06 +08:00
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for (i = 0; i < fb->tile.regions; i++) {
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2012-07-19 15:54:21 +08:00
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tile = nv10_bo_get_tile_region(dev, i);
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if (pitch && !found) {
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found = tile;
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continue;
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2015-08-20 12:54:06 +08:00
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} else if (tile && fb->tile.region[i].pitch) {
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2012-07-19 15:54:21 +08:00
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/* Kill an unused tile region. */
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nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
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}
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nv10_bo_put_tile_region(dev, tile, NULL);
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}
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if (found)
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2017-11-01 01:56:19 +08:00
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nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
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2012-07-19 15:54:21 +08:00
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return found;
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}
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2009-12-11 17:24:15 +08:00
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static void
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nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
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{
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2012-07-20 06:17:34 +08:00
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struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
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struct drm_device *dev = drm->dev;
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2009-12-11 17:24:15 +08:00
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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2013-10-02 16:15:17 +08:00
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if (unlikely(nvbo->gem.filp))
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2009-12-11 17:24:15 +08:00
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DRM_ERROR("bo %p still attached to GEM object\n", bo);
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2013-07-07 16:37:35 +08:00
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WARN_ON(nvbo->pin_refcnt > 0);
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2012-07-19 15:54:21 +08:00
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nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
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2009-12-11 17:24:15 +08:00
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kfree(nvbo);
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}
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2016-05-23 10:34:49 +08:00
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static inline u64
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roundup_64(u64 x, u32 y)
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{
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x += y - 1;
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do_div(x, y);
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return x * y;
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}
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2009-12-11 23:51:09 +08:00
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static void
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2011-02-10 11:41:01 +08:00
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nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
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2016-05-23 10:34:49 +08:00
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int *align, u64 *size)
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2009-12-11 23:51:09 +08:00
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{
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2012-07-20 06:17:34 +08:00
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
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2016-05-18 11:57:42 +08:00
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struct nvif_device *device = &drm->client.device;
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2009-12-11 23:51:09 +08:00
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2014-08-10 02:10:22 +08:00
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if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
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2017-11-01 01:56:19 +08:00
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if (nvbo->mode) {
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2014-08-10 02:10:22 +08:00
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if (device->info.chipset >= 0x40) {
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2009-12-11 23:51:09 +08:00
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*align = 65536;
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2017-11-01 01:56:19 +08:00
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*size = roundup_64(*size, 64 * nvbo->mode);
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2009-12-11 23:51:09 +08:00
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2014-08-10 02:10:22 +08:00
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} else if (device->info.chipset >= 0x30) {
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2009-12-11 23:51:09 +08:00
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*align = 32768;
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2017-11-01 01:56:19 +08:00
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*size = roundup_64(*size, 64 * nvbo->mode);
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2009-12-11 23:51:09 +08:00
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2014-08-10 02:10:22 +08:00
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} else if (device->info.chipset >= 0x20) {
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2009-12-11 23:51:09 +08:00
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*align = 16384;
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2017-11-01 01:56:19 +08:00
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*size = roundup_64(*size, 64 * nvbo->mode);
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2009-12-11 23:51:09 +08:00
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2014-08-10 02:10:22 +08:00
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} else if (device->info.chipset >= 0x10) {
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2009-12-11 23:51:09 +08:00
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*align = 16384;
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2017-11-01 01:56:19 +08:00
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*size = roundup_64(*size, 32 * nvbo->mode);
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2009-12-11 23:51:09 +08:00
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}
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}
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2010-11-12 13:12:51 +08:00
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} else {
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2017-11-01 01:56:19 +08:00
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*size = roundup_64(*size, (1 << nvbo->page));
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*align = max((1 << nvbo->page), *align);
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2009-12-11 23:51:09 +08:00
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}
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2016-05-23 10:34:49 +08:00
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*size = roundup_64(*size, PAGE_SIZE);
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2009-12-11 23:51:09 +08:00
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}
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2009-12-11 17:24:15 +08:00
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int
|
2016-05-23 10:34:49 +08:00
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nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
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2011-06-07 12:21:29 +08:00
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uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
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2014-01-09 18:03:15 +08:00
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struct sg_table *sg, struct reservation_object *robj,
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2011-06-07 12:21:29 +08:00
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struct nouveau_bo **pnvbo)
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2009-12-11 17:24:15 +08:00
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{
|
2017-11-01 01:56:19 +08:00
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struct nouveau_drm *drm = cli->drm;
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2009-12-11 17:24:15 +08:00
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struct nouveau_bo *nvbo;
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2011-11-12 04:42:57 +08:00
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size_t acc_size;
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2011-06-06 12:15:46 +08:00
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int ret;
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2012-04-02 18:53:06 +08:00
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int type = ttm_bo_type_device;
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2013-07-07 16:40:19 +08:00
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2016-05-23 10:34:49 +08:00
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if (!size) {
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NV_WARN(drm, "skipped size %016llx\n", size);
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2013-07-07 16:40:19 +08:00
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return -EINVAL;
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}
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2012-04-02 18:53:06 +08:00
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if (sg)
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type = ttm_bo_type_sg;
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2009-12-11 17:24:15 +08:00
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nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
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if (!nvbo)
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return -ENOMEM;
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INIT_LIST_HEAD(&nvbo->head);
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INIT_LIST_HEAD(&nvbo->entry);
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2011-06-06 12:07:04 +08:00
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INIT_LIST_HEAD(&nvbo->vma_list);
|
2012-07-20 06:17:34 +08:00
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nvbo->bo.bdev = &drm->ttm.bdev;
|
2016-05-24 15:26:48 +08:00
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nvbo->cli = cli;
|
2009-12-11 17:24:15 +08:00
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|
2016-05-18 11:57:42 +08:00
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if (!nvxx_device(&drm->client.device)->func->cpu_coherent)
|
2016-09-18 18:21:56 +08:00
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nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
|
2014-10-27 17:49:17 +08:00
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2017-11-01 01:56:19 +08:00
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if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
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nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
|
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nvbo->comp = gf100_pte_storage_type_map[nvbo->kind] != nvbo->kind;
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} else
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if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
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nvbo->kind = (tile_flags & 0x00007f00) >> 8;
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nvbo->comp = (tile_flags & 0x00030000) >> 16;
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} else {
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nvbo->zeta = (tile_flags & 0x00000007);
|
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|
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}
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nvbo->mode = tile_mode;
|
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|
|
nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
|
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|
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nvbo->page = 12;
|
2014-08-10 02:10:20 +08:00
|
|
|
if (drm->client.vm) {
|
2011-06-06 12:15:46 +08:00
|
|
|
if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
|
2017-11-01 01:56:19 +08:00
|
|
|
nvbo->page = drm->client.vm->mmu->lpg_shift;
|
|
|
|
else {
|
|
|
|
if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
|
|
|
|
nvbo->kind = gf100_pte_storage_type_map[nvbo->kind];
|
|
|
|
nvbo->comp = 0;
|
|
|
|
}
|
2011-06-06 12:15:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
nouveau_bo_fixup_align(nvbo, flags, &align, &size);
|
2011-06-06 12:07:04 +08:00
|
|
|
nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
|
|
|
|
nouveau_bo_placement_set(nvbo, flags, 0);
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2012-07-20 06:17:34 +08:00
|
|
|
acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
|
2011-11-12 04:42:57 +08:00
|
|
|
sizeof(struct nouveau_bo));
|
|
|
|
|
2012-07-20 06:17:34 +08:00
|
|
|
ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
|
2012-04-02 18:53:06 +08:00
|
|
|
type, &nvbo->placement,
|
2012-11-07 05:49:51 +08:00
|
|
|
align >> PAGE_SHIFT, false, NULL, acc_size, sg,
|
2014-01-09 18:03:15 +08:00
|
|
|
robj, nouveau_bo_del_ttm);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret) {
|
|
|
|
/* ttm will call nouveau_bo_del_ttm if it fails.. */
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
*pnvbo = nvbo;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-18 20:07:47 +08:00
|
|
|
static void
|
2014-08-27 19:16:04 +08:00
|
|
|
set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
|
2010-03-18 20:07:47 +08:00
|
|
|
{
|
|
|
|
*n = 0;
|
|
|
|
|
|
|
|
if (type & TTM_PL_FLAG_VRAM)
|
2014-08-27 19:16:04 +08:00
|
|
|
pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
|
2010-03-18 20:07:47 +08:00
|
|
|
if (type & TTM_PL_FLAG_TT)
|
2014-08-27 19:16:04 +08:00
|
|
|
pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
|
2010-03-18 20:07:47 +08:00
|
|
|
if (type & TTM_PL_FLAG_SYSTEM)
|
2014-08-27 19:16:04 +08:00
|
|
|
pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
|
2010-03-18 20:07:47 +08:00
|
|
|
}
|
|
|
|
|
2010-10-10 12:07:32 +08:00
|
|
|
static void
|
|
|
|
set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
|
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
2016-05-18 11:57:42 +08:00
|
|
|
u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
|
2014-08-27 19:16:04 +08:00
|
|
|
unsigned i, fpfn, lpfn;
|
2010-10-10 12:07:32 +08:00
|
|
|
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
|
2017-11-01 01:56:19 +08:00
|
|
|
nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
|
2011-11-07 04:21:28 +08:00
|
|
|
nvbo->bo.mem.num_pages < vram_pages / 4) {
|
2010-10-10 12:07:32 +08:00
|
|
|
/*
|
|
|
|
* Make sure that the color and depth buffers are handled
|
|
|
|
* by independent memory controller units. Up to a 9x
|
|
|
|
* speed up when alpha-blending and depth-test are enabled
|
|
|
|
* at the same time.
|
|
|
|
*/
|
2017-11-01 01:56:19 +08:00
|
|
|
if (nvbo->zeta) {
|
2014-08-27 19:16:04 +08:00
|
|
|
fpfn = vram_pages / 2;
|
|
|
|
lpfn = ~0;
|
2010-10-10 12:07:32 +08:00
|
|
|
} else {
|
2014-08-27 19:16:04 +08:00
|
|
|
fpfn = 0;
|
|
|
|
lpfn = vram_pages / 2;
|
|
|
|
}
|
|
|
|
for (i = 0; i < nvbo->placement.num_placement; ++i) {
|
|
|
|
nvbo->placements[i].fpfn = fpfn;
|
|
|
|
nvbo->placements[i].lpfn = lpfn;
|
|
|
|
}
|
|
|
|
for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
|
|
|
|
nvbo->busy_placements[i].fpfn = fpfn;
|
|
|
|
nvbo->busy_placements[i].lpfn = lpfn;
|
2010-10-10 12:07:32 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
void
|
2010-03-18 20:07:47 +08:00
|
|
|
nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2010-03-18 20:07:47 +08:00
|
|
|
struct ttm_placement *pl = &nvbo->placement;
|
2014-10-27 17:49:17 +08:00
|
|
|
uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
|
|
|
|
TTM_PL_MASK_CACHING) |
|
|
|
|
(nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
|
2010-03-18 20:07:47 +08:00
|
|
|
|
|
|
|
pl->placement = nvbo->placements;
|
|
|
|
set_placement_list(nvbo->placements, &pl->num_placement,
|
|
|
|
type, flags);
|
|
|
|
|
|
|
|
pl->busy_placement = nvbo->busy_placements;
|
|
|
|
set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
|
|
|
|
type | busy, flags);
|
2010-10-10 12:07:32 +08:00
|
|
|
|
|
|
|
set_placement_range(nvbo, type);
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2014-11-10 09:24:27 +08:00
|
|
|
nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
2009-12-11 17:24:15 +08:00
|
|
|
struct ttm_buffer_object *bo = &nvbo->bo;
|
2014-11-10 09:24:27 +08:00
|
|
|
bool force = false, evict = false;
|
2010-03-18 20:07:47 +08:00
|
|
|
int ret;
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2016-04-06 17:12:03 +08:00
|
|
|
ret = ttm_bo_reserve(bo, false, false, NULL);
|
2012-12-12 04:52:30 +08:00
|
|
|
if (ret)
|
2014-11-10 09:12:17 +08:00
|
|
|
return ret;
|
2012-12-12 04:52:30 +08:00
|
|
|
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
|
2014-11-10 09:24:27 +08:00
|
|
|
memtype == TTM_PL_FLAG_VRAM && contig) {
|
2017-11-01 01:56:19 +08:00
|
|
|
if (!nvbo->contig) {
|
|
|
|
nvbo->contig = true;
|
2014-11-10 09:24:27 +08:00
|
|
|
force = true;
|
2017-11-01 01:56:19 +08:00
|
|
|
evict = true;
|
2014-11-10 09:24:27 +08:00
|
|
|
}
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2014-11-10 09:24:27 +08:00
|
|
|
if (nvbo->pin_refcnt) {
|
|
|
|
if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
|
|
|
|
NV_ERROR(drm, "bo %p pinned elsewhere: "
|
|
|
|
"0x%08x vs 0x%08x\n", bo,
|
|
|
|
1 << bo->mem.mem_type, memtype);
|
|
|
|
ret = -EBUSY;
|
|
|
|
}
|
|
|
|
nvbo->pin_refcnt++;
|
2014-11-10 09:12:17 +08:00
|
|
|
goto out;
|
2014-11-10 09:24:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (evict) {
|
|
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
|
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
}
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2014-11-10 09:24:27 +08:00
|
|
|
nvbo->pin_refcnt++;
|
2010-03-18 20:07:47 +08:00
|
|
|
nouveau_bo_placement_set(nvbo, memtype, 0);
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2014-11-10 09:12:17 +08:00
|
|
|
/* drop pin_refcnt temporarily, so we don't trip the assertion
|
|
|
|
* in nouveau_bo_move() that makes sure we're not trying to
|
|
|
|
* move a pinned buffer
|
|
|
|
*/
|
|
|
|
nvbo->pin_refcnt--;
|
2012-11-28 19:25:44 +08:00
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
2014-11-06 12:34:31 +08:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
2014-11-10 09:12:17 +08:00
|
|
|
nvbo->pin_refcnt++;
|
2014-11-06 12:34:31 +08:00
|
|
|
|
|
|
|
switch (bo->mem.mem_type) {
|
|
|
|
case TTM_PL_VRAM:
|
|
|
|
drm->gem.vram_available -= bo->mem.size;
|
|
|
|
break;
|
|
|
|
case TTM_PL_TT:
|
|
|
|
drm->gem.gart_available -= bo->mem.size;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
2014-10-27 17:11:52 +08:00
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
out:
|
2014-11-10 09:24:27 +08:00
|
|
|
if (force && ret)
|
2017-11-01 01:56:19 +08:00
|
|
|
nvbo->contig = false;
|
2012-12-12 04:52:30 +08:00
|
|
|
ttm_bo_unreserve(bo);
|
2009-12-11 17:24:15 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nouveau_bo_unpin(struct nouveau_bo *nvbo)
|
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
2009-12-11 17:24:15 +08:00
|
|
|
struct ttm_buffer_object *bo = &nvbo->bo;
|
2013-07-07 16:37:35 +08:00
|
|
|
int ret, ref;
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2016-04-06 17:12:03 +08:00
|
|
|
ret = ttm_bo_reserve(bo, false, false, NULL);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2013-07-07 16:37:35 +08:00
|
|
|
ref = --nvbo->pin_refcnt;
|
|
|
|
WARN_ON_ONCE(ref < 0);
|
|
|
|
if (ref)
|
2012-12-12 04:52:30 +08:00
|
|
|
goto out;
|
|
|
|
|
2010-03-18 20:07:47 +08:00
|
|
|
nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2012-11-28 19:25:44 +08:00
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret == 0) {
|
|
|
|
switch (bo->mem.mem_type) {
|
|
|
|
case TTM_PL_VRAM:
|
2012-07-20 06:17:34 +08:00
|
|
|
drm->gem.vram_available += bo->mem.size;
|
2009-12-11 17:24:15 +08:00
|
|
|
break;
|
|
|
|
case TTM_PL_TT:
|
2012-07-20 06:17:34 +08:00
|
|
|
drm->gem.gart_available += bo->mem.size;
|
2009-12-11 17:24:15 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-12 04:52:30 +08:00
|
|
|
out:
|
2009-12-11 17:24:15 +08:00
|
|
|
ttm_bo_unreserve(bo);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
nouveau_bo_map(struct nouveau_bo *nvbo)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-04-06 17:12:03 +08:00
|
|
|
ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-07-13 14:29:35 +08:00
|
|
|
ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
ttm_bo_unreserve(&nvbo->bo);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_bo_unmap(struct nouveau_bo *nvbo)
|
|
|
|
{
|
2014-10-27 17:49:17 +08:00
|
|
|
if (!nvbo)
|
|
|
|
return;
|
|
|
|
|
2016-07-13 14:29:35 +08:00
|
|
|
ttm_bo_kunmap(&nvbo->kmap);
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2014-10-27 17:49:19 +08:00
|
|
|
void
|
|
|
|
nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
|
|
|
|
{
|
|
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
2016-05-18 11:57:42 +08:00
|
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
2014-10-27 17:49:19 +08:00
|
|
|
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!ttm_dma)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Don't waste time looping if the object is coherent */
|
|
|
|
if (nvbo->force_coherent)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < ttm_dma->ttm.num_pages; i++)
|
2015-08-20 12:54:23 +08:00
|
|
|
dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i],
|
|
|
|
PAGE_SIZE, DMA_TO_DEVICE);
|
2014-10-27 17:49:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
|
|
|
|
{
|
|
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
2016-05-18 11:57:42 +08:00
|
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
2014-10-27 17:49:19 +08:00
|
|
|
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!ttm_dma)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Don't waste time looping if the object is coherent */
|
|
|
|
if (nvbo->force_coherent)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = 0; i < ttm_dma->ttm.num_pages; i++)
|
2015-08-20 12:54:23 +08:00
|
|
|
dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i],
|
|
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
2014-10-27 17:49:19 +08:00
|
|
|
}
|
|
|
|
|
2010-11-22 06:50:27 +08:00
|
|
|
int
|
|
|
|
nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
|
2012-11-28 19:25:44 +08:00
|
|
|
bool no_wait_gpu)
|
2010-11-22 06:50:27 +08:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2012-11-28 19:25:44 +08:00
|
|
|
ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
|
|
|
|
interruptible, no_wait_gpu);
|
2010-11-22 06:50:27 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-10-27 17:49:19 +08:00
|
|
|
nouveau_bo_sync_for_device(nvbo);
|
|
|
|
|
2010-11-22 06:50:27 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
void
|
|
|
|
nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
|
|
|
|
{
|
|
|
|
bool is_iomem;
|
|
|
|
u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2016-07-13 14:29:35 +08:00
|
|
|
mem += index;
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
if (is_iomem)
|
|
|
|
iowrite16_native(val, (void __force __iomem *)mem);
|
|
|
|
else
|
|
|
|
*mem = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
u32
|
|
|
|
nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
|
|
|
|
{
|
|
|
|
bool is_iomem;
|
|
|
|
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2016-07-13 14:29:35 +08:00
|
|
|
mem += index;
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
if (is_iomem)
|
|
|
|
return ioread32_native((void __force __iomem *)mem);
|
|
|
|
else
|
|
|
|
return *mem;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
|
|
|
|
{
|
|
|
|
bool is_iomem;
|
|
|
|
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2016-07-13 14:29:35 +08:00
|
|
|
mem += index;
|
2014-10-27 17:49:17 +08:00
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
if (is_iomem)
|
|
|
|
iowrite32_native(val, (void __force __iomem *)mem);
|
|
|
|
else
|
|
|
|
*mem = val;
|
|
|
|
}
|
|
|
|
|
2011-11-02 08:46:13 +08:00
|
|
|
static struct ttm_tt *
|
2012-07-20 06:17:34 +08:00
|
|
|
nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
|
|
|
|
uint32_t page_flags, struct page *dummy_read)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2015-09-09 22:45:52 +08:00
|
|
|
#if IS_ENABLED(CONFIG_AGP)
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2015-08-20 12:54:23 +08:00
|
|
|
if (drm->agp.bridge) {
|
|
|
|
return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
|
2012-07-20 06:17:34 +08:00
|
|
|
page_flags, dummy_read);
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
2012-10-14 05:58:26 +08:00
|
|
|
#endif
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2012-07-20 06:17:34 +08:00
|
|
|
return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
|
|
|
|
{
|
|
|
|
/* We'll do this from user space. */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
|
|
|
|
struct ttm_mem_type_manager *man)
|
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
2009-12-11 17:24:15 +08:00
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case TTM_PL_SYSTEM:
|
|
|
|
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
|
|
|
|
man->available_caching = TTM_PL_MASK_CACHING;
|
|
|
|
man->default_caching = TTM_PL_FLAG_CACHED;
|
|
|
|
break;
|
|
|
|
case TTM_PL_VRAM:
|
2014-06-27 18:28:50 +08:00
|
|
|
man->flags = TTM_MEMTYPE_FLAG_FIXED |
|
|
|
|
TTM_MEMTYPE_FLAG_MAPPABLE;
|
|
|
|
man->available_caching = TTM_PL_FLAG_UNCACHED |
|
|
|
|
TTM_PL_FLAG_WC;
|
|
|
|
man->default_caching = TTM_PL_FLAG_WC;
|
|
|
|
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
|
2014-06-27 18:28:50 +08:00
|
|
|
/* Some BARs do not support being ioremapped WC */
|
2016-05-18 11:57:42 +08:00
|
|
|
if (nvxx_bar(&drm->client.device)->iomap_uncached) {
|
2014-06-27 18:28:50 +08:00
|
|
|
man->available_caching = TTM_PL_FLAG_UNCACHED;
|
|
|
|
man->default_caching = TTM_PL_FLAG_UNCACHED;
|
|
|
|
}
|
|
|
|
|
2010-08-25 13:26:04 +08:00
|
|
|
man->func = &nouveau_vram_manager;
|
2010-11-15 09:53:16 +08:00
|
|
|
man->io_reserve_fastpath = false;
|
|
|
|
man->use_io_reserve_lru = true;
|
|
|
|
} else {
|
2010-08-25 13:26:04 +08:00
|
|
|
man->func = &ttm_bo_manager_func;
|
2010-11-15 09:53:16 +08:00
|
|
|
}
|
2009-12-11 17:24:15 +08:00
|
|
|
break;
|
|
|
|
case TTM_PL_TT:
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA)
|
2011-02-10 10:59:51 +08:00
|
|
|
man->func = &nouveau_gart_manager;
|
2012-07-14 17:09:17 +08:00
|
|
|
else
|
2015-08-20 12:54:23 +08:00
|
|
|
if (!drm->agp.bridge)
|
2012-07-14 17:09:17 +08:00
|
|
|
man->func = &nv04_gart_manager;
|
2011-02-10 10:59:51 +08:00
|
|
|
else
|
|
|
|
man->func = &ttm_bo_manager_func;
|
2012-07-20 06:17:34 +08:00
|
|
|
|
2015-08-20 12:54:23 +08:00
|
|
|
if (drm->agp.bridge) {
|
2010-04-09 20:39:25 +08:00
|
|
|
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
|
2010-11-21 05:11:22 +08:00
|
|
|
man->available_caching = TTM_PL_FLAG_UNCACHED |
|
|
|
|
TTM_PL_FLAG_WC;
|
|
|
|
man->default_caching = TTM_PL_FLAG_WC;
|
2012-07-20 06:17:34 +08:00
|
|
|
} else {
|
2009-12-11 17:24:15 +08:00
|
|
|
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
|
|
|
|
TTM_MEMTYPE_FLAG_CMA;
|
|
|
|
man->available_caching = TTM_PL_MASK_CACHING;
|
|
|
|
man->default_caching = TTM_PL_FLAG_CACHED;
|
|
|
|
}
|
2012-07-20 06:17:34 +08:00
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
|
|
|
|
{
|
|
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
|
|
|
|
switch (bo->mem.mem_type) {
|
2009-12-12 01:40:17 +08:00
|
|
|
case TTM_PL_VRAM:
|
2010-03-18 20:07:47 +08:00
|
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
|
|
|
|
TTM_PL_FLAG_SYSTEM);
|
2009-12-12 01:40:17 +08:00
|
|
|
break;
|
2009-12-11 17:24:15 +08:00
|
|
|
default:
|
2010-03-18 20:07:47 +08:00
|
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
|
2009-12-11 17:24:15 +08:00
|
|
|
break;
|
|
|
|
}
|
2009-12-12 01:40:17 +08:00
|
|
|
|
|
|
|
*pl = nvbo->placement;
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-08-06 17:38:25 +08:00
|
|
|
static int
|
|
|
|
nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
|
|
{
|
|
|
|
int ret = RING_SPACE(chan, 2);
|
|
|
|
if (ret == 0) {
|
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
|
2013-07-09 12:20:15 +08:00
|
|
|
OUT_RING (chan, handle & 0x0000ffff);
|
2012-08-06 17:38:25 +08:00
|
|
|
FIRE_RING (chan);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-03-20 12:36:04 +08:00
|
|
|
static int
|
|
|
|
nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2012-03-20 12:36:04 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
2012-03-20 12:36:04 +08:00
|
|
|
int ret = RING_SPACE(chan, 10);
|
|
|
|
if (ret == 0) {
|
2012-04-01 19:09:13 +08:00
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
|
2017-11-01 01:56:19 +08:00
|
|
|
OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
|
|
|
|
OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
|
|
|
|
OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
|
|
|
|
OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
|
2012-03-20 12:36:04 +08:00
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
2016-05-17 09:13:37 +08:00
|
|
|
OUT_RING (chan, new_reg->num_pages);
|
2012-04-01 19:09:13 +08:00
|
|
|
BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
|
2012-03-20 12:36:04 +08:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
static int
|
|
|
|
nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
|
|
{
|
|
|
|
int ret = RING_SPACE(chan, 2);
|
|
|
|
if (ret == 0) {
|
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
|
|
|
|
OUT_RING (chan, handle);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-04 13:17:28 +08:00
|
|
|
static int
|
|
|
|
nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2012-05-04 13:17:28 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
|
|
u64 src_offset = mem->vma[0].addr;
|
|
|
|
u64 dst_offset = mem->vma[1].addr;
|
2016-05-17 09:13:37 +08:00
|
|
|
u32 page_count = new_reg->num_pages;
|
2012-05-04 13:17:28 +08:00
|
|
|
int ret;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
page_count = new_reg->num_pages;
|
2012-05-04 13:17:28 +08:00
|
|
|
while (page_count) {
|
|
|
|
int line_count = (page_count > 8191) ? 8191 : page_count;
|
|
|
|
|
|
|
|
ret = RING_SPACE(chan, 11);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
|
|
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, line_count);
|
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
|
|
|
|
OUT_RING (chan, 0x00000110);
|
|
|
|
|
|
|
|
page_count -= line_count;
|
|
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-12-09 13:17:10 +08:00
|
|
|
static int
|
|
|
|
nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2010-12-09 13:17:10 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
|
|
u64 src_offset = mem->vma[0].addr;
|
|
|
|
u64 dst_offset = mem->vma[1].addr;
|
2016-05-17 09:13:37 +08:00
|
|
|
u32 page_count = new_reg->num_pages;
|
2010-12-09 13:17:10 +08:00
|
|
|
int ret;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
page_count = new_reg->num_pages;
|
2010-12-09 13:17:10 +08:00
|
|
|
while (page_count) {
|
|
|
|
int line_count = (page_count > 2047) ? 2047 : page_count;
|
|
|
|
|
|
|
|
ret = RING_SPACE(chan, 12);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
|
2010-12-09 13:17:10 +08:00
|
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
|
2010-12-09 13:17:10 +08:00
|
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, PAGE_SIZE); /* src_pitch */
|
|
|
|
OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
|
|
|
|
OUT_RING (chan, PAGE_SIZE); /* line_length */
|
|
|
|
OUT_RING (chan, line_count);
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
|
2010-12-09 13:17:10 +08:00
|
|
|
OUT_RING (chan, 0x00100110);
|
|
|
|
|
|
|
|
page_count -= line_count;
|
|
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-04 13:15:12 +08:00
|
|
|
static int
|
|
|
|
nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2012-05-04 13:15:12 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
|
|
u64 src_offset = mem->vma[0].addr;
|
|
|
|
u64 dst_offset = mem->vma[1].addr;
|
2016-05-17 09:13:37 +08:00
|
|
|
u32 page_count = new_reg->num_pages;
|
2012-05-04 13:15:12 +08:00
|
|
|
int ret;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
page_count = new_reg->num_pages;
|
2012-05-04 13:15:12 +08:00
|
|
|
while (page_count) {
|
|
|
|
int line_count = (page_count > 8191) ? 8191 : page_count;
|
|
|
|
|
|
|
|
ret = RING_SPACE(chan, 11);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
|
|
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
|
|
OUT_RING (chan, line_count);
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
|
|
|
|
OUT_RING (chan, 0x00000110);
|
|
|
|
|
|
|
|
page_count -= line_count;
|
|
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-04 12:34:16 +08:00
|
|
|
static int
|
|
|
|
nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2012-05-04 12:34:16 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
2012-05-04 12:34:16 +08:00
|
|
|
int ret = RING_SPACE(chan, 7);
|
|
|
|
if (ret == 0) {
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
|
2017-11-01 01:56:19 +08:00
|
|
|
OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
|
|
|
|
OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
|
|
|
|
OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
|
|
|
|
OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
|
2012-05-04 12:34:16 +08:00
|
|
|
OUT_RING (chan, 0x00000000 /* COPY */);
|
2016-05-17 09:13:37 +08:00
|
|
|
OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
|
2012-05-04 12:34:16 +08:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-04 12:21:15 +08:00
|
|
|
static int
|
|
|
|
nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2012-05-04 12:21:15 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
2012-05-04 12:21:15 +08:00
|
|
|
int ret = RING_SPACE(chan, 7);
|
|
|
|
if (ret == 0) {
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
|
2016-05-17 09:13:37 +08:00
|
|
|
OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
|
2017-11-01 01:56:19 +08:00
|
|
|
OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
|
|
|
|
OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
|
|
|
|
OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
|
|
|
|
OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
|
2012-05-04 12:21:15 +08:00
|
|
|
OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
static int
|
|
|
|
nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
int ret = RING_SPACE(chan, 6);
|
2012-05-04 12:01:52 +08:00
|
|
|
if (ret == 0) {
|
2012-07-20 06:17:34 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
|
|
|
|
OUT_RING (chan, handle);
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
|
2014-08-10 02:10:23 +08:00
|
|
|
OUT_RING (chan, chan->drm->ntfy.handle);
|
|
|
|
OUT_RING (chan, chan->vram.handle);
|
|
|
|
OUT_RING (chan, chan->vram.handle);
|
2012-05-04 12:01:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
static int
|
2010-08-26 09:32:01 +08:00
|
|
|
nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
2016-05-17 09:13:37 +08:00
|
|
|
u64 length = (new_reg->num_pages << PAGE_SHIFT);
|
2017-11-01 01:56:19 +08:00
|
|
|
u64 src_offset = mem->vma[0].addr;
|
|
|
|
u64 dst_offset = mem->vma[1].addr;
|
|
|
|
int src_tiled = !!mem->kind;
|
|
|
|
int dst_tiled = !!nouveau_mem(new_reg)->kind;
|
2009-12-11 17:24:15 +08:00
|
|
|
int ret;
|
|
|
|
|
2010-08-26 09:32:01 +08:00
|
|
|
while (length) {
|
|
|
|
u32 amount, stride, height;
|
|
|
|
|
2013-11-12 20:34:08 +08:00
|
|
|
ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2010-09-23 13:21:17 +08:00
|
|
|
amount = min(length, (u64)(4 * 1024 * 1024));
|
|
|
|
stride = 16 * 4;
|
2010-08-26 09:32:01 +08:00
|
|
|
height = amount / stride;
|
|
|
|
|
2013-11-12 20:34:08 +08:00
|
|
|
if (src_tiled) {
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, 0);
|
2010-09-23 13:21:17 +08:00
|
|
|
OUT_RING (chan, 0);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, stride);
|
|
|
|
OUT_RING (chan, height);
|
|
|
|
OUT_RING (chan, 1);
|
|
|
|
OUT_RING (chan, 0);
|
|
|
|
OUT_RING (chan, 0);
|
|
|
|
} else {
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, 1);
|
|
|
|
}
|
2013-11-12 20:34:08 +08:00
|
|
|
if (dst_tiled) {
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, 0);
|
2010-09-23 13:21:17 +08:00
|
|
|
OUT_RING (chan, 0);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, stride);
|
|
|
|
OUT_RING (chan, height);
|
|
|
|
OUT_RING (chan, 1);
|
|
|
|
OUT_RING (chan, 0);
|
|
|
|
OUT_RING (chan, 0);
|
|
|
|
} else {
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, 1);
|
|
|
|
}
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
|
|
OUT_RING (chan, stride);
|
|
|
|
OUT_RING (chan, stride);
|
|
|
|
OUT_RING (chan, stride);
|
|
|
|
OUT_RING (chan, height);
|
|
|
|
OUT_RING (chan, 0x00000101);
|
|
|
|
OUT_RING (chan, 0x00000000);
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, 0);
|
|
|
|
|
|
|
|
length -= amount;
|
|
|
|
src_offset += amount;
|
|
|
|
dst_offset += amount;
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2010-08-26 09:32:01 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
static int
|
|
|
|
nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
int ret = RING_SPACE(chan, 4);
|
2012-05-04 12:01:52 +08:00
|
|
|
if (ret == 0) {
|
2012-07-20 06:17:34 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
|
|
|
|
OUT_RING (chan, handle);
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
|
2014-08-10 02:10:23 +08:00
|
|
|
OUT_RING (chan, chan->drm->ntfy.handle);
|
2012-05-04 12:01:52 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-02-16 07:10:20 +08:00
|
|
|
static inline uint32_t
|
|
|
|
nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct nouveau_channel *chan, struct ttm_mem_reg *reg)
|
2011-02-16 07:10:20 +08:00
|
|
|
{
|
2016-05-17 09:13:37 +08:00
|
|
|
if (reg->mem_type == TTM_PL_TT)
|
2012-07-20 06:17:34 +08:00
|
|
|
return NvDmaTT;
|
2014-08-10 02:10:23 +08:00
|
|
|
return chan->vram.handle;
|
2011-02-16 07:10:20 +08:00
|
|
|
}
|
|
|
|
|
2010-08-26 09:32:01 +08:00
|
|
|
static int
|
|
|
|
nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
2010-08-26 09:32:01 +08:00
|
|
|
{
|
2016-05-17 09:13:37 +08:00
|
|
|
u32 src_offset = old_reg->start << PAGE_SHIFT;
|
|
|
|
u32 dst_offset = new_reg->start << PAGE_SHIFT;
|
|
|
|
u32 page_count = new_reg->num_pages;
|
2010-08-26 09:32:01 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = RING_SPACE(chan, 3);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
|
2016-05-17 09:13:37 +08:00
|
|
|
OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg));
|
|
|
|
OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
|
2010-08-26 09:32:01 +08:00
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
page_count = new_reg->num_pages;
|
2009-12-11 17:24:15 +08:00
|
|
|
while (page_count) {
|
|
|
|
int line_count = (page_count > 2047) ? 2047 : page_count;
|
|
|
|
|
|
|
|
ret = RING_SPACE(chan, 11);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-08-26 09:32:01 +08:00
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy,
|
2009-12-11 17:24:15 +08:00
|
|
|
NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, src_offset);
|
|
|
|
OUT_RING (chan, dst_offset);
|
|
|
|
OUT_RING (chan, PAGE_SIZE); /* src_pitch */
|
|
|
|
OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
|
|
|
|
OUT_RING (chan, PAGE_SIZE); /* line_length */
|
|
|
|
OUT_RING (chan, line_count);
|
|
|
|
OUT_RING (chan, 0x00000101);
|
|
|
|
OUT_RING (chan, 0x00000000);
|
2012-05-04 12:01:52 +08:00
|
|
|
BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
|
2010-08-26 09:32:01 +08:00
|
|
|
OUT_RING (chan, 0);
|
2009-12-11 17:24:15 +08:00
|
|
|
|
|
|
|
page_count -= line_count;
|
|
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
|
|
}
|
|
|
|
|
2010-08-26 09:32:01 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-06 18:54:42 +08:00
|
|
|
static int
|
2013-11-22 08:35:25 +08:00
|
|
|
nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *reg)
|
2011-06-06 18:54:42 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
|
|
|
|
struct nouveau_mem *new_mem = nouveau_mem(reg);
|
|
|
|
struct nvkm_vm *vmm = drm->client.vm;
|
2016-05-17 09:13:37 +08:00
|
|
|
u64 size = (u64)reg->num_pages << PAGE_SHIFT;
|
2011-06-06 18:54:42 +08:00
|
|
|
int ret;
|
|
|
|
|
2017-11-01 01:56:19 +08:00
|
|
|
ret = nvkm_vm_get(vmm, size, old_mem->mem.page, NV_MEM_ACCESS_RW,
|
|
|
|
&old_mem->vma[0]);
|
2011-06-06 18:54:42 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-11-01 01:56:19 +08:00
|
|
|
ret = nvkm_vm_get(vmm, size, new_mem->mem.page, NV_MEM_ACCESS_RW,
|
|
|
|
&old_mem->vma[1]);
|
2013-11-22 08:35:25 +08:00
|
|
|
if (ret) {
|
2016-05-17 09:13:37 +08:00
|
|
|
nvkm_vm_put(&old_mem->vma[0]);
|
2013-11-22 08:35:25 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-11-01 01:56:19 +08:00
|
|
|
ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
|
|
|
|
if (ret)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
|
|
|
|
done:
|
|
|
|
if (ret) {
|
|
|
|
nvkm_vm_put(&old_mem->vma[1]);
|
|
|
|
nvkm_vm_put(&old_mem->vma[0]);
|
|
|
|
}
|
2011-06-06 18:54:42 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-26 09:32:01 +08:00
|
|
|
static int
|
|
|
|
nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
2010-08-26 09:32:01 +08:00
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
2013-09-18 05:26:34 +08:00
|
|
|
struct nouveau_channel *chan = drm->ttm.chan;
|
2015-08-20 12:54:15 +08:00
|
|
|
struct nouveau_cli *cli = (void *)chan->user.client;
|
2013-11-22 08:39:57 +08:00
|
|
|
struct nouveau_fence *fence;
|
2010-08-26 09:32:01 +08:00
|
|
|
int ret;
|
|
|
|
|
2011-06-06 18:54:42 +08:00
|
|
|
/* create temporary vmas for the transfer and attach them to the
|
2015-01-14 13:36:34 +08:00
|
|
|
* old nvkm_mem node, these will get cleaned up after ttm has
|
2011-06-06 18:54:42 +08:00
|
|
|
* destroyed the ttm_mem_reg
|
2011-02-10 09:22:12 +08:00
|
|
|
*/
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = nouveau_bo_move_prep(drm, bo, new_reg);
|
2011-06-06 18:54:42 +08:00
|
|
|
if (ret)
|
2013-11-22 08:35:25 +08:00
|
|
|
return ret;
|
2011-02-10 09:22:12 +08:00
|
|
|
}
|
|
|
|
|
2014-08-10 02:10:22 +08:00
|
|
|
mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
|
2014-09-16 17:15:07 +08:00
|
|
|
ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
|
2010-10-05 14:53:48 +08:00
|
|
|
if (ret == 0) {
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
|
2013-11-22 08:39:57 +08:00
|
|
|
if (ret == 0) {
|
|
|
|
ret = nouveau_fence_new(chan, false, &fence);
|
|
|
|
if (ret == 0) {
|
2014-04-02 23:14:48 +08:00
|
|
|
ret = ttm_bo_move_accel_cleanup(bo,
|
|
|
|
&fence->base,
|
2013-11-22 08:39:57 +08:00
|
|
|
evict,
|
2016-05-17 09:13:37 +08:00
|
|
|
new_reg);
|
2013-11-22 08:39:57 +08:00
|
|
|
nouveau_fence_unref(&fence);
|
|
|
|
}
|
|
|
|
}
|
2010-10-05 14:53:48 +08:00
|
|
|
}
|
2014-08-10 02:10:22 +08:00
|
|
|
mutex_unlock(&cli->mutex);
|
2010-10-05 14:53:48 +08:00
|
|
|
return ret;
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2012-05-04 12:01:52 +08:00
|
|
|
void
|
2012-08-06 17:38:25 +08:00
|
|
|
nouveau_bo_move_init(struct nouveau_drm *drm)
|
2012-05-04 12:01:52 +08:00
|
|
|
{
|
|
|
|
static const struct {
|
|
|
|
const char *name;
|
2012-05-04 13:17:28 +08:00
|
|
|
int engine;
|
2015-08-20 12:54:16 +08:00
|
|
|
s32 oclass;
|
2012-05-04 12:01:52 +08:00
|
|
|
int (*exec)(struct nouveau_channel *,
|
|
|
|
struct ttm_buffer_object *,
|
|
|
|
struct ttm_mem_reg *, struct ttm_mem_reg *);
|
|
|
|
int (*init)(struct nouveau_channel *, u32 handle);
|
|
|
|
} _methods[] = {
|
2016-07-09 08:41:01 +08:00
|
|
|
{ "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
|
|
{ "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
2016-07-09 08:41:01 +08:00
|
|
|
{ "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
|
|
{ "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
2015-04-14 09:50:35 +08:00
|
|
|
{ "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
|
|
{ "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
2013-07-09 12:20:15 +08:00
|
|
|
{ "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
2012-08-06 17:38:25 +08:00
|
|
|
{ "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
2012-05-04 13:17:28 +08:00
|
|
|
{ "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
|
|
|
|
{ "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
|
|
|
|
{ "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
|
|
|
|
{ "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
|
|
|
|
{ "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
|
|
|
|
{ "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
|
|
|
|
{ "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
|
2012-05-04 12:34:16 +08:00
|
|
|
{},
|
2012-05-04 13:17:28 +08:00
|
|
|
{ "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
|
2012-05-04 12:01:52 +08:00
|
|
|
}, *mthd = _methods;
|
|
|
|
const char *name = "CPU";
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
do {
|
2012-08-06 17:38:25 +08:00
|
|
|
struct nouveau_channel *chan;
|
2012-07-20 06:17:34 +08:00
|
|
|
|
2013-07-09 12:20:15 +08:00
|
|
|
if (mthd->engine)
|
2012-08-06 17:38:25 +08:00
|
|
|
chan = drm->cechan;
|
|
|
|
else
|
|
|
|
chan = drm->channel;
|
|
|
|
if (chan == NULL)
|
|
|
|
continue;
|
|
|
|
|
2015-08-20 12:54:15 +08:00
|
|
|
ret = nvif_object_init(&chan->user,
|
2014-08-10 02:10:22 +08:00
|
|
|
mthd->oclass | (mthd->engine << 16),
|
|
|
|
mthd->oclass, NULL, 0,
|
|
|
|
&drm->ttm.copy);
|
2012-05-04 12:01:52 +08:00
|
|
|
if (ret == 0) {
|
2014-08-10 02:10:22 +08:00
|
|
|
ret = mthd->init(chan, drm->ttm.copy.handle);
|
2012-07-20 06:17:34 +08:00
|
|
|
if (ret) {
|
2014-08-10 02:10:22 +08:00
|
|
|
nvif_object_fini(&drm->ttm.copy);
|
2012-07-20 06:17:34 +08:00
|
|
|
continue;
|
2012-05-04 12:01:52 +08:00
|
|
|
}
|
2012-07-20 06:17:34 +08:00
|
|
|
|
|
|
|
drm->ttm.move = mthd->exec;
|
2013-07-08 08:40:35 +08:00
|
|
|
drm->ttm.chan = chan;
|
2012-07-20 06:17:34 +08:00
|
|
|
name = mthd->name;
|
|
|
|
break;
|
2012-05-04 12:01:52 +08:00
|
|
|
}
|
|
|
|
} while ((++mthd)->exec);
|
|
|
|
|
2012-07-20 06:17:34 +08:00
|
|
|
NV_INFO(drm, "MM: using %s for buffer copies\n", name);
|
2012-05-04 12:01:52 +08:00
|
|
|
}
|
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
static int
|
|
|
|
nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2014-08-27 19:16:04 +08:00
|
|
|
struct ttm_place placement_memtype = {
|
|
|
|
.fpfn = 0,
|
|
|
|
.lpfn = 0,
|
|
|
|
.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
|
|
|
|
};
|
2009-12-11 17:24:15 +08:00
|
|
|
struct ttm_placement placement;
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg tmp_reg;
|
2009-12-11 17:24:15 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
placement.num_placement = placement.num_busy_placement = 1;
|
2009-12-17 02:05:00 +08:00
|
|
|
placement.placement = placement.busy_placement = &placement_memtype;
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
tmp_reg = *new_reg;
|
|
|
|
tmp_reg.mm_node = NULL;
|
|
|
|
ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = ttm_tt_bind(bo->ttm, &tmp_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
out:
|
2016-05-17 09:13:37 +08:00
|
|
|
ttm_bo_mem_put(bo, &tmp_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2014-08-27 19:16:04 +08:00
|
|
|
struct ttm_place placement_memtype = {
|
|
|
|
.fpfn = 0,
|
|
|
|
.lpfn = 0,
|
|
|
|
.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
|
|
|
|
};
|
2009-12-11 17:24:15 +08:00
|
|
|
struct ttm_placement placement;
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg tmp_reg;
|
2009-12-11 17:24:15 +08:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
placement.num_placement = placement.num_busy_placement = 1;
|
2009-12-17 02:05:00 +08:00
|
|
|
placement.placement = placement.busy_placement = &placement_memtype;
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
tmp_reg = *new_reg;
|
|
|
|
tmp_reg.mm_node = NULL;
|
|
|
|
ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
out:
|
2016-05-17 09:13:37 +08:00
|
|
|
ttm_bo_mem_put(bo, &tmp_reg);
|
2009-12-11 17:24:15 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-02-10 08:35:16 +08:00
|
|
|
static void
|
2016-12-16 00:23:49 +08:00
|
|
|
nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *new_reg)
|
2011-02-10 08:35:16 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
|
2011-02-10 08:35:16 +08:00
|
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_vma *vma;
|
2011-06-06 12:07:04 +08:00
|
|
|
|
drm/ttm: fix two regressions since move_notify changes
Both changes in dc97b3409a790d2a21aac6e5cdb99558b5944119 cause serious
regressions in the nouveau driver.
move_notify() was originally able to presume that bo->mem is the old node,
and new_mem is the new node. The above commit moves the call to
move_notify() to after move() has been done, which means that now, sometimes,
new_mem isn't the new node at all, bo->mem is, and new_mem points at a
stale, possibly-just-been-killed-by-move node.
This is clearly not a good situation. This patch reverts this change, and
replaces it with a cleanup in the move() failure path instead.
The second issue is that the call to move_notify() from cleanup_memtype_use()
causes the TTM ghost objects to get passed into the driver. This is clearly
bad as the driver knows nothing about these "fake" TTM BOs, and ends up
accessing uninitialised memory.
I worked around this in nouveau's move_notify() hook by ensuring the BO
destructor was nouveau's. I don't particularly like this solution, and
would rather TTM never pass the driver these objects. However, I don't
clearly understand the reason why we're calling move_notify() here anyway
and am happy to work around the problem in nouveau instead of breaking the
behaviour expected by other drivers.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Cc: Jerome Glisse <j.glisse@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-25 13:34:22 +08:00
|
|
|
/* ttm can now (stupidly) pass the driver bos it didn't create... */
|
|
|
|
if (bo->destroy != nouveau_bo_del_ttm)
|
|
|
|
return;
|
|
|
|
|
2017-11-01 01:56:19 +08:00
|
|
|
if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
|
2017-11-01 01:56:19 +08:00
|
|
|
mem->mem.page == nvbo->page) {
|
2017-11-01 01:56:19 +08:00
|
|
|
list_for_each_entry(vma, &nvbo->vma_list, head) {
|
2017-11-01 01:56:19 +08:00
|
|
|
nouveau_vma_map(vma, mem);
|
2017-11-01 01:56:19 +08:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
list_for_each_entry(vma, &nvbo->vma_list, head) {
|
2016-12-12 15:52:45 +08:00
|
|
|
WARN_ON(ttm_bo_wait(bo, false, false));
|
2017-11-01 01:56:19 +08:00
|
|
|
nouveau_vma_unmap(vma);
|
2011-06-06 12:07:04 +08:00
|
|
|
}
|
2011-02-10 08:35:16 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
static int
|
2016-05-17 09:13:37 +08:00
|
|
|
nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg,
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm_tile **new_tile)
|
2009-12-11 17:24:15 +08:00
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
|
|
struct drm_device *dev = drm->dev;
|
2009-12-11 23:51:09 +08:00
|
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
2016-05-17 09:13:37 +08:00
|
|
|
u64 offset = new_reg->start << PAGE_SHIFT;
|
2009-12-11 17:24:15 +08:00
|
|
|
|
2011-02-10 08:35:16 +08:00
|
|
|
*new_tile = NULL;
|
2016-05-17 09:13:37 +08:00
|
|
|
if (new_reg->mem_type != TTM_PL_VRAM)
|
2009-12-11 23:51:09 +08:00
|
|
|
return 0;
|
|
|
|
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
|
2016-05-17 09:13:37 +08:00
|
|
|
*new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
|
2017-11-01 01:56:19 +08:00
|
|
|
nvbo->mode, nvbo->zeta);
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2009-12-11 23:51:09 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm_tile *new_tile,
|
|
|
|
struct nouveau_drm_tile **old_tile)
|
2009-12-11 23:51:09 +08:00
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
|
|
struct drm_device *dev = drm->dev;
|
2016-10-25 20:00:45 +08:00
|
|
|
struct dma_fence *fence = reservation_object_get_excl(bo->resv);
|
2009-12-11 23:51:09 +08:00
|
|
|
|
2014-04-02 23:14:48 +08:00
|
|
|
nv10_bo_put_tile_region(dev, *old_tile, fence);
|
2011-02-10 08:35:16 +08:00
|
|
|
*old_tile = new_tile;
|
2009-12-11 23:51:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
2009-12-11 23:51:09 +08:00
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
2009-12-11 23:51:09 +08:00
|
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_reg *old_reg = &bo->mem;
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm_tile *new_tile = NULL;
|
2009-12-11 23:51:09 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
2016-06-06 16:17:53 +08:00
|
|
|
ret = ttm_bo_wait(bo, intr, no_wait_gpu);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2014-10-27 17:11:52 +08:00
|
|
|
if (nvbo->pin_refcnt)
|
|
|
|
NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
|
|
|
|
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
|
2011-02-10 08:35:16 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2009-12-11 23:51:09 +08:00
|
|
|
|
|
|
|
/* Fake bo copy. */
|
2016-05-17 09:13:37 +08:00
|
|
|
if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
|
2009-12-11 17:24:15 +08:00
|
|
|
BUG_ON(bo->mem.mm_node != NULL);
|
2016-05-17 09:13:37 +08:00
|
|
|
bo->mem = *new_reg;
|
|
|
|
new_reg->mm_node = NULL;
|
2009-12-11 23:51:09 +08:00
|
|
|
goto out;
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2009-12-11 23:51:09 +08:00
|
|
|
/* Hardware assisted copy. */
|
2013-11-22 08:52:54 +08:00
|
|
|
if (drm->ttm.move) {
|
2016-05-17 09:13:37 +08:00
|
|
|
if (new_reg->mem_type == TTM_PL_SYSTEM)
|
2013-11-22 08:52:54 +08:00
|
|
|
ret = nouveau_bo_move_flipd(bo, evict, intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
no_wait_gpu, new_reg);
|
|
|
|
else if (old_reg->mem_type == TTM_PL_SYSTEM)
|
2013-11-22 08:52:54 +08:00
|
|
|
ret = nouveau_bo_move_flips(bo, evict, intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
no_wait_gpu, new_reg);
|
2013-11-22 08:52:54 +08:00
|
|
|
else
|
|
|
|
ret = nouveau_bo_move_m2mf(bo, evict, intr,
|
2016-05-17 09:13:37 +08:00
|
|
|
no_wait_gpu, new_reg);
|
2013-11-22 08:52:54 +08:00
|
|
|
if (!ret)
|
|
|
|
goto out;
|
|
|
|
}
|
2009-12-11 23:51:09 +08:00
|
|
|
|
|
|
|
/* Fallback to software copy. */
|
2016-04-06 17:12:04 +08:00
|
|
|
ret = ttm_bo_wait(bo, intr, no_wait_gpu);
|
2013-11-22 08:52:54 +08:00
|
|
|
if (ret == 0)
|
2016-05-17 09:13:37 +08:00
|
|
|
ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg);
|
2009-12-11 23:51:09 +08:00
|
|
|
|
|
|
|
out:
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
|
2011-02-10 08:35:16 +08:00
|
|
|
if (ret)
|
|
|
|
nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
|
|
|
|
else
|
|
|
|
nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
|
|
|
|
}
|
2009-12-11 23:51:09 +08:00
|
|
|
|
|
|
|
return ret;
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
|
|
|
{
|
2013-08-26 00:28:59 +08:00
|
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
|
2016-09-01 20:48:33 +08:00
|
|
|
return drm_vma_node_verify_access(&nvbo->gem.vma_node,
|
|
|
|
filp->private_data);
|
2009-12-11 17:24:15 +08:00
|
|
|
}
|
|
|
|
|
2010-04-09 20:39:25 +08:00
|
|
|
static int
|
2016-05-17 09:13:37 +08:00
|
|
|
nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
|
2010-04-09 20:39:25 +08:00
|
|
|
{
|
2016-05-17 09:13:37 +08:00
|
|
|
struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type];
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
2016-05-18 11:57:42 +08:00
|
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(reg);
|
2010-11-15 09:53:16 +08:00
|
|
|
int ret;
|
2010-04-09 20:39:25 +08:00
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
reg->bus.addr = NULL;
|
|
|
|
reg->bus.offset = 0;
|
|
|
|
reg->bus.size = reg->num_pages << PAGE_SHIFT;
|
|
|
|
reg->bus.base = 0;
|
|
|
|
reg->bus.is_iomem = false;
|
2010-04-09 20:39:25 +08:00
|
|
|
if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
|
|
|
|
return -EINVAL;
|
2016-05-17 09:13:37 +08:00
|
|
|
switch (reg->mem_type) {
|
2010-04-09 20:39:25 +08:00
|
|
|
case TTM_PL_SYSTEM:
|
|
|
|
/* System memory */
|
|
|
|
return 0;
|
|
|
|
case TTM_PL_TT:
|
2015-09-09 22:45:52 +08:00
|
|
|
#if IS_ENABLED(CONFIG_AGP)
|
2015-08-20 12:54:23 +08:00
|
|
|
if (drm->agp.bridge) {
|
2016-05-17 09:13:37 +08:00
|
|
|
reg->bus.offset = reg->start << PAGE_SHIFT;
|
|
|
|
reg->bus.base = drm->agp.base;
|
|
|
|
reg->bus.is_iomem = !drm->agp.cma;
|
2010-04-09 20:39:25 +08:00
|
|
|
}
|
|
|
|
#endif
|
2017-11-01 01:56:19 +08:00
|
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || !mem->kind)
|
2013-11-12 20:34:09 +08:00
|
|
|
/* untiled */
|
|
|
|
break;
|
|
|
|
/* fallthrough, tiled memory */
|
2010-04-09 20:39:25 +08:00
|
|
|
case TTM_PL_VRAM:
|
2016-05-17 09:13:37 +08:00
|
|
|
reg->bus.offset = reg->start << PAGE_SHIFT;
|
|
|
|
reg->bus.base = device->func->resource_addr(device, 1);
|
|
|
|
reg->bus.is_iomem = true;
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nvkm_vmm *bar = nvkm_bar_bar1_vmm(device);
|
2015-08-20 12:54:17 +08:00
|
|
|
int page_shift = 12;
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
|
2017-11-01 01:56:19 +08:00
|
|
|
page_shift = mem->mem.page;
|
2010-11-15 09:48:33 +08:00
|
|
|
|
2017-11-01 01:56:19 +08:00
|
|
|
ret = nvkm_vm_get(bar, mem->_mem->size << 12,
|
|
|
|
page_shift, NV_MEM_ACCESS_RW,
|
|
|
|
&mem->bar_vma);
|
2012-07-14 17:09:17 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-11-15 09:53:16 +08:00
|
|
|
|
2017-11-01 01:56:19 +08:00
|
|
|
nvkm_vm_map(&mem->bar_vma, mem->_mem);
|
2016-05-17 09:13:37 +08:00
|
|
|
reg->bus.offset = mem->bar_vma.offset;
|
2010-11-15 09:53:16 +08:00
|
|
|
}
|
2010-04-09 20:39:25 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-05-17 09:13:37 +08:00
|
|
|
nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
|
2010-04-09 20:39:25 +08:00
|
|
|
{
|
2017-11-01 01:56:19 +08:00
|
|
|
struct nouveau_mem *mem = nouveau_mem(reg);
|
2010-11-15 09:53:16 +08:00
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
if (!mem->bar_vma.node)
|
2010-11-15 09:53:16 +08:00
|
|
|
return;
|
|
|
|
|
2016-05-17 09:13:37 +08:00
|
|
|
nvkm_vm_unmap(&mem->bar_vma);
|
|
|
|
nvkm_vm_put(&mem->bar_vma);
|
2010-04-09 20:39:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
|
|
{
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
2010-09-10 09:12:25 +08:00
|
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
2016-05-18 11:57:42 +08:00
|
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
2015-08-20 12:54:23 +08:00
|
|
|
u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
|
2014-08-27 19:16:04 +08:00
|
|
|
int i, ret;
|
2010-09-10 09:12:25 +08:00
|
|
|
|
|
|
|
/* as long as the bo isn't in vram, and isn't tiled, we've got
|
|
|
|
* nothing to do here.
|
|
|
|
*/
|
|
|
|
if (bo->mem.mem_type != TTM_PL_VRAM) {
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
|
2017-11-01 01:56:19 +08:00
|
|
|
!nvbo->kind)
|
2010-09-10 09:12:25 +08:00
|
|
|
return 0;
|
2013-11-12 20:34:09 +08:00
|
|
|
|
|
|
|
if (bo->mem.mem_type == TTM_PL_SYSTEM) {
|
|
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
|
|
|
|
|
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
return 0;
|
2010-09-10 09:12:25 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* make sure bo is in mappable vram */
|
2016-05-18 11:57:42 +08:00
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
|
2013-11-12 20:34:09 +08:00
|
|
|
bo->mem.start + bo->mem.num_pages < mappable)
|
2010-09-10 09:12:25 +08:00
|
|
|
return 0;
|
|
|
|
|
2014-08-27 19:16:04 +08:00
|
|
|
for (i = 0; i < nvbo->placement.num_placement; ++i) {
|
|
|
|
nvbo->placements[i].fpfn = 0;
|
|
|
|
nvbo->placements[i].lpfn = mappable;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
|
|
|
|
nvbo->busy_placements[i].fpfn = 0;
|
|
|
|
nvbo->busy_placements[i].lpfn = mappable;
|
|
|
|
}
|
2010-09-10 09:12:25 +08:00
|
|
|
|
2012-05-18 22:31:12 +08:00
|
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
|
2012-11-28 19:25:44 +08:00
|
|
|
return nouveau_bo_validate(nvbo, false, false);
|
2010-04-09 20:39:25 +08:00
|
|
|
}
|
|
|
|
|
2011-10-18 05:14:26 +08:00
|
|
|
static int
|
|
|
|
nouveau_ttm_tt_populate(struct ttm_tt *ttm)
|
|
|
|
{
|
2011-11-10 06:15:26 +08:00
|
|
|
struct ttm_dma_tt *ttm_dma = (void *)ttm;
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm;
|
2015-01-14 13:36:34 +08:00
|
|
|
struct nvkm_device *device;
|
2011-10-18 05:14:26 +08:00
|
|
|
struct drm_device *dev;
|
2014-07-31 17:09:42 +08:00
|
|
|
struct device *pdev;
|
2011-10-18 05:14:26 +08:00
|
|
|
unsigned i;
|
|
|
|
int r;
|
2012-04-02 18:53:06 +08:00
|
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
2011-10-18 05:14:26 +08:00
|
|
|
|
|
|
|
if (ttm->state != tt_unpopulated)
|
|
|
|
return 0;
|
|
|
|
|
2012-04-02 18:53:06 +08:00
|
|
|
if (slave && ttm->sg) {
|
|
|
|
/* make userspace faulting work */
|
|
|
|
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
|
|
|
|
ttm_dma->dma_address, ttm->num_pages);
|
|
|
|
ttm->state = tt_unbound;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-20 06:17:34 +08:00
|
|
|
drm = nouveau_bdev(ttm->bdev);
|
2016-05-18 11:57:42 +08:00
|
|
|
device = nvxx_device(&drm->client.device);
|
2012-07-20 06:17:34 +08:00
|
|
|
dev = drm->dev;
|
2015-08-20 12:54:23 +08:00
|
|
|
pdev = device->dev;
|
2011-10-18 05:14:26 +08:00
|
|
|
|
2015-09-09 22:45:52 +08:00
|
|
|
#if IS_ENABLED(CONFIG_AGP)
|
2015-08-20 12:54:23 +08:00
|
|
|
if (drm->agp.bridge) {
|
2012-01-04 06:37:37 +08:00
|
|
|
return ttm_agp_tt_populate(ttm);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-03-02 18:12:27 +08:00
|
|
|
#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
|
2011-10-18 05:14:26 +08:00
|
|
|
if (swiotlb_nr_tbl()) {
|
2011-11-10 06:15:26 +08:00
|
|
|
return ttm_dma_populate((void *)ttm, dev->dev);
|
2011-10-18 05:14:26 +08:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
r = ttm_pool_populate(ttm);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
2014-07-31 17:09:42 +08:00
|
|
|
dma_addr_t addr;
|
|
|
|
|
|
|
|
addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
|
|
|
|
if (dma_mapping_error(pdev, addr)) {
|
2016-02-16 02:41:46 +08:00
|
|
|
while (i--) {
|
2014-07-31 17:09:42 +08:00
|
|
|
dma_unmap_page(pdev, ttm_dma->dma_address[i],
|
|
|
|
PAGE_SIZE, DMA_BIDIRECTIONAL);
|
2011-11-10 06:15:26 +08:00
|
|
|
ttm_dma->dma_address[i] = 0;
|
2011-10-18 05:14:26 +08:00
|
|
|
}
|
|
|
|
ttm_pool_unpopulate(ttm);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
2014-07-31 17:09:42 +08:00
|
|
|
|
|
|
|
ttm_dma->dma_address[i] = addr;
|
2011-10-18 05:14:26 +08:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
|
|
|
{
|
2011-11-10 06:15:26 +08:00
|
|
|
struct ttm_dma_tt *ttm_dma = (void *)ttm;
|
2012-07-20 06:17:34 +08:00
|
|
|
struct nouveau_drm *drm;
|
2015-01-14 13:36:34 +08:00
|
|
|
struct nvkm_device *device;
|
2011-10-18 05:14:26 +08:00
|
|
|
struct drm_device *dev;
|
2014-07-31 17:09:42 +08:00
|
|
|
struct device *pdev;
|
2011-10-18 05:14:26 +08:00
|
|
|
unsigned i;
|
2012-04-02 18:53:06 +08:00
|
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
|
|
|
|
if (slave)
|
|
|
|
return;
|
2011-10-18 05:14:26 +08:00
|
|
|
|
2012-07-20 06:17:34 +08:00
|
|
|
drm = nouveau_bdev(ttm->bdev);
|
2016-05-18 11:57:42 +08:00
|
|
|
device = nvxx_device(&drm->client.device);
|
2012-07-20 06:17:34 +08:00
|
|
|
dev = drm->dev;
|
2015-08-20 12:54:23 +08:00
|
|
|
pdev = device->dev;
|
2011-10-18 05:14:26 +08:00
|
|
|
|
2015-09-09 22:45:52 +08:00
|
|
|
#if IS_ENABLED(CONFIG_AGP)
|
2015-08-20 12:54:23 +08:00
|
|
|
if (drm->agp.bridge) {
|
2012-01-04 06:37:37 +08:00
|
|
|
ttm_agp_tt_unpopulate(ttm);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-03-02 18:12:27 +08:00
|
|
|
#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
|
2011-10-18 05:14:26 +08:00
|
|
|
if (swiotlb_nr_tbl()) {
|
2011-11-10 06:15:26 +08:00
|
|
|
ttm_dma_unpopulate((void *)ttm, dev->dev);
|
2011-10-18 05:14:26 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
2011-11-10 06:15:26 +08:00
|
|
|
if (ttm_dma->dma_address[i]) {
|
2014-07-31 17:09:42 +08:00
|
|
|
dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
|
|
|
|
DMA_BIDIRECTIONAL);
|
2011-10-18 05:14:26 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ttm_pool_unpopulate(ttm);
|
|
|
|
}
|
|
|
|
|
2012-04-30 10:51:48 +08:00
|
|
|
void
|
2014-04-09 22:19:30 +08:00
|
|
|
nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
|
2012-04-30 10:51:48 +08:00
|
|
|
{
|
2014-01-09 18:03:11 +08:00
|
|
|
struct reservation_object *resv = nvbo->bo.resv;
|
2014-01-21 20:02:14 +08:00
|
|
|
|
2014-04-09 22:19:30 +08:00
|
|
|
if (exclusive)
|
|
|
|
reservation_object_add_excl_fence(resv, &fence->base);
|
|
|
|
else if (fence)
|
|
|
|
reservation_object_add_shared_fence(resv, &fence->base);
|
2012-04-30 10:51:48 +08:00
|
|
|
}
|
|
|
|
|
2009-12-11 17:24:15 +08:00
|
|
|
struct ttm_bo_driver nouveau_bo_driver = {
|
2011-11-02 08:46:13 +08:00
|
|
|
.ttm_tt_create = &nouveau_ttm_tt_create,
|
2011-10-18 05:14:26 +08:00
|
|
|
.ttm_tt_populate = &nouveau_ttm_tt_populate,
|
|
|
|
.ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
|
2009-12-11 17:24:15 +08:00
|
|
|
.invalidate_caches = nouveau_bo_invalidate_caches,
|
|
|
|
.init_mem_type = nouveau_bo_init_mem_type,
|
2016-08-30 23:26:04 +08:00
|
|
|
.eviction_valuable = ttm_bo_eviction_valuable,
|
2009-12-11 17:24:15 +08:00
|
|
|
.evict_flags = nouveau_bo_evict_flags,
|
2011-02-10 08:35:16 +08:00
|
|
|
.move_notify = nouveau_bo_move_ntfy,
|
2009-12-11 17:24:15 +08:00
|
|
|
.move = nouveau_bo_move,
|
|
|
|
.verify_access = nouveau_bo_verify_access,
|
2010-04-09 20:39:25 +08:00
|
|
|
.fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
|
|
|
|
.io_mem_reserve = &nouveau_ttm_io_mem_reserve,
|
|
|
|
.io_mem_free = &nouveau_ttm_io_mem_free,
|
2017-03-28 22:54:50 +08:00
|
|
|
.io_mem_pfn = ttm_bo_default_io_mem_pfn,
|
2009-12-11 17:24:15 +08:00
|
|
|
};
|