usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* core.c - DesignWare USB3 DRD Controller Core file
|
|
|
|
*
|
|
|
|
* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
|
|
|
|
*
|
|
|
|
* Authors: Felipe Balbi <balbi@ti.com>,
|
|
|
|
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
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|
|
|
* are met:
|
|
|
|
* 1. Redistributions of source code must retain the above copyright
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|
|
|
* notice, this list of conditions, and the following disclaimer,
|
|
|
|
* without modification.
|
|
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
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|
|
|
* 3. The names of the above-listed copyright holders may not be used
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|
|
* to endorse or promote products derived from this software without
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|
|
* specific prior written permission.
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|
|
*
|
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|
|
* ALTERNATIVELY, this software may be distributed under the terms of the
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|
|
|
* GNU General Public License ("GPL") version 2, as published by the Free
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|
|
|
* Software Foundation.
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|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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|
|
* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
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|
|
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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|
|
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
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|
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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|
2011-09-05 18:37:28 +08:00
|
|
|
#include <linux/module.h>
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/slab.h>
|
|
|
|
#include <linux/spinlock.h>
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/pm_runtime.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/ioport.h>
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include <linux/list.h>
|
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/dma-mapping.h>
|
2012-01-19 00:04:09 +08:00
|
|
|
#include <linux/of.h>
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
#include <linux/usb/ch9.h>
|
|
|
|
#include <linux/usb/gadget.h>
|
|
|
|
|
|
|
|
#include "core.h"
|
|
|
|
#include "gadget.h"
|
|
|
|
#include "io.h"
|
|
|
|
|
|
|
|
#include "debug.h"
|
|
|
|
|
2011-10-08 03:55:04 +08:00
|
|
|
static char *maximum_speed = "super";
|
|
|
|
module_param(maximum_speed, charp, 0);
|
|
|
|
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
|
|
|
|
|
2011-10-18 18:54:01 +08:00
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
#define DWC3_DEVS_POSSIBLE 32
|
|
|
|
|
|
|
|
static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
|
|
|
|
|
|
|
|
int dwc3_get_device_id(void)
|
|
|
|
{
|
|
|
|
int id;
|
|
|
|
|
|
|
|
again:
|
|
|
|
id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
|
|
|
|
if (id < DWC3_DEVS_POSSIBLE) {
|
|
|
|
int old;
|
|
|
|
|
|
|
|
old = test_and_set_bit(id, dwc3_devs);
|
|
|
|
if (old)
|
|
|
|
goto again;
|
|
|
|
} else {
|
|
|
|
pr_err("dwc3: no space for new device\n");
|
|
|
|
id = -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2012-02-04 21:37:14 +08:00
|
|
|
return id;
|
2011-10-18 18:54:01 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(dwc3_get_device_id);
|
|
|
|
|
|
|
|
void dwc3_put_device_id(int id)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (id < 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
ret = test_bit(id, dwc3_devs);
|
|
|
|
WARN(!ret, "dwc3: ID %d not in use\n", id);
|
|
|
|
clear_bit(id, dwc3_devs);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(dwc3_put_device_id);
|
|
|
|
|
2011-11-01 05:25:40 +08:00
|
|
|
void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
|
|
reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
|
|
|
|
reg |= DWC3_GCTL_PRTCAPDIR(mode);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
}
|
2011-10-18 18:54:01 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
|
|
|
|
* @dwc: pointer to our context structure
|
|
|
|
*/
|
|
|
|
static void dwc3_core_soft_reset(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
/* Before Resetting PHY, put Core in Reset */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
|
|
reg |= DWC3_GCTL_CORESOFTRESET;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
|
|
|
|
/* Assert USB3 PHY reset */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
|
|
|
|
/* Assert USB2 PHY reset */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
|
|
|
|
mdelay(100);
|
|
|
|
|
|
|
|
/* Clear USB3 PHY reset */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
|
|
|
|
/* Clear USB2 PHY reset */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
|
2012-06-21 20:14:28 +08:00
|
|
|
mdelay(100);
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/* After PHYs are stable we can take Core out of reset state */
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
|
|
reg &= ~DWC3_GCTL_CORESOFTRESET;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_free_one_event_buffer - Frees one event buffer
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
* @evt: Pointer to event buffer to be freed
|
|
|
|
*/
|
|
|
|
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
|
|
|
|
struct dwc3_event_buffer *evt)
|
|
|
|
{
|
|
|
|
dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
|
|
|
|
kfree(evt);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2012-02-16 10:56:56 +08:00
|
|
|
* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
* @length: size of the event buffer
|
|
|
|
*
|
2012-02-16 10:56:56 +08:00
|
|
|
* Returns a pointer to the allocated event buffer structure on success
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* otherwise ERR_PTR(errno).
|
|
|
|
*/
|
|
|
|
static struct dwc3_event_buffer *__devinit
|
|
|
|
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
|
|
|
evt = kzalloc(sizeof(*evt), GFP_KERNEL);
|
|
|
|
if (!evt)
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
|
|
|
evt->dwc = dwc;
|
|
|
|
evt->length = length;
|
|
|
|
evt->buf = dma_alloc_coherent(dwc->dev, length,
|
|
|
|
&evt->dma, GFP_KERNEL);
|
|
|
|
if (!evt->buf) {
|
|
|
|
kfree(evt);
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
return evt;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_free_event_buffers - frees all allocated event buffers
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*/
|
|
|
|
static void dwc3_free_event_buffers(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
int i;
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
for (i = 0; i < dwc->num_event_buffers; i++) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
evt = dwc->ev_buffs[i];
|
2012-03-06 16:05:15 +08:00
|
|
|
if (evt)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_free_one_event_buffer(dwc, evt);
|
|
|
|
}
|
2012-03-06 16:05:15 +08:00
|
|
|
|
|
|
|
kfree(dwc->ev_buffs);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
|
2012-02-16 10:56:56 +08:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* @length: size of event buffer
|
|
|
|
*
|
2012-02-16 10:56:56 +08:00
|
|
|
* Returns 0 on success otherwise negative errno. In the error case, dwc
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
* may contain some buffers allocated but not all which were requested.
|
|
|
|
*/
|
2011-10-12 15:31:04 +08:00
|
|
|
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
2011-10-12 15:31:04 +08:00
|
|
|
int num;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
int i;
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
|
|
|
|
dwc->num_event_buffers = num;
|
|
|
|
|
2011-10-24 17:03:13 +08:00
|
|
|
dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
|
|
|
|
if (!dwc->ev_buffs) {
|
|
|
|
dev_err(dwc->dev, "can't allocate event buffers array\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
|
|
|
|
evt = dwc3_alloc_one_event_buffer(dwc, length);
|
|
|
|
if (IS_ERR(evt)) {
|
|
|
|
dev_err(dwc->dev, "can't allocate event buffer\n");
|
|
|
|
return PTR_ERR(evt);
|
|
|
|
}
|
|
|
|
dwc->ev_buffs[i] = evt;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dwc3_event_buffers_setup - setup our allocated event buffers
|
2012-02-16 10:56:56 +08:00
|
|
|
* @dwc: pointer to our controller context structure
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
2012-04-27 19:28:02 +08:00
|
|
|
static int dwc3_event_buffers_setup(struct dwc3 *dwc)
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
int n;
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
for (n = 0; n < dwc->num_event_buffers; n++) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
evt = dwc->ev_buffs[n];
|
|
|
|
dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
|
|
|
|
evt->buf, (unsigned long long) evt->dma,
|
|
|
|
evt->length);
|
|
|
|
|
2012-04-27 19:28:02 +08:00
|
|
|
evt->lpos = 0;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
|
|
|
|
lower_32_bits(evt->dma));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
|
|
|
|
upper_32_bits(evt->dma));
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
|
|
|
|
evt->length & 0xffff);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_event_buffer *evt;
|
|
|
|
int n;
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
for (n = 0; n < dwc->num_event_buffers; n++) {
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
evt = dwc->ev_buffs[n];
|
2012-04-27 19:28:02 +08:00
|
|
|
|
|
|
|
evt->lpos = 0;
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-09-30 15:58:49 +08:00
|
|
|
static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
|
|
|
|
parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
|
|
|
|
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
|
|
|
|
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
|
|
|
|
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
|
|
|
|
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
|
|
|
|
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
|
|
|
|
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
|
|
|
|
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
|
|
|
|
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
|
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
/**
|
|
|
|
* dwc3_core_init - Low-level initialization of DWC3 Core
|
|
|
|
* @dwc: Pointer to our controller context structure
|
|
|
|
*
|
|
|
|
* Returns 0 on success otherwise negative errno.
|
|
|
|
*/
|
|
|
|
static int __devinit dwc3_core_init(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
unsigned long timeout;
|
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
2011-08-29 19:56:36 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
|
|
|
|
/* This should read as U3 followed by revision number */
|
|
|
|
if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
|
|
|
|
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto err0;
|
|
|
|
}
|
2011-12-15 03:59:30 +08:00
|
|
|
dwc->revision = reg;
|
2011-08-29 19:56:36 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_core_soft_reset(dwc);
|
|
|
|
|
|
|
|
/* issue device SoftReset too */
|
|
|
|
timeout = jiffies + msecs_to_jiffies(500);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
|
|
|
|
do {
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
if (!(reg & DWC3_DCTL_CSFTRST))
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (time_after(jiffies, timeout)) {
|
|
|
|
dev_err(dwc->dev, "Reset Timed Out\n");
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto err0;
|
|
|
|
}
|
|
|
|
|
|
|
|
cpu_relax();
|
|
|
|
} while (true);
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
dwc3_cache_hwparams(dwc);
|
|
|
|
|
2011-11-01 05:25:41 +08:00
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
2012-02-25 09:32:13 +08:00
|
|
|
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
|
2011-11-01 05:25:41 +08:00
|
|
|
reg &= ~DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
|
2011-11-24 18:22:05 +08:00
|
|
|
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
|
2011-11-01 05:25:41 +08:00
|
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
|
|
|
|
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_dbg(dwc->dev, "No power optimization available\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* WORKAROUND: DWC3 revisions <1.90a have a bug
|
2012-02-16 10:56:56 +08:00
|
|
|
* where the device can fail to connect at SuperSpeed
|
2011-11-01 05:25:41 +08:00
|
|
|
* and falls back to high-speed mode which causes
|
2012-02-16 10:56:56 +08:00
|
|
|
* the device to enter a Connect/Disconnect loop
|
2011-11-01 05:25:41 +08:00
|
|
|
*/
|
|
|
|
if (dwc->revision < DWC3_REVISION_190A)
|
|
|
|
reg |= DWC3_GCTL_U2RSTECN;
|
|
|
|
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
|
|
|
2011-10-12 15:31:04 +08:00
|
|
|
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to allocate event buffers\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = dwc3_event_buffers_setup(dwc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dwc->dev, "failed to setup event buffers\n");
|
|
|
|
goto err1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err1:
|
|
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
|
|
|
|
err0:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_core_exit(struct dwc3 *dwc)
|
|
|
|
{
|
|
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DWC3_ALIGN_MASK (16 - 1)
|
|
|
|
|
|
|
|
static int __devinit dwc3_probe(struct platform_device *pdev)
|
|
|
|
{
|
2012-01-19 00:04:09 +08:00
|
|
|
struct device_node *node = pdev->dev.of_node;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
struct resource *res;
|
|
|
|
struct dwc3 *dwc;
|
2012-02-15 17:27:55 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
2011-10-12 15:44:56 +08:00
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
int ret = -ENOMEM;
|
2011-10-12 15:44:56 +08:00
|
|
|
|
|
|
|
void __iomem *regs;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
void *mem;
|
|
|
|
|
2011-10-12 15:44:56 +08:00
|
|
|
u8 mode;
|
|
|
|
|
2012-02-15 17:27:55 +08:00
|
|
|
mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (!mem) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "not enough memory\n");
|
|
|
|
return -ENOMEM;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
|
|
|
|
dwc->mem = mem;
|
|
|
|
|
2012-04-24 19:18:39 +08:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (!res) {
|
2012-04-24 19:18:39 +08:00
|
|
|
dev_err(dev, "missing IRQ\n");
|
2012-02-15 17:27:55 +08:00
|
|
|
return -ENODEV;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
2012-04-24 19:18:39 +08:00
|
|
|
dwc->xhci_resources[1] = *res;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2012-04-24 19:18:39 +08:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!res) {
|
|
|
|
dev_err(dev, "missing memory resource\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
dwc->xhci_resources[0] = *res;
|
|
|
|
dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
|
|
|
|
DWC3_XHCI_REGS_END;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Request memory region but exclude xHCI regs,
|
|
|
|
* since it will be requested by the xhci-plat driver.
|
|
|
|
*/
|
|
|
|
res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
|
|
|
|
resource_size(res) - DWC3_GLOBALS_REGS_START,
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_name(dev));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (!res) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "can't request mem region\n");
|
|
|
|
return -ENOMEM;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2012-02-15 17:27:55 +08:00
|
|
|
regs = devm_ioremap(dev, res->start, resource_size(res));
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
if (!regs) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "ioremap failed\n");
|
|
|
|
return -ENOMEM;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_init(&dwc->lock);
|
|
|
|
platform_set_drvdata(pdev, dwc);
|
|
|
|
|
|
|
|
dwc->regs = regs;
|
|
|
|
dwc->regs_size = resource_size(res);
|
2012-02-15 17:27:55 +08:00
|
|
|
dwc->dev = dev;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
2011-10-08 03:55:04 +08:00
|
|
|
if (!strncmp("super", maximum_speed, 5))
|
|
|
|
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
|
|
|
|
else if (!strncmp("high", maximum_speed, 4))
|
|
|
|
dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
|
|
|
|
else if (!strncmp("full", maximum_speed, 4))
|
|
|
|
dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
|
|
|
|
else if (!strncmp("low", maximum_speed, 3))
|
|
|
|
dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
|
|
|
|
else
|
|
|
|
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
|
|
|
|
|
2012-01-19 00:04:09 +08:00
|
|
|
if (of_get_property(node, "tx-fifo-resize", NULL))
|
|
|
|
dwc->needs_fifo_resize = true;
|
|
|
|
|
2012-02-15 17:27:55 +08:00
|
|
|
pm_runtime_enable(dev);
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
pm_runtime_forbid(dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize core\n");
|
|
|
|
return ret;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2011-10-12 15:44:56 +08:00
|
|
|
mode = DWC3_MODE(dwc->hwparams.hwparams0);
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case DWC3_MODE_DEVICE:
|
2011-11-01 05:25:40 +08:00
|
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
|
|
goto err1;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
2011-10-12 19:08:26 +08:00
|
|
|
break;
|
|
|
|
case DWC3_MODE_HOST:
|
2011-11-01 05:25:40 +08:00
|
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
|
2011-10-12 19:08:26 +08:00
|
|
|
ret = dwc3_host_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize host\n");
|
|
|
|
goto err1;
|
2011-10-12 19:08:26 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DWC3_MODE_DRD:
|
2011-11-01 05:25:40 +08:00
|
|
|
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
|
2011-10-12 19:08:26 +08:00
|
|
|
ret = dwc3_host_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize host\n");
|
|
|
|
goto err1;
|
2011-10-12 19:08:26 +08:00
|
|
|
}
|
|
|
|
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
|
|
goto err1;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
2011-10-12 15:44:56 +08:00
|
|
|
break;
|
|
|
|
default:
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "Unsupported mode of operation %d\n", mode);
|
|
|
|
goto err1;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
2011-10-12 15:44:56 +08:00
|
|
|
dwc->mode = mode;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
ret = dwc3_debugfs_init(dwc);
|
|
|
|
if (ret) {
|
2012-02-15 17:27:55 +08:00
|
|
|
dev_err(dev, "failed to initialize debugfs\n");
|
|
|
|
goto err2;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
}
|
|
|
|
|
2012-02-15 17:27:55 +08:00
|
|
|
pm_runtime_allow(dev);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2012-02-15 17:27:55 +08:00
|
|
|
err2:
|
2011-10-12 15:44:56 +08:00
|
|
|
switch (mode) {
|
|
|
|
case DWC3_MODE_DEVICE:
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_exit(dwc);
|
2011-10-12 15:44:56 +08:00
|
|
|
break;
|
2011-10-12 19:08:26 +08:00
|
|
|
case DWC3_MODE_HOST:
|
|
|
|
dwc3_host_exit(dwc);
|
|
|
|
break;
|
|
|
|
case DWC3_MODE_DRD:
|
|
|
|
dwc3_host_exit(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_exit(dwc);
|
2011-10-12 19:08:26 +08:00
|
|
|
break;
|
2011-10-12 15:44:56 +08:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
err1:
|
2012-02-15 17:27:55 +08:00
|
|
|
dwc3_core_exit(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devexit dwc3_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct dwc3 *dwc = platform_get_drvdata(pdev);
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
|
|
|
dwc3_debugfs_exit(dwc);
|
|
|
|
|
2011-10-12 15:44:56 +08:00
|
|
|
switch (dwc->mode) {
|
|
|
|
case DWC3_MODE_DEVICE:
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_exit(dwc);
|
2011-10-12 15:44:56 +08:00
|
|
|
break;
|
2011-10-12 19:08:26 +08:00
|
|
|
case DWC3_MODE_HOST:
|
|
|
|
dwc3_host_exit(dwc);
|
|
|
|
break;
|
|
|
|
case DWC3_MODE_DRD:
|
|
|
|
dwc3_host_exit(dwc);
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
dwc3_gadget_exit(dwc);
|
2011-10-12 19:08:26 +08:00
|
|
|
break;
|
2011-10-12 15:44:56 +08:00
|
|
|
default:
|
|
|
|
/* do nothing */
|
|
|
|
break;
|
|
|
|
}
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
|
|
|
|
dwc3_core_exit(dwc);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver dwc3_driver = {
|
|
|
|
.probe = dwc3_probe,
|
|
|
|
.remove = __devexit_p(dwc3_remove),
|
|
|
|
.driver = {
|
|
|
|
.name = "dwc3",
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-02-28 19:57:20 +08:00
|
|
|
module_platform_driver(dwc3_driver);
|
|
|
|
|
2011-10-20 01:39:50 +08:00
|
|
|
MODULE_ALIAS("platform:dwc3");
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 23:10:58 +08:00
|
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
|
|
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
|