linux-next/drivers/clk/rockchip/Makefile

#
# Rockchip Clock specific Makefile
#

obj-y	+= clk-rockchip.o
obj-y	+= clk.o
obj-y	+= clk-pll.o
obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o
clk: add support for Rockchip gate clocks This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2013-06-13 22:59:40 +08:00			`#`
			`# Rockchip Clock specific Makefile`
			`#`

			`obj-y += clk-rockchip.o`
clk: rockchip: add basic infrastructure for clock branches This adds infrastructure for registering clock branches. On Rockchip SoCs most clock branches are a combination of mux,divider and gate components, thus a composite clock is used when appropriate. Clock branches are supposed to be declared in an array using the COMPOSITE* or MUX, etc makros defined in the header and then registered using rockchip_clk_register_branches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-07-03 07:58:39 +08:00			`obj-y += clk.o`
clk: rockchip: add clock type for pll clocks and pll used on rk3066 All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to handle their plls: \|--\ xin32k ----------------\|mux\ xin24m -----\| pll \|----\|pll\|--- pll output \---------------\|src/ \|--/ The pll output is sourced from 1 of 3 sources, the actual pll being one of them. To change the pll frequency it is imperative to remux it to another source beforehand. This is done by adding a clock-listener to the pll that handles the remuxing before and after the rate change. The output mux is implemented as a separate clock to make use of already existing common-clock features for disabling the pll if one of the other two sources is used. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-07-03 07:59:10 +08:00			`obj-y += clk-pll.o`
clk: rockchip: add reset controller All Rockchip SoCs at least down to the ARM9-based RK28xx include the reset- controller for SoC peripherals in their clock controller. While the older SoCs (ARM9 and Cortex-A8) use a regular scheme to change register values, the Cortex-A9 SoCs use a hiword-mask making locking unecessary. To be compatible with both schemes the reset controller takes a flag to decide which scheme to use, similar to the other HIWORD_MASK flags used in the clock framework. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-By: Max Schwarz <max.schwarz@online.de> Tested-By: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-07-03 07:59:39 +08:00			`obj-$(CONFIG_RESET_CONTROLLER) += softrst.o`