2017-08-04 02:19:46 +08:00
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/*
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* Microsemi Switchtec(tm) PCIe Management Driver
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* Copyright (c) 2017, Microsemi Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/switchtec.h>
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#include <linux/module.h>
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2017-08-04 02:19:47 +08:00
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#include <linux/delay.h>
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#include <linux/kthread.h>
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2017-08-04 02:19:48 +08:00
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#include <linux/interrupt.h>
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2017-08-04 02:19:46 +08:00
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MODULE_DESCRIPTION("Microsemi Switchtec(tm) NTB Driver");
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MODULE_VERSION("0.1");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Microsemi Corporation");
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2017-08-04 02:19:47 +08:00
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static bool use_lut_mws;
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module_param(use_lut_mws, bool, 0644);
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MODULE_PARM_DESC(use_lut_mws,
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"Enable the use of the LUT based memory windows");
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#ifndef ioread64
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#ifdef readq
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#define ioread64 readq
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#else
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#define ioread64 _ioread64
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static inline u64 _ioread64(void __iomem *mmio)
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{
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u64 low, high;
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low = ioread32(mmio);
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high = ioread32(mmio + sizeof(u32));
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return low | (high << 32);
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}
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#endif
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#endif
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#ifndef iowrite64
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#ifdef writeq
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#define iowrite64 writeq
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#else
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#define iowrite64 _iowrite64
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static inline void _iowrite64(u64 val, void __iomem *mmio)
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{
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iowrite32(val, mmio);
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iowrite32(val >> 32, mmio + sizeof(u32));
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}
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#endif
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#endif
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#define SWITCHTEC_NTB_MAGIC 0x45CC0001
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#define MAX_MWS 128
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struct shared_mw {
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u32 magic;
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u32 partition_id;
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u64 mw_sizes[MAX_MWS];
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};
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#define MAX_DIRECT_MW ARRAY_SIZE(((struct ntb_ctrl_regs *)(0))->bar_entry)
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#define LUT_SIZE SZ_64K
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2017-08-04 02:19:46 +08:00
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struct switchtec_ntb {
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struct switchtec_dev *stdev;
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2017-08-04 02:19:47 +08:00
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int self_partition;
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int peer_partition;
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2017-08-04 02:19:48 +08:00
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int doorbell_irq;
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int message_irq;
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2017-08-04 02:19:47 +08:00
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struct ntb_info_regs __iomem *mmio_ntb;
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struct ntb_ctrl_regs __iomem *mmio_ctrl;
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struct ntb_dbmsg_regs __iomem *mmio_dbmsg;
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struct ntb_ctrl_regs __iomem *mmio_self_ctrl;
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struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
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struct ntb_dbmsg_regs __iomem *mmio_self_dbmsg;
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struct shared_mw *self_shared;
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struct shared_mw __iomem *peer_shared;
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dma_addr_t self_shared_dma;
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2017-08-04 02:19:48 +08:00
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u64 db_mask;
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u64 db_valid_mask;
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int db_shift;
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int db_peer_shift;
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2017-08-04 02:19:47 +08:00
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int nr_direct_mw;
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int nr_lut_mw;
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int direct_mw_to_bar[MAX_DIRECT_MW];
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int peer_nr_direct_mw;
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int peer_nr_lut_mw;
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int peer_direct_mw_to_bar[MAX_DIRECT_MW];
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2017-08-04 02:19:46 +08:00
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};
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2017-08-04 02:19:47 +08:00
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static int switchtec_ntb_part_op(struct switchtec_ntb *sndev,
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struct ntb_ctrl_regs __iomem *ctl,
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u32 op, int wait_status)
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{
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static const char * const op_text[] = {
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[NTB_CTRL_PART_OP_LOCK] = "lock",
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[NTB_CTRL_PART_OP_CFG] = "configure",
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[NTB_CTRL_PART_OP_RESET] = "reset",
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};
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int i;
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u32 ps;
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int status;
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switch (op) {
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case NTB_CTRL_PART_OP_LOCK:
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status = NTB_CTRL_PART_STATUS_LOCKING;
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break;
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case NTB_CTRL_PART_OP_CFG:
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status = NTB_CTRL_PART_STATUS_CONFIGURING;
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break;
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case NTB_CTRL_PART_OP_RESET:
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status = NTB_CTRL_PART_STATUS_RESETTING;
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break;
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default:
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return -EINVAL;
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}
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iowrite32(op, &ctl->partition_op);
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for (i = 0; i < 1000; i++) {
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if (msleep_interruptible(50) != 0) {
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iowrite32(NTB_CTRL_PART_OP_RESET, &ctl->partition_op);
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return -EINTR;
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}
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ps = ioread32(&ctl->partition_status) & 0xFFFF;
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if (ps != status)
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break;
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}
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if (ps == wait_status)
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return 0;
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if (ps == status) {
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dev_err(&sndev->stdev->dev,
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"Timed out while peforming %s (%d). (%08x)",
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op_text[op], op,
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ioread32(&ctl->partition_status));
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return -ETIMEDOUT;
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}
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return -EIO;
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}
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static void switchtec_ntb_init_sndev(struct switchtec_ntb *sndev)
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{
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u64 part_map;
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sndev->self_partition = sndev->stdev->partition;
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sndev->mmio_ntb = sndev->stdev->mmio_ntb;
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part_map = ioread64(&sndev->mmio_ntb->ep_map);
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part_map &= ~(1 << sndev->self_partition);
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sndev->peer_partition = ffs(part_map) - 1;
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dev_dbg(&sndev->stdev->dev, "Partition ID %d of %d (%llx)",
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sndev->self_partition, sndev->stdev->partition_count,
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part_map);
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sndev->mmio_ctrl = (void * __iomem)sndev->mmio_ntb +
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SWITCHTEC_NTB_REG_CTRL_OFFSET;
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sndev->mmio_dbmsg = (void * __iomem)sndev->mmio_ntb +
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SWITCHTEC_NTB_REG_DBMSG_OFFSET;
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sndev->mmio_self_ctrl = &sndev->mmio_ctrl[sndev->self_partition];
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sndev->mmio_peer_ctrl = &sndev->mmio_ctrl[sndev->peer_partition];
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sndev->mmio_self_dbmsg = &sndev->mmio_dbmsg[sndev->self_partition];
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}
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static int map_bars(int *map, struct ntb_ctrl_regs __iomem *ctrl)
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{
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int i;
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int cnt = 0;
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for (i = 0; i < ARRAY_SIZE(ctrl->bar_entry); i++) {
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u32 r = ioread32(&ctrl->bar_entry[i].ctl);
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if (r & NTB_CTRL_BAR_VALID)
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map[cnt++] = i;
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}
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return cnt;
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}
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static void switchtec_ntb_init_mw(struct switchtec_ntb *sndev)
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{
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sndev->nr_direct_mw = map_bars(sndev->direct_mw_to_bar,
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sndev->mmio_self_ctrl);
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sndev->nr_lut_mw = ioread16(&sndev->mmio_self_ctrl->lut_table_entries);
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sndev->nr_lut_mw = rounddown_pow_of_two(sndev->nr_lut_mw);
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dev_dbg(&sndev->stdev->dev, "MWs: %d direct, %d lut",
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sndev->nr_direct_mw, sndev->nr_lut_mw);
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sndev->peer_nr_direct_mw = map_bars(sndev->peer_direct_mw_to_bar,
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sndev->mmio_peer_ctrl);
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sndev->peer_nr_lut_mw =
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ioread16(&sndev->mmio_peer_ctrl->lut_table_entries);
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sndev->peer_nr_lut_mw = rounddown_pow_of_two(sndev->peer_nr_lut_mw);
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dev_dbg(&sndev->stdev->dev, "Peer MWs: %d direct, %d lut",
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sndev->peer_nr_direct_mw, sndev->peer_nr_lut_mw);
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}
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2017-08-04 02:19:48 +08:00
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/*
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* There are 64 doorbells in the switch hardware but this is
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* shared among all partitions. So we must split them in half
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* (32 for each partition). However, the message interrupts are
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* also shared with the top 4 doorbells so we just limit this to
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* 28 doorbells per partition
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*/
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static void switchtec_ntb_init_db(struct switchtec_ntb *sndev)
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{
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sndev->db_valid_mask = 0x0FFFFFFF;
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if (sndev->self_partition < sndev->peer_partition) {
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sndev->db_shift = 0;
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sndev->db_peer_shift = 32;
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} else {
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sndev->db_shift = 32;
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sndev->db_peer_shift = 0;
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}
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sndev->db_mask = 0x0FFFFFFFFFFFFFFFULL;
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iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask);
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iowrite64(sndev->db_valid_mask << sndev->db_peer_shift,
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&sndev->mmio_self_dbmsg->odb_mask);
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}
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static void switchtec_ntb_init_msgs(struct switchtec_ntb *sndev)
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{
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int i;
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u32 msg_map = 0;
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for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) {
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int m = i | sndev->peer_partition << 2;
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msg_map |= m << i * 8;
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}
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iowrite32(msg_map, &sndev->mmio_self_dbmsg->msg_map);
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for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++)
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iowrite64(NTB_DBMSG_IMSG_STATUS | NTB_DBMSG_IMSG_MASK,
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&sndev->mmio_self_dbmsg->imsg[i]);
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}
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2017-08-04 02:19:47 +08:00
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static int switchtec_ntb_init_req_id_table(struct switchtec_ntb *sndev)
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{
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int rc = 0;
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u16 req_id;
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u32 error;
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req_id = ioread16(&sndev->mmio_ntb->requester_id);
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if (ioread32(&sndev->mmio_self_ctrl->req_id_table_size) < 2) {
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dev_err(&sndev->stdev->dev,
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"Not enough requester IDs available.");
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return -EFAULT;
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}
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rc = switchtec_ntb_part_op(sndev, sndev->mmio_self_ctrl,
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NTB_CTRL_PART_OP_LOCK,
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NTB_CTRL_PART_STATUS_LOCKED);
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if (rc)
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return rc;
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iowrite32(NTB_PART_CTRL_ID_PROT_DIS,
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&sndev->mmio_self_ctrl->partition_ctrl);
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/*
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* Root Complex Requester ID (which is 0:00.0)
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*/
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iowrite32(0 << 16 | NTB_CTRL_REQ_ID_EN,
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&sndev->mmio_self_ctrl->req_id_table[0]);
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/*
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* Host Bridge Requester ID (as read from the mmap address)
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*/
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iowrite32(req_id << 16 | NTB_CTRL_REQ_ID_EN,
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&sndev->mmio_self_ctrl->req_id_table[1]);
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rc = switchtec_ntb_part_op(sndev, sndev->mmio_self_ctrl,
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NTB_CTRL_PART_OP_CFG,
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NTB_CTRL_PART_STATUS_NORMAL);
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if (rc == -EIO) {
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error = ioread32(&sndev->mmio_self_ctrl->req_id_error);
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dev_err(&sndev->stdev->dev,
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"Error setting up the requester ID table: %08x",
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error);
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}
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return rc;
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}
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static void switchtec_ntb_init_shared(struct switchtec_ntb *sndev)
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{
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int i;
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memset(sndev->self_shared, 0, LUT_SIZE);
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sndev->self_shared->magic = SWITCHTEC_NTB_MAGIC;
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sndev->self_shared->partition_id = sndev->stdev->partition;
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for (i = 0; i < sndev->nr_direct_mw; i++) {
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int bar = sndev->direct_mw_to_bar[i];
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resource_size_t sz = pci_resource_len(sndev->stdev->pdev, bar);
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if (i == 0)
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sz = min_t(resource_size_t, sz,
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LUT_SIZE * sndev->nr_lut_mw);
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sndev->self_shared->mw_sizes[i] = sz;
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}
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for (i = 0; i < sndev->nr_lut_mw; i++) {
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int idx = sndev->nr_direct_mw + i;
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sndev->self_shared->mw_sizes[idx] = LUT_SIZE;
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}
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}
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static int switchtec_ntb_init_shared_mw(struct switchtec_ntb *sndev)
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{
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struct ntb_ctrl_regs __iomem *ctl = sndev->mmio_peer_ctrl;
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int bar = sndev->direct_mw_to_bar[0];
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u32 ctl_val;
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int rc;
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sndev->self_shared = dma_zalloc_coherent(&sndev->stdev->pdev->dev,
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LUT_SIZE,
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&sndev->self_shared_dma,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!sndev->self_shared) {
|
|
|
|
dev_err(&sndev->stdev->dev,
|
|
|
|
"unable to allocate memory for shared mw");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
switchtec_ntb_init_shared(sndev);
|
|
|
|
|
|
|
|
rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_LOCK,
|
|
|
|
NTB_CTRL_PART_STATUS_LOCKED);
|
|
|
|
if (rc)
|
|
|
|
goto unalloc_and_exit;
|
|
|
|
|
|
|
|
ctl_val = ioread32(&ctl->bar_entry[bar].ctl);
|
|
|
|
ctl_val &= 0xFF;
|
|
|
|
ctl_val |= NTB_CTRL_BAR_LUT_WIN_EN;
|
|
|
|
ctl_val |= ilog2(LUT_SIZE) << 8;
|
|
|
|
ctl_val |= (sndev->nr_lut_mw - 1) << 14;
|
|
|
|
iowrite32(ctl_val, &ctl->bar_entry[bar].ctl);
|
|
|
|
|
|
|
|
iowrite64((NTB_CTRL_LUT_EN | (sndev->self_partition << 1) |
|
|
|
|
sndev->self_shared_dma),
|
|
|
|
&ctl->lut_entry[0]);
|
|
|
|
|
|
|
|
rc = switchtec_ntb_part_op(sndev, ctl, NTB_CTRL_PART_OP_CFG,
|
|
|
|
NTB_CTRL_PART_STATUS_NORMAL);
|
|
|
|
if (rc) {
|
|
|
|
u32 bar_error, lut_error;
|
|
|
|
|
|
|
|
bar_error = ioread32(&ctl->bar_error);
|
|
|
|
lut_error = ioread32(&ctl->lut_error);
|
|
|
|
dev_err(&sndev->stdev->dev,
|
|
|
|
"Error setting up shared MW: %08x / %08x",
|
|
|
|
bar_error, lut_error);
|
|
|
|
goto unalloc_and_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
sndev->peer_shared = pci_iomap(sndev->stdev->pdev, bar, LUT_SIZE);
|
|
|
|
if (!sndev->peer_shared) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto unalloc_and_exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(&sndev->stdev->dev, "Shared MW Ready");
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
unalloc_and_exit:
|
|
|
|
dma_free_coherent(&sndev->stdev->pdev->dev, LUT_SIZE,
|
|
|
|
sndev->self_shared, sndev->self_shared_dma);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void switchtec_ntb_deinit_shared_mw(struct switchtec_ntb *sndev)
|
|
|
|
{
|
|
|
|
if (sndev->peer_shared)
|
|
|
|
pci_iounmap(sndev->stdev->pdev, sndev->peer_shared);
|
|
|
|
|
|
|
|
if (sndev->self_shared)
|
|
|
|
dma_free_coherent(&sndev->stdev->pdev->dev, LUT_SIZE,
|
|
|
|
sndev->self_shared,
|
|
|
|
sndev->self_shared_dma);
|
|
|
|
}
|
|
|
|
|
2017-08-04 02:19:48 +08:00
|
|
|
static irqreturn_t switchtec_ntb_doorbell_isr(int irq, void *dev)
|
|
|
|
{
|
|
|
|
struct switchtec_ntb *sndev = dev;
|
|
|
|
|
|
|
|
dev_dbg(&sndev->stdev->dev, "doorbell\n");
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t switchtec_ntb_message_isr(int irq, void *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct switchtec_ntb *sndev = dev;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sndev->mmio_self_dbmsg->imsg); i++) {
|
|
|
|
u64 msg = ioread64(&sndev->mmio_self_dbmsg->imsg[i]);
|
|
|
|
|
|
|
|
if (msg & NTB_DBMSG_IMSG_STATUS) {
|
|
|
|
dev_dbg(&sndev->stdev->dev, "message: %d %08x\n", i,
|
|
|
|
(u32)msg);
|
|
|
|
iowrite8(1, &sndev->mmio_self_dbmsg->imsg[i].status);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int switchtec_ntb_init_db_msg_irq(struct switchtec_ntb *sndev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int rc;
|
|
|
|
int doorbell_irq = 0;
|
|
|
|
int message_irq = 0;
|
|
|
|
int event_irq;
|
|
|
|
int idb_vecs = sizeof(sndev->mmio_self_dbmsg->idb_vec_map);
|
|
|
|
|
|
|
|
event_irq = ioread32(&sndev->stdev->mmio_part_cfg->vep_vector_number);
|
|
|
|
|
|
|
|
while (doorbell_irq == event_irq)
|
|
|
|
doorbell_irq++;
|
|
|
|
while (message_irq == doorbell_irq ||
|
|
|
|
message_irq == event_irq)
|
|
|
|
message_irq++;
|
|
|
|
|
|
|
|
dev_dbg(&sndev->stdev->dev, "irqs - event: %d, db: %d, msgs: %d",
|
|
|
|
event_irq, doorbell_irq, message_irq);
|
|
|
|
|
|
|
|
for (i = 0; i < idb_vecs - 4; i++)
|
|
|
|
iowrite8(doorbell_irq,
|
|
|
|
&sndev->mmio_self_dbmsg->idb_vec_map[i]);
|
|
|
|
|
|
|
|
for (; i < idb_vecs; i++)
|
|
|
|
iowrite8(message_irq,
|
|
|
|
&sndev->mmio_self_dbmsg->idb_vec_map[i]);
|
|
|
|
|
|
|
|
sndev->doorbell_irq = pci_irq_vector(sndev->stdev->pdev, doorbell_irq);
|
|
|
|
sndev->message_irq = pci_irq_vector(sndev->stdev->pdev, message_irq);
|
|
|
|
|
|
|
|
rc = request_irq(sndev->doorbell_irq,
|
|
|
|
switchtec_ntb_doorbell_isr, 0,
|
|
|
|
"switchtec_ntb_doorbell", sndev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = request_irq(sndev->message_irq,
|
|
|
|
switchtec_ntb_message_isr, 0,
|
|
|
|
"switchtec_ntb_message", sndev);
|
|
|
|
if (rc) {
|
|
|
|
free_irq(sndev->doorbell_irq, sndev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void switchtec_ntb_deinit_db_msg_irq(struct switchtec_ntb *sndev)
|
|
|
|
{
|
|
|
|
free_irq(sndev->doorbell_irq, sndev);
|
|
|
|
free_irq(sndev->message_irq, sndev);
|
|
|
|
}
|
|
|
|
|
2017-08-04 02:19:46 +08:00
|
|
|
static int switchtec_ntb_add(struct device *dev,
|
|
|
|
struct class_interface *class_intf)
|
|
|
|
{
|
|
|
|
struct switchtec_dev *stdev = to_stdev(dev);
|
|
|
|
struct switchtec_ntb *sndev;
|
2017-08-04 02:19:47 +08:00
|
|
|
int rc;
|
2017-08-04 02:19:46 +08:00
|
|
|
|
|
|
|
stdev->sndev = NULL;
|
|
|
|
|
|
|
|
if (stdev->pdev->class != MICROSEMI_NTB_CLASSCODE)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2017-08-04 02:19:47 +08:00
|
|
|
if (stdev->partition_count != 2)
|
|
|
|
dev_warn(dev, "ntb driver only supports 2 partitions");
|
|
|
|
|
2017-08-04 02:19:46 +08:00
|
|
|
sndev = kzalloc_node(sizeof(*sndev), GFP_KERNEL, dev_to_node(dev));
|
|
|
|
if (!sndev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
sndev->stdev = stdev;
|
|
|
|
|
2017-08-04 02:19:47 +08:00
|
|
|
switchtec_ntb_init_sndev(sndev);
|
|
|
|
switchtec_ntb_init_mw(sndev);
|
2017-08-04 02:19:48 +08:00
|
|
|
switchtec_ntb_init_db(sndev);
|
|
|
|
switchtec_ntb_init_msgs(sndev);
|
2017-08-04 02:19:47 +08:00
|
|
|
|
|
|
|
rc = switchtec_ntb_init_req_id_table(sndev);
|
|
|
|
if (rc)
|
|
|
|
goto free_and_exit;
|
|
|
|
|
|
|
|
rc = switchtec_ntb_init_shared_mw(sndev);
|
|
|
|
if (rc)
|
|
|
|
goto free_and_exit;
|
|
|
|
|
2017-08-04 02:19:48 +08:00
|
|
|
rc = switchtec_ntb_init_db_msg_irq(sndev);
|
|
|
|
if (rc)
|
|
|
|
goto deinit_shared_and_exit;
|
|
|
|
|
2017-08-04 02:19:46 +08:00
|
|
|
stdev->sndev = sndev;
|
|
|
|
dev_info(dev, "NTB device registered");
|
|
|
|
|
|
|
|
return 0;
|
2017-08-04 02:19:47 +08:00
|
|
|
|
2017-08-04 02:19:48 +08:00
|
|
|
deinit_shared_and_exit:
|
|
|
|
switchtec_ntb_deinit_shared_mw(sndev);
|
2017-08-04 02:19:47 +08:00
|
|
|
free_and_exit:
|
|
|
|
kfree(sndev);
|
|
|
|
dev_err(dev, "failed to register ntb device: %d", rc);
|
|
|
|
return rc;
|
2017-08-04 02:19:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void switchtec_ntb_remove(struct device *dev,
|
|
|
|
struct class_interface *class_intf)
|
|
|
|
{
|
|
|
|
struct switchtec_dev *stdev = to_stdev(dev);
|
|
|
|
struct switchtec_ntb *sndev = stdev->sndev;
|
|
|
|
|
|
|
|
if (!sndev)
|
|
|
|
return;
|
|
|
|
|
|
|
|
stdev->sndev = NULL;
|
2017-08-04 02:19:48 +08:00
|
|
|
switchtec_ntb_deinit_db_msg_irq(sndev);
|
2017-08-04 02:19:47 +08:00
|
|
|
switchtec_ntb_deinit_shared_mw(sndev);
|
2017-08-04 02:19:46 +08:00
|
|
|
kfree(sndev);
|
|
|
|
dev_info(dev, "ntb device unregistered");
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct class_interface switchtec_interface = {
|
|
|
|
.add_dev = switchtec_ntb_add,
|
|
|
|
.remove_dev = switchtec_ntb_remove,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init switchtec_ntb_init(void)
|
|
|
|
{
|
|
|
|
switchtec_interface.class = switchtec_class;
|
|
|
|
return class_interface_register(&switchtec_interface);
|
|
|
|
}
|
|
|
|
module_init(switchtec_ntb_init);
|
|
|
|
|
|
|
|
static void __exit switchtec_ntb_exit(void)
|
|
|
|
{
|
|
|
|
class_interface_unregister(&switchtec_interface);
|
|
|
|
}
|
|
|
|
module_exit(switchtec_ntb_exit);
|