2014-01-16 02:47:25 +08:00
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/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/export.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/regmap.h>
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2014-05-17 07:07:11 +08:00
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#include <linux/math64.h>
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2014-01-16 02:47:25 +08:00
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#include <asm/div64.h>
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#include "clk-rcg.h"
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2014-09-05 04:21:50 +08:00
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#include "common.h"
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2014-01-16 02:47:25 +08:00
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#define CMD_REG 0x0
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#define CMD_UPDATE BIT(0)
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#define CMD_ROOT_EN BIT(1)
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#define CMD_DIRTY_CFG BIT(4)
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#define CMD_DIRTY_N BIT(5)
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#define CMD_DIRTY_M BIT(6)
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#define CMD_DIRTY_D BIT(7)
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#define CMD_ROOT_OFF BIT(31)
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#define CFG_REG 0x4
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#define CFG_SRC_DIV_SHIFT 0
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#define CFG_SRC_SEL_SHIFT 8
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#define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
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#define CFG_MODE_SHIFT 12
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#define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
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#define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
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#define M_REG 0x8
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#define N_REG 0xc
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#define D_REG 0x10
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static int clk_rcg2_is_enabled(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 cmd;
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int ret;
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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if (ret)
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return ret;
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2014-05-17 07:07:08 +08:00
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return (cmd & CMD_ROOT_OFF) == 0;
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2014-01-16 02:47:25 +08:00
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}
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static u8 clk_rcg2_get_parent(struct clk_hw *hw)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 cfg;
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int i, ret;
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
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if (ret)
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2015-03-21 00:30:24 +08:00
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goto err;
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2014-01-16 02:47:25 +08:00
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cfg &= CFG_SRC_SEL_MASK;
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cfg >>= CFG_SRC_SEL_SHIFT;
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for (i = 0; i < num_parents; i++)
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2015-03-21 00:30:26 +08:00
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if (cfg == rcg->parent_map[i].cfg)
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2014-01-16 02:47:25 +08:00
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return i;
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2015-03-21 00:30:24 +08:00
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err:
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pr_debug("%s: Clock %s has invalid parent, using default.\n",
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__func__, __clk_get_name(hw->clk));
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return 0;
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2014-01-16 02:47:25 +08:00
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}
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static int update_config(struct clk_rcg2 *rcg)
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{
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int count, ret;
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u32 cmd;
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struct clk_hw *hw = &rcg->clkr.hw;
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const char *name = __clk_get_name(hw->clk);
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
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CMD_UPDATE, CMD_UPDATE);
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if (ret)
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return ret;
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/* Wait for update to take effect */
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for (count = 500; count > 0; count--) {
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ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
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if (ret)
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return ret;
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if (!(cmd & CMD_UPDATE))
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return 0;
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udelay(1);
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}
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WARN(1, "%s: rcg didn't update its configuration.", name);
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return 0;
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}
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static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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int ret;
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2015-03-21 00:30:26 +08:00
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u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
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2014-01-16 02:47:25 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
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2015-03-21 00:30:26 +08:00
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CFG_SRC_SEL_MASK, cfg);
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2014-01-16 02:47:25 +08:00
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if (ret)
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return ret;
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return update_config(rcg);
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}
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/*
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* Calculate m/n:d rate
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*
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* parent_rate m
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* rate = ----------- x ---
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* hid_div n
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*/
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static unsigned long
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calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
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{
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if (hid_div) {
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rate *= 2;
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rate /= hid_div + 1;
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}
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if (mode) {
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u64 tmp = rate;
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tmp *= m;
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do_div(tmp, n);
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rate = tmp;
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}
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return rate;
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}
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static unsigned long
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clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
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if (rcg->mnd_width) {
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mask = BIT(rcg->mnd_width) - 1;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
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m &= mask;
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regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
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n = ~n;
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n &= mask;
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n += m;
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mode = cfg & CFG_MODE_MASK;
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mode >>= CFG_MODE_SHIFT;
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}
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mask = BIT(rcg->hid_width) - 1;
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hid_div = cfg >> CFG_SRC_DIV_SHIFT;
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hid_div &= mask;
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return calc_rate(parent_rate, m, n, mode, hid_div);
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}
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static long _freq_tbl_determine_rate(struct clk_hw *hw,
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const struct freq_tbl *f, unsigned long rate,
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2014-12-02 15:54:22 +08:00
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unsigned long *p_rate, struct clk_hw **p_hw)
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2014-01-16 02:47:25 +08:00
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{
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unsigned long clk_flags;
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2014-12-02 15:54:22 +08:00
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struct clk *p;
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2014-01-16 02:47:25 +08:00
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2014-09-05 04:21:50 +08:00
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f = qcom_find_freq(f, rate);
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2014-01-16 02:47:25 +08:00
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if (!f)
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return -EINVAL;
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clk_flags = __clk_get_flags(hw->clk);
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2014-12-02 15:54:22 +08:00
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p = clk_get_parent_by_index(hw->clk, f->src);
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2014-01-16 02:47:25 +08:00
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if (clk_flags & CLK_SET_RATE_PARENT) {
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if (f->pre_div) {
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rate /= 2;
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rate *= f->pre_div + 1;
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}
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if (f->n) {
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u64 tmp = rate;
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tmp = tmp * f->n;
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do_div(tmp, f->m);
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rate = tmp;
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}
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} else {
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2014-12-02 15:54:22 +08:00
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rate = __clk_get_rate(p);
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2014-01-16 02:47:25 +08:00
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}
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2014-12-02 15:54:22 +08:00
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*p_hw = __clk_get_hw(p);
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2014-01-16 02:47:25 +08:00
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*p_rate = rate;
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return f->freq;
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}
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static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
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2015-01-23 19:03:31 +08:00
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unsigned long min_rate, unsigned long max_rate,
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2014-12-02 15:54:22 +08:00
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unsigned long *p_rate, struct clk_hw **p)
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2014-01-16 02:47:25 +08:00
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
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}
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2014-05-17 07:07:11 +08:00
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static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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2014-01-16 02:47:25 +08:00
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{
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u32 cfg, mask;
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2015-03-21 00:30:26 +08:00
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struct clk_hw *hw = &rcg->clkr.hw;
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int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
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if (index < 0)
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return index;
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2014-01-16 02:47:25 +08:00
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if (rcg->mnd_width && f->n) {
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mask = BIT(rcg->mnd_width) - 1;
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2014-05-17 07:07:11 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + M_REG, mask, f->m);
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2014-01-16 02:47:25 +08:00
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if (ret)
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return ret;
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2014-05-17 07:07:11 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
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2014-01-16 02:47:25 +08:00
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if (ret)
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return ret;
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2014-05-17 07:07:11 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + D_REG, mask, ~f->n);
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2014-01-16 02:47:25 +08:00
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if (ret)
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return ret;
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}
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mask = BIT(rcg->hid_width) - 1;
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mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
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cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
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2015-03-21 00:30:26 +08:00
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cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
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2015-03-04 17:49:35 +08:00
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if (rcg->mnd_width && f->n && (f->m != f->n))
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2014-01-16 02:47:25 +08:00
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cfg |= CFG_MODE_DUAL_EDGE;
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2014-05-17 07:07:11 +08:00
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ret = regmap_update_bits(rcg->clkr.regmap,
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rcg->cmd_rcgr + CFG_REG, mask, cfg);
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2014-01-16 02:47:25 +08:00
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if (ret)
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return ret;
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return update_config(rcg);
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}
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2014-05-17 07:07:11 +08:00
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static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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const struct freq_tbl *f;
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2014-09-05 04:21:50 +08:00
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f = qcom_find_freq(rcg->freq_tbl, rate);
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2014-05-17 07:07:11 +08:00
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if (!f)
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return -EINVAL;
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return clk_rcg2_configure(rcg, f);
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}
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2014-01-16 02:47:25 +08:00
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static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return __clk_rcg2_set_rate(hw, rate);
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}
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static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate, u8 index)
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{
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return __clk_rcg2_set_rate(hw, rate);
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}
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const struct clk_ops clk_rcg2_ops = {
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.is_enabled = clk_rcg2_is_enabled,
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.get_parent = clk_rcg2_get_parent,
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.set_parent = clk_rcg2_set_parent,
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.recalc_rate = clk_rcg2_recalc_rate,
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.determine_rate = clk_rcg2_determine_rate,
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.set_rate = clk_rcg2_set_rate,
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.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
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};
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EXPORT_SYMBOL_GPL(clk_rcg2_ops);
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2014-05-17 07:07:11 +08:00
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struct frac_entry {
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int num;
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int den;
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};
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static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
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{ 52, 295 }, /* 119 M */
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{ 11, 57 }, /* 130.25 M */
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{ 63, 307 }, /* 138.50 M */
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{ 11, 50 }, /* 148.50 M */
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{ 47, 206 }, /* 154 M */
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{ 31, 100 }, /* 205.25 M */
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{ 107, 269 }, /* 268.50 M */
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{ },
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};
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static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
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{ 31, 211 }, /* 119 M */
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{ 32, 199 }, /* 130.25 M */
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{ 63, 307 }, /* 138.50 M */
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{ 11, 60 }, /* 148.50 M */
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{ 50, 263 }, /* 154 M */
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{ 31, 120 }, /* 205.25 M */
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{ 119, 359 }, /* 268.50 M */
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{ },
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};
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static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_rcg2 *rcg = to_clk_rcg2(hw);
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struct freq_tbl f = *rcg->freq_tbl;
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const struct frac_entry *frac;
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|
|
|
int delta = 100000;
|
|
|
|
s64 src_rate = parent_rate;
|
|
|
|
s64 request;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
u32 hid_div;
|
|
|
|
|
|
|
|
if (src_rate == 810000000)
|
|
|
|
frac = frac_table_810m;
|
|
|
|
else
|
|
|
|
frac = frac_table_675m;
|
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
|
|
|
request = rate;
|
|
|
|
request *= frac->den;
|
|
|
|
request = div_s64(request, frac->num);
|
|
|
|
if ((src_rate < (request - delta)) ||
|
|
|
|
(src_rate > (request + delta)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
&hid_div);
|
|
|
|
f.pre_div = hid_div;
|
|
|
|
f.pre_div >>= CFG_SRC_DIV_SHIFT;
|
|
|
|
f.pre_div &= mask;
|
|
|
|
f.m = frac->num;
|
|
|
|
f.n = frac->den;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
/* Parent index is set statically in frequency table */
|
|
|
|
return clk_edp_pixel_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
|
2015-01-23 19:03:31 +08:00
|
|
|
unsigned long min_rate,
|
|
|
|
unsigned long max_rate,
|
2014-12-02 15:54:22 +08:00
|
|
|
unsigned long *p_rate, struct clk_hw **p)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const struct freq_tbl *f = rcg->freq_tbl;
|
|
|
|
const struct frac_entry *frac;
|
|
|
|
int delta = 100000;
|
|
|
|
s64 src_rate = *p_rate;
|
|
|
|
s64 request;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
u32 hid_div;
|
|
|
|
|
|
|
|
/* Force the correct parent */
|
2014-12-02 15:54:22 +08:00
|
|
|
*p = __clk_get_hw(clk_get_parent_by_index(hw->clk, f->src));
|
2014-05-17 07:07:11 +08:00
|
|
|
|
|
|
|
if (src_rate == 810000000)
|
|
|
|
frac = frac_table_810m;
|
|
|
|
else
|
|
|
|
frac = frac_table_675m;
|
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
|
|
|
request = rate;
|
|
|
|
request *= frac->den;
|
|
|
|
request = div_s64(request, frac->num);
|
|
|
|
if ((src_rate < (request - delta)) ||
|
|
|
|
(src_rate > (request + delta)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
&hid_div);
|
|
|
|
hid_div >>= CFG_SRC_DIV_SHIFT;
|
|
|
|
hid_div &= mask;
|
|
|
|
|
|
|
|
return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
|
|
|
|
hid_div);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_edp_pixel_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_edp_pixel_set_rate,
|
|
|
|
.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_edp_pixel_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
|
|
|
|
|
|
|
|
static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
|
2015-01-23 19:03:31 +08:00
|
|
|
unsigned long min_rate, unsigned long max_rate,
|
2014-12-02 15:54:22 +08:00
|
|
|
unsigned long *p_rate, struct clk_hw **p_hw)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
const struct freq_tbl *f = rcg->freq_tbl;
|
|
|
|
unsigned long parent_rate, div;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
2014-12-02 15:54:22 +08:00
|
|
|
struct clk *p;
|
2014-05-17 07:07:11 +08:00
|
|
|
|
|
|
|
if (rate == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2014-12-02 15:54:22 +08:00
|
|
|
p = clk_get_parent_by_index(hw->clk, f->src);
|
|
|
|
*p_hw = __clk_get_hw(p);
|
|
|
|
*p_rate = parent_rate = __clk_round_rate(p, rate);
|
2014-05-17 07:07:11 +08:00
|
|
|
|
|
|
|
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
|
|
|
|
div = min_t(u32, div, mask);
|
|
|
|
|
|
|
|
return calc_rate(parent_rate, 0, 0, 0, div);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
struct freq_tbl f = *rcg->freq_tbl;
|
|
|
|
unsigned long div;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
|
|
|
|
div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
|
|
|
|
div = min_t(u32, div, mask);
|
|
|
|
|
|
|
|
f.pre_div = div;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
|
|
|
|
unsigned long rate, unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
/* Parent index is set statically in frequency table */
|
|
|
|
return clk_byte_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_byte_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_byte_set_rate,
|
|
|
|
.set_rate_and_parent = clk_byte_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_byte_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_byte_ops);
|
|
|
|
|
|
|
|
static const struct frac_entry frac_table_pixel[] = {
|
|
|
|
{ 3, 8 },
|
|
|
|
{ 2, 9 },
|
|
|
|
{ 4, 9 },
|
|
|
|
{ 1, 1 },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
|
2015-01-23 19:03:31 +08:00
|
|
|
unsigned long min_rate,
|
|
|
|
unsigned long max_rate,
|
2014-12-02 15:54:22 +08:00
|
|
|
unsigned long *p_rate, struct clk_hw **p)
|
2014-05-17 07:07:11 +08:00
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
unsigned long request, src_rate;
|
|
|
|
int delta = 100000;
|
|
|
|
const struct freq_tbl *f = rcg->freq_tbl;
|
|
|
|
const struct frac_entry *frac = frac_table_pixel;
|
2014-12-02 15:54:22 +08:00
|
|
|
struct clk *parent = clk_get_parent_by_index(hw->clk, f->src);
|
|
|
|
|
|
|
|
*p = __clk_get_hw(parent);
|
2014-05-17 07:07:11 +08:00
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
|
|
|
request = (rate * frac->den) / frac->num;
|
|
|
|
|
|
|
|
src_rate = __clk_round_rate(parent, request);
|
|
|
|
if ((src_rate < (request - delta)) ||
|
|
|
|
(src_rate > (request + delta)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
*p_rate = src_rate;
|
|
|
|
return (src_rate * frac->num) / frac->den;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate)
|
|
|
|
{
|
|
|
|
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
|
|
|
struct freq_tbl f = *rcg->freq_tbl;
|
|
|
|
const struct frac_entry *frac = frac_table_pixel;
|
|
|
|
unsigned long request, src_rate;
|
|
|
|
int delta = 100000;
|
|
|
|
u32 mask = BIT(rcg->hid_width) - 1;
|
|
|
|
u32 hid_div;
|
|
|
|
struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
|
|
|
|
|
|
|
|
for (; frac->num; frac++) {
|
|
|
|
request = (rate * frac->den) / frac->num;
|
|
|
|
|
|
|
|
src_rate = __clk_round_rate(parent, request);
|
|
|
|
if ((src_rate < (request - delta)) ||
|
|
|
|
(src_rate > (request + delta)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
|
|
|
|
&hid_div);
|
|
|
|
f.pre_div = hid_div;
|
|
|
|
f.pre_div >>= CFG_SRC_DIV_SHIFT;
|
|
|
|
f.pre_div &= mask;
|
|
|
|
f.m = frac->num;
|
|
|
|
f.n = frac->den;
|
|
|
|
|
|
|
|
return clk_rcg2_configure(rcg, &f);
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
|
|
|
|
unsigned long parent_rate, u8 index)
|
|
|
|
{
|
|
|
|
/* Parent index is set statically in frequency table */
|
|
|
|
return clk_pixel_set_rate(hw, rate, parent_rate);
|
|
|
|
}
|
|
|
|
|
|
|
|
const struct clk_ops clk_pixel_ops = {
|
|
|
|
.is_enabled = clk_rcg2_is_enabled,
|
|
|
|
.get_parent = clk_rcg2_get_parent,
|
|
|
|
.set_parent = clk_rcg2_set_parent,
|
|
|
|
.recalc_rate = clk_rcg2_recalc_rate,
|
|
|
|
.set_rate = clk_pixel_set_rate,
|
|
|
|
.set_rate_and_parent = clk_pixel_set_rate_and_parent,
|
|
|
|
.determine_rate = clk_pixel_determine_rate,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(clk_pixel_ops);
|