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linux-next/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts

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arm: dts: socfpga*.dts*: use SPDX-License-Identifier Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-06 04:27:27 +08:00
// SPDX-License-Identifier: GPL-2.0+
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
/*
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
* Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
*/
/dts-v1/;
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
#include "socfpga_arria10_socdk.dtsi"
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
&mmc {
ARM: socfpga: dts: enable UART1 for the debug uart Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add removal of unused aliases
2015-04-03 02:26:35 +08:00
status = "okay";
ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node Enable SD highspeed support for the SoCFPGA Arria10 devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-01-06 04:18:16 +08:00
cap-sd-highspeed;
ARM: dts: socfpga: enable MMC highspeed support Add 'cap-mmc-highspeed' property to enable high-speed support for MMC cards. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-02-06 06:32:47 +08:00
cap-mmc-highspeed;
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
broken-cd;
bus-width = <4>;
ARM: socfpga: dts: enable UART1 for the debug uart Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add removal of unused aliases
2015-04-03 02:26:35 +08:00
};
ARM: dts: Add Arria10 SD/MMC EDAC devicetree entry Add the device tree entries needed to support the Altera SD/MMC FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1470753653-23465-4-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-09 22:40:53 +08:00
&eccmgr {
sdmmca-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
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