2013-07-24 14:15:29 +08:00
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/*
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2013-10-15 10:44:54 +08:00
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* copyright (c) 2013 Freescale Semiconductor, Inc.
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2013-07-24 14:15:29 +08:00
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* Freescale IMX AHCI SATA platform driver
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/ahci_platform.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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2013-10-15 10:44:54 +08:00
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#include <linux/libata.h>
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2013-07-24 14:15:29 +08:00
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#include "ahci.h"
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enum {
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2014-05-04 21:48:05 +08:00
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/* Timer 1-ms Register */
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IMX_TIMER1MS = 0x00e0,
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/* Port0 PHY Control Register */
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IMX_P0PHYCR = 0x0178,
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IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
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2014-05-04 21:48:06 +08:00
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IMX_P0PHYCR_CR_READ = 1 << 19,
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IMX_P0PHYCR_CR_WRITE = 1 << 18,
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IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
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IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
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/* Port0 PHY Status Register */
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IMX_P0PHYSR = 0x017c,
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IMX_P0PHYSR_CR_ACK = 1 << 18,
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IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
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/* Lane0 Output Status Register */
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IMX_LANE0_OUT_STAT = 0x2003,
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IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
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/* Clock Reset Register */
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IMX_CLOCK_RESET = 0x7f3f,
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IMX_CLOCK_RESET_RESET = 1 << 0,
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2013-07-24 14:15:29 +08:00
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};
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2013-11-25 16:47:02 +08:00
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enum ahci_imx_type {
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AHCI_IMX53,
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AHCI_IMX6Q,
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};
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2013-07-24 14:15:29 +08:00
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struct imx_ahci_priv {
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struct platform_device *ahci_pdev;
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2013-11-25 16:47:02 +08:00
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enum ahci_imx_type type;
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2013-07-24 14:15:29 +08:00
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struct clk *ahb_clk;
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struct regmap *gpr;
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2013-10-15 10:44:54 +08:00
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bool no_device;
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bool first_time;
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};
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static int ahci_imx_hotplug;
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module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
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MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
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2014-02-22 23:53:37 +08:00
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static void ahci_imx_host_stop(struct ata_host *host);
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2014-05-04 21:48:06 +08:00
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static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
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{
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int timeout = 10;
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u32 crval;
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u32 srval;
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/* Assert or deassert the bit */
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crval = readl(mmio + IMX_P0PHYCR);
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if (assert)
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crval |= bit;
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else
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crval &= ~bit;
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writel(crval, mmio + IMX_P0PHYCR);
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/* Wait for the cr_ack signal */
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do {
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srval = readl(mmio + IMX_P0PHYSR);
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if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
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break;
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usleep_range(100, 200);
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} while (--timeout);
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return timeout ? 0 : -ETIMEDOUT;
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}
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static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
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{
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u32 crval = addr;
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int ret;
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/* Supply the address on cr_data_in */
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writel(crval, mmio + IMX_P0PHYCR);
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/* Assert the cr_cap_addr signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
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if (ret)
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return ret;
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/* Deassert cr_cap_addr */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
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if (ret)
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return ret;
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return 0;
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}
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static int imx_phy_reg_write(u16 val, void __iomem *mmio)
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{
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u32 crval = val;
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int ret;
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/* Supply the data on cr_data_in */
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writel(crval, mmio + IMX_P0PHYCR);
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/* Assert the cr_cap_data signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
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if (ret)
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return ret;
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/* Deassert cr_cap_data */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
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if (ret)
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return ret;
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if (val & IMX_CLOCK_RESET_RESET) {
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/*
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* In case we're resetting the phy, it's unable to acknowledge,
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* so we return immediately here.
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*/
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crval |= IMX_P0PHYCR_CR_WRITE;
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writel(crval, mmio + IMX_P0PHYCR);
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goto out;
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}
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/* Assert the cr_write signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
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if (ret)
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return ret;
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/* Deassert cr_write */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
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if (ret)
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return ret;
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out:
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return 0;
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}
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static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
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{
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int ret;
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/* Assert the cr_read signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
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if (ret)
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return ret;
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/* Capture the data from cr_data_out[] */
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*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
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/* Deassert cr_read */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
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if (ret)
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return ret;
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return 0;
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}
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static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
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{
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void __iomem *mmio = hpriv->mmio;
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int timeout = 10;
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u16 val;
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int ret;
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/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
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ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
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if (ret)
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return ret;
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ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
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if (ret)
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return ret;
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/* Wait for PHY RX_PLL to be stable */
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do {
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usleep_range(100, 200);
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ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
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if (ret)
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return ret;
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ret = imx_phy_reg_read(&val, mmio);
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if (ret)
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return ret;
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if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
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break;
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} while (--timeout);
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return timeout ? 0 : -ETIMEDOUT;
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}
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2014-02-22 23:53:37 +08:00
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static int imx_sata_enable(struct ahci_host_priv *hpriv)
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2013-11-25 16:47:01 +08:00
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{
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2014-02-22 23:53:37 +08:00
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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2014-05-04 21:48:06 +08:00
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struct device *dev = &imxpriv->ahci_pdev->dev;
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2013-11-25 16:47:01 +08:00
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int ret;
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2014-02-22 23:53:37 +08:00
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if (imxpriv->no_device)
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return 0;
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if (hpriv->target_pwr) {
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ret = regulator_enable(hpriv->target_pwr);
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if (ret)
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2013-11-25 16:47:02 +08:00
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return ret;
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}
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2014-02-22 23:53:37 +08:00
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ret = ahci_platform_enable_clks(hpriv);
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if (ret < 0)
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goto disable_regulator;
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2013-11-25 16:47:01 +08:00
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2013-11-25 16:47:02 +08:00
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if (imxpriv->type == AHCI_IMX6Q) {
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2014-02-22 23:53:37 +08:00
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/*
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* set PHY Paremeters, two steps to configure the GPR13,
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* one write for rest of parameters, mask of first write
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* is 0x07ffffff, and the other one write for setting
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* the mpll_clk_en.
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*/
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
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IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
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IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
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IMX6Q_GPR13_SATA_SPD_MODE_MASK |
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IMX6Q_GPR13_SATA_MPLL_SS_EN |
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IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
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IMX6Q_GPR13_SATA_TX_BOOST_MASK |
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IMX6Q_GPR13_SATA_TX_LVL_MASK |
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IMX6Q_GPR13_SATA_MPLL_CLK_EN |
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IMX6Q_GPR13_SATA_TX_EDGE_RATE,
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IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
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IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
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IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
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IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
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IMX6Q_GPR13_SATA_MPLL_SS_EN |
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IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
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IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
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IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
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2013-11-25 16:47:02 +08:00
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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2014-05-04 21:48:06 +08:00
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ret = imx_sata_phy_reset(hpriv);
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if (ret) {
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dev_err(dev, "failed to reset phy: %d\n", ret);
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goto disable_regulator;
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}
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2013-11-25 16:47:02 +08:00
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}
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2013-11-25 16:47:01 +08:00
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usleep_range(1000, 2000);
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return 0;
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2013-11-25 16:47:02 +08:00
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2014-02-22 23:53:37 +08:00
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disable_regulator:
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if (hpriv->target_pwr)
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regulator_disable(hpriv->target_pwr);
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2013-11-25 16:47:02 +08:00
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return ret;
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2013-11-25 16:47:01 +08:00
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}
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2014-02-22 23:53:37 +08:00
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static void imx_sata_disable(struct ahci_host_priv *hpriv)
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2013-11-25 16:47:01 +08:00
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{
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2014-02-22 23:53:37 +08:00
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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if (imxpriv->no_device)
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return;
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2013-11-25 16:47:01 +08:00
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2013-11-25 16:47:02 +08:00
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if (imxpriv->type == AHCI_IMX6Q) {
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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}
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2014-02-22 23:53:37 +08:00
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ahci_platform_disable_clks(hpriv);
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2013-11-25 16:47:02 +08:00
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2014-02-22 23:53:37 +08:00
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if (hpriv->target_pwr)
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regulator_disable(hpriv->target_pwr);
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2013-11-25 16:47:01 +08:00
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}
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2013-10-15 10:44:54 +08:00
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static void ahci_imx_error_handler(struct ata_port *ap)
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{
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u32 reg_val;
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struct ata_device *dev;
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struct ata_host *host = dev_get_drvdata(ap->dev);
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struct ahci_host_priv *hpriv = host->private_data;
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void __iomem *mmio = hpriv->mmio;
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2014-02-22 23:53:37 +08:00
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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2013-10-15 10:44:54 +08:00
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ahci_error_handler(ap);
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if (!(imxpriv->first_time) || ahci_imx_hotplug)
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return;
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imxpriv->first_time = false;
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ata_for_each_dev(dev, &ap->link, ENABLED)
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return;
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/*
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* Disable link to save power. An imx ahci port can't be recovered
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* without full reset once the pddq mode is enabled making it
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* impossible to use as part of libata LPM.
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*/
|
2014-05-04 21:48:05 +08:00
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reg_val = readl(mmio + IMX_P0PHYCR);
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writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
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2014-02-22 23:53:37 +08:00
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|
|
imx_sata_disable(hpriv);
|
2013-10-15 10:44:54 +08:00
|
|
|
imxpriv->no_device = true;
|
|
|
|
}
|
|
|
|
|
2013-12-03 23:25:37 +08:00
|
|
|
static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
|
2013-11-25 16:47:02 +08:00
|
|
|
unsigned long deadline)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = link->ap;
|
2014-02-22 23:53:37 +08:00
|
|
|
struct ata_host *host = dev_get_drvdata(ap->dev);
|
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
|
|
struct imx_ahci_priv *imxpriv = hpriv->plat_data;
|
2013-11-25 16:47:02 +08:00
|
|
|
int ret = -EIO;
|
|
|
|
|
|
|
|
if (imxpriv->type == AHCI_IMX53)
|
|
|
|
ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
|
|
|
|
else if (imxpriv->type == AHCI_IMX6Q)
|
|
|
|
ret = ahci_ops.softreset(link, class, deadline);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-10-15 10:44:54 +08:00
|
|
|
static struct ata_port_operations ahci_imx_ops = {
|
2014-02-22 23:53:37 +08:00
|
|
|
.inherits = &ahci_ops,
|
|
|
|
.host_stop = ahci_imx_host_stop,
|
2013-10-15 10:44:54 +08:00
|
|
|
.error_handler = ahci_imx_error_handler,
|
2013-11-25 16:47:02 +08:00
|
|
|
.softreset = ahci_imx_softreset,
|
2013-10-15 10:44:54 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ata_port_info ahci_imx_port_info = {
|
|
|
|
.flags = AHCI_FLAG_COMMON,
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &ahci_imx_ops,
|
2013-07-24 14:15:29 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id imx_ahci_of_match[] = {
|
2013-11-25 16:47:02 +08:00
|
|
|
{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
|
|
|
|
{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
|
2013-07-24 14:15:29 +08:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
|
|
|
|
|
|
|
|
static int imx_ahci_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
const struct of_device_id *of_id;
|
2014-02-22 23:53:37 +08:00
|
|
|
struct ahci_host_priv *hpriv;
|
2013-07-24 14:15:29 +08:00
|
|
|
struct imx_ahci_priv *imxpriv;
|
2014-02-22 23:53:37 +08:00
|
|
|
unsigned int reg_val;
|
2013-07-24 14:15:29 +08:00
|
|
|
int ret;
|
|
|
|
|
2013-11-25 16:47:02 +08:00
|
|
|
of_id = of_match_device(imx_ahci_of_match, dev);
|
|
|
|
if (!of_id)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-07-24 14:15:29 +08:00
|
|
|
imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
|
2014-02-22 23:53:37 +08:00
|
|
|
if (!imxpriv)
|
2013-07-24 14:15:29 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-05-04 21:48:06 +08:00
|
|
|
imxpriv->ahci_pdev = pdev;
|
2013-10-15 10:44:54 +08:00
|
|
|
imxpriv->no_device = false;
|
|
|
|
imxpriv->first_time = true;
|
2014-02-22 23:53:37 +08:00
|
|
|
imxpriv->type = (enum ahci_imx_type)of_id->data;
|
2013-07-24 14:15:29 +08:00
|
|
|
imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
|
|
|
|
if (IS_ERR(imxpriv->ahb_clk)) {
|
|
|
|
dev_err(dev, "can't get ahb clock.\n");
|
2014-02-22 23:53:37 +08:00
|
|
|
return PTR_ERR(imxpriv->ahb_clk);
|
2013-07-24 14:15:29 +08:00
|
|
|
}
|
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
if (imxpriv->type == AHCI_IMX6Q) {
|
|
|
|
imxpriv->gpr = syscon_regmap_lookup_by_compatible(
|
|
|
|
"fsl,imx6q-iomuxc-gpr");
|
|
|
|
if (IS_ERR(imxpriv->gpr)) {
|
|
|
|
dev_err(dev,
|
|
|
|
"failed to find fsl,imx6q-iomux-gpr regmap\n");
|
|
|
|
return PTR_ERR(imxpriv->gpr);
|
2013-11-25 16:47:02 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
hpriv = ahci_platform_get_resources(pdev);
|
|
|
|
if (IS_ERR(hpriv))
|
|
|
|
return PTR_ERR(hpriv);
|
|
|
|
|
|
|
|
hpriv->plat_data = imxpriv;
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
ret = imx_sata_enable(hpriv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
/*
|
|
|
|
* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
|
2014-05-04 21:48:05 +08:00
|
|
|
* and IP vendor specific register IMX_TIMER1MS.
|
2014-02-22 23:53:37 +08:00
|
|
|
* Configure CAP_SSS (support stagered spin up).
|
|
|
|
* Implement the port0.
|
|
|
|
* Get the ahb clock rate, and configure the TIMER1MS register.
|
|
|
|
*/
|
|
|
|
reg_val = readl(hpriv->mmio + HOST_CAP);
|
|
|
|
if (!(reg_val & HOST_CAP_SSS)) {
|
|
|
|
reg_val |= HOST_CAP_SSS;
|
|
|
|
writel(reg_val, hpriv->mmio + HOST_CAP);
|
|
|
|
}
|
|
|
|
reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
|
|
|
|
if (!(reg_val & 0x1)) {
|
|
|
|
reg_val |= 0x1;
|
|
|
|
writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
|
2013-07-24 14:15:29 +08:00
|
|
|
}
|
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
|
2014-05-04 21:48:05 +08:00
|
|
|
writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
|
|
|
|
if (ret)
|
|
|
|
imx_sata_disable(hpriv);
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
return ret;
|
|
|
|
}
|
2013-11-25 16:47:02 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
static void ahci_imx_host_stop(struct ata_host *host)
|
|
|
|
{
|
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
2013-11-25 16:47:01 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
imx_sata_disable(hpriv);
|
|
|
|
}
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-03-06 03:17:49 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2014-02-22 23:53:37 +08:00
|
|
|
static int imx_ahci_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
|
|
int ret;
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
ret = ahci_platform_suspend_host(dev);
|
|
|
|
if (ret)
|
2013-07-24 14:15:29 +08:00
|
|
|
return ret;
|
2014-02-22 23:53:37 +08:00
|
|
|
|
|
|
|
imx_sata_disable(hpriv);
|
2013-07-24 14:15:29 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
static int imx_ahci_resume(struct device *dev)
|
2013-07-24 14:15:29 +08:00
|
|
|
{
|
2014-02-22 23:53:37 +08:00
|
|
|
struct ata_host *host = dev_get_drvdata(dev);
|
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
|
|
int ret;
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
ret = imx_sata_enable(hpriv);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return ahci_platform_resume_host(dev);
|
2013-07-24 14:15:29 +08:00
|
|
|
}
|
2014-03-06 03:17:49 +08:00
|
|
|
#endif
|
2013-07-24 14:15:29 +08:00
|
|
|
|
2014-02-22 23:53:37 +08:00
|
|
|
static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
|
|
|
|
|
2013-07-24 14:15:29 +08:00
|
|
|
static struct platform_driver imx_ahci_driver = {
|
|
|
|
.probe = imx_ahci_probe,
|
2014-02-22 23:53:37 +08:00
|
|
|
.remove = ata_platform_remove_one,
|
2013-07-24 14:15:29 +08:00
|
|
|
.driver = {
|
|
|
|
.name = "ahci-imx",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = imx_ahci_of_match,
|
2014-02-22 23:53:37 +08:00
|
|
|
.pm = &ahci_imx_pm_ops,
|
2013-07-24 14:15:29 +08:00
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(imx_ahci_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
|
|
|
|
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("ahci:imx");
|