2019-06-04 16:11:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2014-11-18 03:02:35 +08:00
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/*
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2020-07-08 17:34:51 +08:00
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* Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com
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2014-11-18 03:02:35 +08:00
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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/ {
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model = "NovaTech OrionLXm";
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compatible = "novatech,am335x-lxm", "ti,am33xx";
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cpus {
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cpu@0 {
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cpu0-supply = <&vdd1_reg>;
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};
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};
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2016-08-31 18:35:30 +08:00
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memory@80000000 {
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2014-11-18 03:02:35 +08:00
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device_type = "memory";
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reg = <0x80000000 0x20000000>; /* 512 MB */
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};
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/* Power supply provides a fixed 5V @2A */
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2016-08-02 00:46:58 +08:00
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vbat: fixedregulator0 {
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2014-11-18 03:02:35 +08:00
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compatible = "regulator-fixed";
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regulator-name = "vbat";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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/* Power supply provides a fixed 3.3V @3A */
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2016-08-02 00:46:58 +08:00
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vmmcsd_fixed: fixedregulator1 {
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2014-11-18 03:02:35 +08:00
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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&am33xx_pinmux {
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
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2014-11-18 03:02:35 +08:00
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>;
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};
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
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2014-11-18 03:02:35 +08:00
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
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AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */
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AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */
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AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */
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AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
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2014-11-18 03:02:35 +08:00
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/* Slave 2 */
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
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AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
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2014-11-18 03:02:35 +08:00
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */
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AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */
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AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */
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AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */
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AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */
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AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */
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AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */
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2014-11-18 03:02:35 +08:00
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/* Slave 2 reset value*/
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */
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AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */
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2014-11-18 03:02:35 +08:00
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
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2014-11-18 03:02:35 +08:00
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
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AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
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2014-11-18 03:02:35 +08:00
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>;
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};
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emmc_pins: pinmux_emmc_pins {
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pinctrl-single,pins = <
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
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2014-11-18 03:02:35 +08:00
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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2019-04-13 00:26:12 +08:00
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AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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2014-11-18 03:02:35 +08:00
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>;
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <400000>;
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serial_config1: serial_config1@20 {
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compatible = "nxp,pca9539";
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reg = <0x20>;
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2020-09-16 23:57:08 +08:00
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gpio-controller;
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#gpio-cells = <2>;
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2014-11-18 03:02:35 +08:00
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};
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serial_config2: serial_config2@21 {
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compatible = "nxp,pca9539";
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reg = <0x21>;
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2020-09-16 23:57:08 +08:00
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gpio-controller;
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#gpio-cells = <2>;
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2014-11-18 03:02:35 +08:00
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};
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tps: tps@2d {
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compatible = "ti,tps65910";
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reg = <0x2d>;
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};
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};
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/include/ "tps65910.dtsi"
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&tps {
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vcc1-supply = <&vbat>;
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vcc2-supply = <&vbat>;
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vcc3-supply = <&vbat>;
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vcc4-supply = <&vbat>;
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vcc5-supply = <&vbat>;
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vcc6-supply = <&vbat>;
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vcc7-supply = <&vbat>;
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vccio-supply = <&vbat>;
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regulators {
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/* vrtc - unused */
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vio_reg: regulator@1 {
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regulator-name = "vio_1v5,ddr";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vdd1_reg: regulator@2 {
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regulator-name = "vdd1,mpu";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <1500000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vdd2_reg: regulator@3 {
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regulator-name = "vdd2_1v1,core";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vdd3 - unused */
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/* vdig1 - unused */
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vdig2_reg: regulator@6 {
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regulator-name = "vdig2_1v8,vdds_pll";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* vpll - unused */
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vdac_reg: regulator@8 {
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regulator-name = "vdac_1v8,vdds";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vaux1_reg: regulator@9 {
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regulator-name = "vaux1_1v8,usb";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vaux2_reg: regulator@10 {
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regulator-name = "vaux2_3v3,io";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vaux33_reg: regulator@11 {
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regulator-name = "vaux33_3v3,usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vmmc_reg: regulator@12 {
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regulator-name = "vmmc_3v3,io";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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&sham {
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status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&aes {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&uart0 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&uart0_pins>;
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb0 {
|
|
|
|
dr_mode = "host";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb1 {
|
|
|
|
dr_mode = "host";
|
|
|
|
};
|
|
|
|
|
|
|
|
&cpsw_emac0 {
|
2018-09-09 08:05:03 +08:00
|
|
|
phy-handle = <ðphy0>;
|
2014-11-18 03:02:35 +08:00
|
|
|
phy-mode = "rmii";
|
|
|
|
dual_emac_res_vlan = <2>;
|
|
|
|
};
|
|
|
|
|
|
|
|
&cpsw_emac1 {
|
2018-09-09 08:05:03 +08:00
|
|
|
phy-handle = <ðphy1>;
|
2014-11-18 03:02:35 +08:00
|
|
|
phy-mode = "rmii";
|
|
|
|
dual_emac_res_vlan = <3>;
|
|
|
|
};
|
|
|
|
|
|
|
|
&mac {
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
pinctrl-0 = <&cpsw_default>;
|
|
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
|
|
dual_emac = <1>;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&davinci_mdio {
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
|
|
status = "okay";
|
2018-09-09 08:05:03 +08:00
|
|
|
|
|
|
|
ethphy0: ethernet-phy@5 {
|
|
|
|
reg = <5>;
|
|
|
|
};
|
|
|
|
|
|
|
|
ethphy1: ethernet-phy@4 {
|
|
|
|
reg = <4>;
|
|
|
|
};
|
2014-11-18 03:02:35 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
&mmc1 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
|
|
vmmc-supply = <&vmmcsd_fixed>;
|
|
|
|
bus-width = <4>;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&mmc2 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&emmc_pins>;
|
|
|
|
vmmc-supply = <&vmmcsd_fixed>;
|
|
|
|
bus-width = <8>;
|
2020-05-13 04:38:04 +08:00
|
|
|
non-removable;
|
2014-11-18 03:02:35 +08:00
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|