2006-10-18 19:34:16 +08:00
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/*
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* Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
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*
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2007-07-27 21:08:51 +08:00
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* Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
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2006-10-18 19:34:16 +08:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2.
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*/
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#include <linux/kernel.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2006-10-18 19:34:16 +08:00
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#include <linux/i2c.h>
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2009-09-15 17:46:52 +08:00
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#include "dvb_math.h"
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2006-10-18 19:34:16 +08:00
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#include "dvb_frontend.h"
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#include "dib7000p.h"
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
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2007-07-31 18:09:30 +08:00
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static int buggy_sfn_workaround;
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module_param(buggy_sfn_workaround, int, 0644);
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2007-07-31 21:36:06 +08:00
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MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
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2007-07-31 18:09:30 +08:00
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2007-07-27 21:08:51 +08:00
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#define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
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2006-10-18 19:34:16 +08:00
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2011-01-04 15:54:31 +08:00
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struct i2c_device {
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struct i2c_adapter *i2c_adap;
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u8 i2c_addr;
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};
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2006-10-18 19:34:16 +08:00
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struct dib7000p_state {
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struct dvb_frontend demod;
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2011-01-04 15:54:31 +08:00
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struct dib7000p_config cfg;
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2006-10-18 19:34:16 +08:00
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u8 i2c_addr;
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2011-01-04 15:54:31 +08:00
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struct i2c_adapter *i2c_adap;
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2006-10-18 19:34:16 +08:00
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struct dibx000_i2c_master i2c_master;
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u16 wbd_ref;
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2011-01-04 15:54:31 +08:00
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u8 current_band;
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2008-01-25 18:31:58 +08:00
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u32 current_bandwidth;
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2006-10-18 19:34:16 +08:00
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struct dibx000_agc_config *current_agc;
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u32 timf;
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2011-01-04 15:54:31 +08:00
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u8 div_force_off:1;
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u8 div_state:1;
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2007-07-30 23:49:04 +08:00
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u16 div_sync_wait;
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2007-07-27 21:08:51 +08:00
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u8 agc_state;
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2006-10-18 19:34:16 +08:00
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u16 gpio_dir;
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u16 gpio_val;
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2007-07-31 18:09:30 +08:00
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2011-01-04 15:54:31 +08:00
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u8 sfn_workaround_active:1;
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#define SOC7090 0x7090
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u16 version;
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u16 tuner_enable;
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struct i2c_adapter dib7090_tuner_adap;
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2011-05-03 23:27:33 +08:00
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/* for the I2C transfer */
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struct i2c_msg msg[2];
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u8 i2c_write_buffer[4];
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u8 i2c_read_buffer[2];
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2006-10-18 19:34:16 +08:00
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};
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enum dib7000p_power_mode {
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DIB7000P_POWER_ALL = 0,
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2007-07-27 21:08:51 +08:00
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DIB7000P_POWER_ANALOG_ADC,
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2006-10-18 19:34:16 +08:00
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DIB7000P_POWER_INTERFACE_ONLY,
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};
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2011-01-04 15:54:31 +08:00
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static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
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static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
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2006-10-18 19:34:16 +08:00
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static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
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{
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2011-05-03 23:27:33 +08:00
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state->i2c_write_buffer[0] = reg >> 8;
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state->i2c_write_buffer[1] = reg & 0xff;
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memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
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state->msg[0].addr = state->i2c_addr >> 1;
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state->msg[0].flags = 0;
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state->msg[0].buf = state->i2c_write_buffer;
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state->msg[0].len = 2;
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state->msg[1].addr = state->i2c_addr >> 1;
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state->msg[1].flags = I2C_M_RD;
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state->msg[1].buf = state->i2c_read_buffer;
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state->msg[1].len = 2;
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if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
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2011-01-04 15:54:31 +08:00
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dprintk("i2c read error on %d", reg);
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2006-10-18 19:34:16 +08:00
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2011-05-03 23:27:33 +08:00
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return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
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2006-10-18 19:34:16 +08:00
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}
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static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
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{
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2011-05-03 23:27:33 +08:00
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state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
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state->i2c_write_buffer[1] = reg & 0xff;
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state->i2c_write_buffer[2] = (val >> 8) & 0xff;
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state->i2c_write_buffer[3] = val & 0xff;
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memset(&state->msg[0], 0, sizeof(struct i2c_msg));
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state->msg[0].addr = state->i2c_addr >> 1;
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state->msg[0].flags = 0;
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state->msg[0].buf = state->i2c_write_buffer;
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state->msg[0].len = 4;
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return i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
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2006-10-18 19:34:16 +08:00
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}
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2011-01-04 15:54:31 +08:00
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static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
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2007-07-27 21:08:51 +08:00
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{
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u16 l = 0, r, *n;
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n = buf;
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l = *n++;
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while (l) {
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r = *n++;
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do {
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dib7000p_write_word(state, r, *n++);
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r++;
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} while (--l);
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l = *n++;
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}
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}
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2006-10-18 19:34:16 +08:00
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static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
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{
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2011-01-04 15:54:31 +08:00
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int ret = 0;
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2006-10-18 19:34:16 +08:00
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u16 outreg, fifo_threshold, smo_mode;
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outreg = 0;
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fifo_threshold = 1792;
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2009-09-24 00:41:27 +08:00
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smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
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2006-10-18 19:34:16 +08:00
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2011-01-04 15:54:31 +08:00
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dprintk("setting output mode for demod %p to %d", &state->demod, mode);
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2006-10-18 19:34:16 +08:00
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switch (mode) {
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2011-01-05 00:08:14 +08:00
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case OUTMODE_MPEG2_PAR_GATED_CLK:
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2011-01-04 15:54:31 +08:00
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outreg = (1 << 10); /* 0x0400 */
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break;
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2011-01-05 00:08:14 +08:00
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case OUTMODE_MPEG2_PAR_CONT_CLK:
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2011-01-04 15:54:31 +08:00
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outreg = (1 << 10) | (1 << 6); /* 0x0440 */
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break;
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2011-01-05 00:08:14 +08:00
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case OUTMODE_MPEG2_SERIAL:
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2011-01-04 15:54:31 +08:00
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outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */
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break;
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case OUTMODE_DIVERSITY:
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if (state->cfg.hostbus_diversity)
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outreg = (1 << 10) | (4 << 6); /* 0x0500 */
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else
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outreg = (1 << 11);
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break;
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2011-01-05 00:08:14 +08:00
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case OUTMODE_MPEG2_FIFO:
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2011-01-04 15:54:31 +08:00
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smo_mode |= (3 << 1);
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fifo_threshold = 512;
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outreg = (1 << 10) | (5 << 6);
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break;
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case OUTMODE_ANALOG_ADC:
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outreg = (1 << 10) | (3 << 6);
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break;
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2011-01-05 00:08:14 +08:00
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case OUTMODE_HIGH_Z:
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2011-01-04 15:54:31 +08:00
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outreg = 0;
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break;
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default:
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dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
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break;
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2006-10-18 19:34:16 +08:00
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}
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if (state->cfg.output_mpeg2_in_188_bytes)
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2011-01-04 15:54:31 +08:00
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smo_mode |= (1 << 5);
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2006-10-18 19:34:16 +08:00
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2011-01-04 15:54:31 +08:00
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ret |= dib7000p_write_word(state, 235, smo_mode);
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ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
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if (state->version != SOC7090)
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ret |= dib7000p_write_word(state, 1286, outreg); /* P_Div_active */
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2006-10-18 19:34:16 +08:00
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return ret;
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}
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2007-07-27 21:08:51 +08:00
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static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
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{
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struct dib7000p_state *state = demod->demodulator_priv;
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if (state->div_force_off) {
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2011-01-04 15:54:31 +08:00
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dprintk("diversity combination deactivated - forced by COFDM parameters");
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2007-07-27 21:08:51 +08:00
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onoff = 0;
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2009-09-24 00:41:27 +08:00
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dib7000p_write_word(state, 207, 0);
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} else
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dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
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2011-01-04 15:54:31 +08:00
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state->div_state = (u8) onoff;
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2007-07-27 21:08:51 +08:00
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if (onoff) {
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dib7000p_write_word(state, 204, 6);
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dib7000p_write_word(state, 205, 16);
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/* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
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} else {
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dib7000p_write_word(state, 204, 1);
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dib7000p_write_word(state, 205, 0);
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}
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return 0;
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}
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2006-10-18 19:34:16 +08:00
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static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
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{
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/* by default everything is powered off */
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2011-01-04 15:54:31 +08:00
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u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
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2006-10-18 19:34:16 +08:00
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/* now, depending on the requested mode, we power on */
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switch (mode) {
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/* power up everything in the demod */
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2011-01-04 15:54:31 +08:00
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case DIB7000P_POWER_ALL:
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reg_774 = 0x0000;
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reg_775 = 0x0000;
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reg_776 = 0x0;
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reg_899 = 0x0;
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if (state->version == SOC7090)
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reg_1280 &= 0x001f;
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else
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reg_1280 &= 0x01ff;
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break;
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case DIB7000P_POWER_ANALOG_ADC:
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/* dem, cfg, iqc, sad, agc */
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reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
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/* nud */
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reg_776 &= ~((1 << 0));
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/* Dout */
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if (state->version != SOC7090)
|
2007-07-27 21:08:51 +08:00
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reg_1280 &= ~((1 << 11));
|
2011-01-04 15:54:31 +08:00
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reg_1280 &= ~(1 << 6);
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/* fall through wanted to enable the interfaces */
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2007-07-27 21:08:51 +08:00
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2006-10-18 19:34:16 +08:00
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/* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
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2011-01-04 15:54:31 +08:00
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case DIB7000P_POWER_INTERFACE_ONLY: /* TODO power up either SDIO or I2C */
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if (state->version == SOC7090)
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reg_1280 &= ~((1 << 7) | (1 << 5));
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else
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2006-10-18 19:34:16 +08:00
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|
|
reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
|
2011-01-04 15:54:31 +08:00
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
/* TODO following stuff is just converted from the dib7000-driver - check when is used what */
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 774, reg_774);
|
|
|
|
dib7000p_write_word(state, 775, reg_775);
|
|
|
|
dib7000p_write_word(state, 776, reg_776);
|
|
|
|
dib7000p_write_word(state, 899, reg_899);
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_write_word(state, 1280, reg_1280);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
|
|
|
|
{
|
2011-01-04 15:54:31 +08:00
|
|
|
u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909);
|
|
|
|
u16 reg;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
switch (no) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case DIBX000_SLOW_ADC_ON:
|
|
|
|
if (state->version == SOC7090) {
|
|
|
|
reg = dib7000p_read_word(state, 1925);
|
|
|
|
|
|
|
|
dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2)); /* en_slowAdc = 1 & reset_sladc = 1 */
|
|
|
|
|
|
|
|
reg = dib7000p_read_word(state, 1925); /* read acces to make it works... strange ... */
|
|
|
|
msleep(200);
|
|
|
|
dib7000p_write_word(state, 1925, reg & ~(1 << 4)); /* en_slowAdc = 1 & reset_sladc = 0 */
|
|
|
|
|
|
|
|
reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
|
|
|
|
dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524); /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
|
|
|
|
} else {
|
2006-10-18 19:34:16 +08:00
|
|
|
reg_909 |= (1 << 1) | (1 << 0);
|
|
|
|
dib7000p_write_word(state, 909, reg_909);
|
|
|
|
reg_909 &= ~(1 << 1);
|
2011-01-04 15:54:31 +08:00
|
|
|
}
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case DIBX000_SLOW_ADC_OFF:
|
|
|
|
if (state->version == SOC7090) {
|
|
|
|
reg = dib7000p_read_word(state, 1925);
|
|
|
|
dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
|
|
|
|
} else
|
|
|
|
reg_909 |= (1 << 1) | (1 << 0);
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case DIBX000_ADC_ON:
|
|
|
|
reg_908 &= 0x0fff;
|
|
|
|
reg_909 &= 0x0003;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
case DIBX000_ADC_OFF:
|
2011-01-04 15:54:31 +08:00
|
|
|
reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
|
|
|
|
reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case DIBX000_VBG_ENABLE:
|
|
|
|
reg_908 &= ~(1 << 15);
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case DIBX000_VBG_DISABLE:
|
|
|
|
reg_908 |= (1 << 15);
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
default:
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
// dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2010-09-07 23:50:46 +08:00
|
|
|
reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
|
2010-09-07 23:50:45 +08:00
|
|
|
reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_write_word(state, 908, reg_908);
|
|
|
|
dib7000p_write_word(state, 909, reg_909);
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
u32 timf;
|
|
|
|
|
|
|
|
// store the current bandwidth for later use
|
2007-07-27 21:08:51 +08:00
|
|
|
state->current_bandwidth = bw;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
if (state->timf == 0) {
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("using default timf");
|
2006-10-18 19:34:16 +08:00
|
|
|
timf = state->cfg.bw->timf;
|
|
|
|
} else {
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("using updated timf");
|
2006-10-18 19:34:16 +08:00
|
|
|
timf = state->timf;
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
timf = timf * (bw / 50) / 160;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7000p_sad_calib(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
/* internal */
|
|
|
|
dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
|
2011-01-04 15:54:31 +08:00
|
|
|
|
|
|
|
if (state->version == SOC7090)
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 74, 2048);
|
2011-01-04 15:54:31 +08:00
|
|
|
else
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 74, 776);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* do the calibration */
|
|
|
|
dib7000p_write_word(state, 73, (1 << 0));
|
|
|
|
dib7000p_write_word(state, 73, (0 << 0));
|
|
|
|
|
|
|
|
msleep(1);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-30 23:49:04 +08:00
|
|
|
int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
|
|
|
if (value > 4095)
|
|
|
|
value = 4095;
|
|
|
|
state->wbd_ref = value;
|
|
|
|
return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_set_wbd_ref);
|
2011-01-04 15:54:31 +08:00
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
static void dib7000p_reset_pll(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
|
2007-07-27 21:08:51 +08:00
|
|
|
u16 clk_cfg0;
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090) {
|
|
|
|
dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
|
|
|
|
;
|
2011-01-04 15:54:31 +08:00
|
|
|
|
|
|
|
dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
|
|
|
|
} else {
|
|
|
|
/* force PLL bypass */
|
|
|
|
clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
|
|
|
|
(bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 900, clk_cfg0);
|
|
|
|
|
|
|
|
/* P_pll_cfg */
|
|
|
|
dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
|
|
|
|
clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
|
|
|
|
dib7000p_write_word(state, 900, clk_cfg0);
|
|
|
|
}
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
dib7000p_write_word(state, 72, bw->sad_cfg);
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
|
|
|
|
internal |= (u32) dib7000p_read_word(state, 19);
|
|
|
|
internal /= 1000;
|
|
|
|
|
|
|
|
return internal;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
|
|
|
|
u8 loopdiv, prediv;
|
|
|
|
u32 internal, xtal;
|
|
|
|
|
|
|
|
/* get back old values */
|
|
|
|
prediv = reg_1856 & 0x3f;
|
|
|
|
loopdiv = (reg_1856 >> 6) & 0x3f;
|
|
|
|
|
|
|
|
if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
|
|
|
|
dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
|
|
|
|
reg_1856 &= 0xf000;
|
|
|
|
reg_1857 = dib7000p_read_word(state, 1857);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
|
2011-01-04 15:54:31 +08:00
|
|
|
|
|
|
|
dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
|
|
|
|
|
|
|
|
/* write new system clk into P_sec_len */
|
|
|
|
internal = dib7000p_get_internal_freq(state);
|
|
|
|
xtal = (internal / loopdiv) * prediv;
|
|
|
|
internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */
|
|
|
|
dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
|
2011-01-04 15:54:31 +08:00
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("Waiting for PLL to lock");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_update_pll);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
static int dib7000p_reset_gpio(struct dib7000p_state *st)
|
|
|
|
{
|
|
|
|
/* reset the GPIOs */
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
dib7000p_write_word(st, 1029, st->gpio_dir);
|
|
|
|
dib7000p_write_word(st, 1030, st->gpio_val);
|
|
|
|
|
|
|
|
/* TODO 1031 is P_gpio_od */
|
|
|
|
|
|
|
|
dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
|
|
|
|
|
|
|
|
dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-30 23:49:04 +08:00
|
|
|
static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
|
|
|
|
{
|
|
|
|
st->gpio_dir = dib7000p_read_word(st, 1029);
|
2011-01-04 15:54:31 +08:00
|
|
|
st->gpio_dir &= ~(1 << num); /* reset the direction bit */
|
|
|
|
st->gpio_dir |= (dir & 0x1) << num; /* set the new direction */
|
2007-07-30 23:49:04 +08:00
|
|
|
dib7000p_write_word(st, 1029, st->gpio_dir);
|
|
|
|
|
|
|
|
st->gpio_val = dib7000p_read_word(st, 1030);
|
2011-01-04 15:54:31 +08:00
|
|
|
st->gpio_val &= ~(1 << num); /* reset the direction bit */
|
|
|
|
st->gpio_val |= (val & 0x01) << num; /* set the new value */
|
2007-07-30 23:49:04 +08:00
|
|
|
dib7000p_write_word(st, 1030, st->gpio_val);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
|
|
|
return dib7000p_cfg_gpio(state, num, dir, val);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_set_gpio);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static u16 dib7000p_defaults[] = {
|
2007-07-27 21:08:51 +08:00
|
|
|
// auto search configuration
|
|
|
|
3, 2,
|
2011-01-04 15:54:31 +08:00
|
|
|
0x0004,
|
|
|
|
0x1000,
|
|
|
|
0x0814, /* Equal Lock */
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
12, 6,
|
2011-01-04 15:54:31 +08:00
|
|
|
0x001b,
|
|
|
|
0x7740,
|
|
|
|
0x005b,
|
|
|
|
0x8d80,
|
|
|
|
0x01c9,
|
|
|
|
0xc380,
|
|
|
|
0x0000,
|
|
|
|
0x0080,
|
|
|
|
0x0000,
|
|
|
|
0x0090,
|
|
|
|
0x0001,
|
|
|
|
0xd4c0,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 26,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x6680,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
/* set ADC level to -16 */
|
|
|
|
11, 79,
|
2011-01-04 15:54:31 +08:00
|
|
|
(1 << 13) - 825 - 117,
|
|
|
|
(1 << 13) - 837 - 117,
|
|
|
|
(1 << 13) - 811 - 117,
|
|
|
|
(1 << 13) - 766 - 117,
|
|
|
|
(1 << 13) - 737 - 117,
|
|
|
|
(1 << 13) - 693 - 117,
|
|
|
|
(1 << 13) - 648 - 117,
|
|
|
|
(1 << 13) - 619 - 117,
|
|
|
|
(1 << 13) - 575 - 117,
|
|
|
|
(1 << 13) - 531 - 117,
|
|
|
|
(1 << 13) - 501 - 117,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 142,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x0410,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
/* disable power smoothing */
|
|
|
|
8, 145,
|
2011-01-04 15:54:31 +08:00
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
|
|
|
0,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 154,
|
2011-01-05 00:08:14 +08:00
|
|
|
1 << 13,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 168,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x0ccd,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 183,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x200f,
|
2011-01-04 15:54:31 +08:00
|
|
|
|
|
|
|
1, 212,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x169,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
5, 187,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x023d,
|
|
|
|
0x00a4,
|
|
|
|
0x00a4,
|
|
|
|
0x7ff0,
|
|
|
|
0x3ccc,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 198,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x800,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 222,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x0010,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 235,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x0062,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
2, 901,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x0006,
|
|
|
|
(3 << 10) | (1 << 6),
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
1, 905,
|
2011-01-05 00:08:14 +08:00
|
|
|
0x2c8e,
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
0,
|
|
|
|
};
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
static int dib7000p_demod_reset(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090)
|
|
|
|
dibx000_reset_i2c_master(&state->i2c_master);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
|
|
|
|
|
|
|
|
/* restart all parts */
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 770, 0xffff);
|
|
|
|
dib7000p_write_word(state, 771, 0xffff);
|
|
|
|
dib7000p_write_word(state, 772, 0x001f);
|
|
|
|
dib7000p_write_word(state, 898, 0x0003);
|
|
|
|
dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
|
|
|
|
|
|
|
|
dib7000p_write_word(state, 770, 0);
|
|
|
|
dib7000p_write_word(state, 771, 0);
|
|
|
|
dib7000p_write_word(state, 772, 0);
|
|
|
|
dib7000p_write_word(state, 898, 0);
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_write_word(state, 1280, 0);
|
|
|
|
|
|
|
|
/* default */
|
|
|
|
dib7000p_reset_pll(state);
|
|
|
|
|
|
|
|
if (dib7000p_reset_gpio(state) != 0)
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("GPIO reset was not successful.");
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090) {
|
|
|
|
dib7000p_write_word(state, 899, 0);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
/* impulse noise */
|
|
|
|
dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
|
|
|
|
dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
|
|
|
|
dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 273, (1<<6) | 30);
|
2011-01-04 15:54:31 +08:00
|
|
|
}
|
|
|
|
if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
|
|
|
|
dprintk("OUTPUT_MODE could not be reset.");
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
|
|
|
|
dib7000p_sad_calib(state);
|
|
|
|
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
/* unforce divstr regardless whether i2c enumeration was done or not */
|
|
|
|
dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
|
|
|
|
|
|
|
|
dib7000p_set_bandwidth(state, 8000);
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
if (state->version == SOC7090) {
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
|
2011-01-05 00:08:14 +08:00
|
|
|
} else {
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->cfg.tuner_is_baseband)
|
|
|
|
dib7000p_write_word(state, 36, 0x0755);
|
|
|
|
else
|
|
|
|
dib7000p_write_word(state, 36, 0x1f55);
|
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
dib7000p_write_tab(state, dib7000p_defaults);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
u16 tmp = 0;
|
|
|
|
tmp = dib7000p_read_word(state, 903);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 903, (tmp | 0x1));
|
2007-07-27 21:08:51 +08:00
|
|
|
tmp = dib7000p_read_word(state, 900);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
static void dib7000p_restart_agc(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
// P_restart_iqc & P_restart_agc
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_write_word(state, 770, 0x0000);
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static int dib7000p_update_lna(struct dib7000p_state *state)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
u16 dyn_gain;
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
if (state->cfg.update_lna) {
|
2006-10-18 19:34:16 +08:00
|
|
|
dyn_gain = dib7000p_read_word(state, 394);
|
2011-01-05 00:08:14 +08:00
|
|
|
if (state->cfg.update_lna(&state->demod, dyn_gain)) {
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_restart_agc(state);
|
2007-07-27 21:08:51 +08:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
|
|
|
|
{
|
|
|
|
struct dibx000_agc_config *agc = NULL;
|
|
|
|
int i;
|
|
|
|
if (state->current_band == band && state->current_agc != NULL)
|
|
|
|
return 0;
|
|
|
|
state->current_band = band;
|
|
|
|
|
|
|
|
for (i = 0; i < state->cfg.agc_config_count; i++)
|
|
|
|
if (state->cfg.agc[i].band_caps & band) {
|
|
|
|
agc = &state->cfg.agc[i];
|
2006-10-18 19:34:16 +08:00
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (agc == NULL) {
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("no valid AGC configuration found for band 0x%02x", band);
|
2007-07-27 21:08:51 +08:00
|
|
|
return -EINVAL;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
state->current_agc = agc;
|
|
|
|
|
|
|
|
/* AGC */
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 75, agc->setup);
|
|
|
|
dib7000p_write_word(state, 76, agc->inv_gain);
|
|
|
|
dib7000p_write_word(state, 77, agc->time_stabiliz);
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
|
|
|
|
|
|
|
|
// Demod AGC loop configuration
|
|
|
|
dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
/* AGC continued */
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
|
2007-07-27 21:08:51 +08:00
|
|
|
state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
|
|
|
|
|
|
|
|
if (state->wbd_ref != 0)
|
|
|
|
dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
|
|
|
|
else
|
|
|
|
dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
|
|
|
|
|
|
|
|
dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 107, agc->agc1_max);
|
|
|
|
dib7000p_write_word(state, 108, agc->agc1_min);
|
|
|
|
dib7000p_write_word(state, 109, agc->agc2_max);
|
|
|
|
dib7000p_write_word(state, 110, agc->agc2_min);
|
|
|
|
dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
|
|
|
|
dib7000p_write_word(state, 112, agc->agc1_pt3);
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
|
|
|
|
return 0;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
|
|
|
|
{
|
|
|
|
u32 internal = dib7000p_get_internal_freq(state);
|
|
|
|
s32 unit_khz_dds_val = 67108864 / (internal); /* 2**26 / Fsampling is the unit 1KHz offset */
|
|
|
|
u32 abs_offset_khz = ABS(offset_khz);
|
|
|
|
u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
|
|
|
|
u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
|
|
|
|
|
|
|
|
dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
|
|
|
|
|
|
|
|
if (offset_khz < 0)
|
|
|
|
unit_khz_dds_val *= -1;
|
|
|
|
|
|
|
|
/* IF tuner */
|
|
|
|
if (invert)
|
|
|
|
dds -= (abs_offset_khz * unit_khz_dds_val); /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
|
|
|
|
else
|
|
|
|
dds += (abs_offset_khz * unit_khz_dds_val);
|
|
|
|
|
|
|
|
if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
|
|
|
|
dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
|
|
|
|
dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
2007-07-27 21:08:51 +08:00
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
|
|
|
int ret = -1;
|
|
|
|
u8 *agc_state = &state->agc_state;
|
|
|
|
u8 agc_split;
|
2011-01-04 15:54:31 +08:00
|
|
|
u16 reg;
|
|
|
|
u32 upd_demod_gain_period = 0x1000;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
switch (state->agc_state) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case 0:
|
|
|
|
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
|
|
|
|
if (state->version == SOC7090) {
|
|
|
|
reg = dib7000p_read_word(state, 0x79b) & 0xff00;
|
|
|
|
dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF); /* lsb */
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
|
2011-01-04 15:54:31 +08:00
|
|
|
|
|
|
|
/* enable adc i & q */
|
|
|
|
reg = dib7000p_read_word(state, 0x780);
|
|
|
|
dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
|
|
|
|
} else {
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_set_adc_state(state, DIBX000_ADC_ON);
|
|
|
|
dib7000p_pll_clk_cfg(state);
|
2011-01-04 15:54:31 +08:00
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
|
|
|
|
return -1;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_set_dds(state, 0);
|
|
|
|
ret = 7;
|
|
|
|
(*agc_state)++;
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case 1:
|
|
|
|
if (state->cfg.agc_control)
|
|
|
|
state->cfg.agc_control(&state->demod, 1);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 78, 32768);
|
|
|
|
if (!state->current_agc->perform_agc_softsplit) {
|
|
|
|
/* we are using the wbd - so slow AGC startup */
|
|
|
|
/* force 0 split on WBD and restart AGC */
|
|
|
|
dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
|
2007-07-27 21:08:51 +08:00
|
|
|
(*agc_state)++;
|
2011-01-04 15:54:31 +08:00
|
|
|
ret = 5;
|
|
|
|
} else {
|
|
|
|
/* default AGC startup */
|
|
|
|
(*agc_state) = 4;
|
|
|
|
/* wait AGC rough lock time */
|
|
|
|
ret = 7;
|
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_restart_agc(state);
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case 2: /* fast split search path after 5sec */
|
|
|
|
dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4)); /* freeze AGC loop */
|
|
|
|
dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8)); /* fast split search 0.25kHz */
|
|
|
|
(*agc_state)++;
|
|
|
|
ret = 14;
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case 3: /* split search ended */
|
|
|
|
agc_split = (u8) dib7000p_read_word(state, 396); /* store the split value for the next time */
|
|
|
|
dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 75, state->current_agc->setup); /* std AGC loop */
|
|
|
|
dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_restart_agc(state);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("SPLIT %p: %hd", demod, agc_split);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
(*agc_state)++;
|
|
|
|
ret = 5;
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
case 4: /* LNA startup */
|
|
|
|
ret = 7;
|
|
|
|
|
|
|
|
if (dib7000p_update_lna(state))
|
|
|
|
ret = 5;
|
2011-01-05 00:08:14 +08:00
|
|
|
else
|
2007-07-27 21:08:51 +08:00
|
|
|
(*agc_state)++;
|
2011-01-04 15:54:31 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case 5:
|
|
|
|
if (state->cfg.agc_control)
|
|
|
|
state->cfg.agc_control(&state->demod, 0);
|
|
|
|
(*agc_state)++;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
return ret;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static void dib7000p_update_timf(struct dib7000p_state *state)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
|
2007-07-27 21:08:51 +08:00
|
|
|
state->timf = timf * 160 / (state->current_bandwidth / 50);
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_write_word(state, 23, (u16) (timf >> 16));
|
|
|
|
dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
|
|
|
|
|
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
switch (op) {
|
|
|
|
case DEMOD_TIMF_SET:
|
|
|
|
state->timf = timf;
|
|
|
|
break;
|
|
|
|
case DEMOD_TIMF_UPDATE:
|
|
|
|
dib7000p_update_timf(state);
|
|
|
|
break;
|
|
|
|
case DEMOD_TIMF_GET:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
dib7000p_set_bandwidth(state, state->current_bandwidth);
|
|
|
|
return state->timf;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2011-01-04 15:54:31 +08:00
|
|
|
EXPORT_SYMBOL(dib7000p_ctrl_timf);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
2007-07-27 21:08:51 +08:00
|
|
|
u16 value, est[4];
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* nfft, guard, qam, alpha */
|
2007-07-27 21:08:51 +08:00
|
|
|
value = 0;
|
|
|
|
switch (ch->u.ofdm.transmission_mode) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case TRANSMISSION_MODE_2K:
|
|
|
|
value |= (0 << 7);
|
|
|
|
break;
|
2011-01-16 23:01:20 +08:00
|
|
|
case TRANSMISSION_MODE_4K:
|
2011-01-04 15:54:31 +08:00
|
|
|
value |= (2 << 7);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case TRANSMISSION_MODE_8K:
|
|
|
|
value |= (1 << 7);
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
switch (ch->u.ofdm.guard_interval) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case GUARD_INTERVAL_1_32:
|
|
|
|
value |= (0 << 5);
|
|
|
|
break;
|
|
|
|
case GUARD_INTERVAL_1_16:
|
|
|
|
value |= (1 << 5);
|
|
|
|
break;
|
|
|
|
case GUARD_INTERVAL_1_4:
|
|
|
|
value |= (3 << 5);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case GUARD_INTERVAL_1_8:
|
|
|
|
value |= (2 << 5);
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
switch (ch->u.ofdm.constellation) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case QPSK:
|
|
|
|
value |= (0 << 3);
|
|
|
|
break;
|
|
|
|
case QAM_16:
|
|
|
|
value |= (1 << 3);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case QAM_64:
|
|
|
|
value |= (2 << 3);
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
switch (HIERARCHY_1) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case HIERARCHY_2:
|
|
|
|
value |= 2;
|
|
|
|
break;
|
|
|
|
case HIERARCHY_4:
|
|
|
|
value |= 4;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case HIERARCHY_1:
|
|
|
|
value |= 1;
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
dib7000p_write_word(state, 0, value);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 5, (seq << 4) | 1); /* do not force tps, search list 0 */
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
/* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
|
|
|
|
value = 0;
|
|
|
|
if (1 != 0)
|
|
|
|
value |= (1 << 6);
|
|
|
|
if (ch->u.ofdm.hierarchy_information == 1)
|
|
|
|
value |= (1 << 4);
|
|
|
|
if (1 == 1)
|
|
|
|
value |= 1;
|
|
|
|
switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case FEC_2_3:
|
|
|
|
value |= (2 << 1);
|
|
|
|
break;
|
|
|
|
case FEC_3_4:
|
|
|
|
value |= (3 << 1);
|
|
|
|
break;
|
|
|
|
case FEC_5_6:
|
|
|
|
value |= (5 << 1);
|
|
|
|
break;
|
|
|
|
case FEC_7_8:
|
|
|
|
value |= (7 << 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case FEC_1_2:
|
|
|
|
value |= (1 << 1);
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
dib7000p_write_word(state, 208, value);
|
|
|
|
|
|
|
|
/* offset loop parameters */
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 26, 0x6680);
|
|
|
|
dib7000p_write_word(state, 32, 0x0003);
|
|
|
|
dib7000p_write_word(state, 29, 0x1273);
|
|
|
|
dib7000p_write_word(state, 33, 0x0005);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* P_dvsy_sync_wait */
|
2007-07-27 21:08:51 +08:00
|
|
|
switch (ch->u.ofdm.transmission_mode) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case TRANSMISSION_MODE_8K:
|
|
|
|
value = 256;
|
|
|
|
break;
|
|
|
|
case TRANSMISSION_MODE_4K:
|
|
|
|
value = 128;
|
|
|
|
break;
|
|
|
|
case TRANSMISSION_MODE_2K:
|
|
|
|
default:
|
|
|
|
value = 64;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
switch (ch->u.ofdm.guard_interval) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case GUARD_INTERVAL_1_16:
|
|
|
|
value *= 2;
|
|
|
|
break;
|
|
|
|
case GUARD_INTERVAL_1_8:
|
|
|
|
value *= 4;
|
|
|
|
break;
|
|
|
|
case GUARD_INTERVAL_1_4:
|
|
|
|
value *= 8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case GUARD_INTERVAL_1_32:
|
|
|
|
value *= 1;
|
|
|
|
break;
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
2010-09-07 23:50:46 +08:00
|
|
|
if (state->cfg.diversity_delay == 0)
|
2011-01-05 00:08:14 +08:00
|
|
|
state->div_sync_wait = (value * 3) / 2 + 48;
|
2010-09-07 23:50:46 +08:00
|
|
|
else
|
2011-01-05 00:08:14 +08:00
|
|
|
state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
/* deactive the possibility of diversity reception if extended interleaver */
|
|
|
|
state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
|
|
|
|
dib7000p_set_diversity_in(&state->demod, state->div_state);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* channel estimation fine configuration */
|
2007-07-27 21:08:51 +08:00
|
|
|
switch (ch->u.ofdm.constellation) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case QAM_64:
|
|
|
|
est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */
|
|
|
|
est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */
|
|
|
|
est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
|
|
|
|
est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */
|
|
|
|
break;
|
|
|
|
case QAM_16:
|
|
|
|
est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */
|
|
|
|
est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */
|
|
|
|
est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */
|
|
|
|
est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */
|
|
|
|
est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */
|
|
|
|
est[2] = 0x0333; /* P_adp_regul_ext 0.1 */
|
|
|
|
est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
for (value = 0; value < 4; value++)
|
|
|
|
dib7000p_write_word(state, 187 + value, est[value]);
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
2007-07-27 21:08:51 +08:00
|
|
|
struct dvb_frontend_parameters schan;
|
|
|
|
u32 value, factor;
|
2011-01-04 15:54:31 +08:00
|
|
|
u32 internal = dib7000p_get_internal_freq(state);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
schan = *ch;
|
|
|
|
schan.u.ofdm.constellation = QAM_64;
|
2011-01-04 15:54:31 +08:00
|
|
|
schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
|
|
|
|
schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
|
|
|
|
schan.u.ofdm.code_rate_HP = FEC_2_3;
|
|
|
|
schan.u.ofdm.code_rate_LP = FEC_3_4;
|
|
|
|
schan.u.ofdm.hierarchy_information = 0;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
dib7000p_set_channel(state, &schan, 7);
|
|
|
|
|
|
|
|
factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth);
|
|
|
|
if (factor >= 5000)
|
|
|
|
factor = 1;
|
|
|
|
else
|
|
|
|
factor = 6;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
value = 30 * internal * factor;
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 7, (u16) (value & 0xffff));
|
2011-01-04 15:54:31 +08:00
|
|
|
value = 100 * internal * factor;
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 9, (u16) (value & 0xffff));
|
2011-01-04 15:54:31 +08:00
|
|
|
value = 500 * internal * factor;
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
|
|
|
|
dib7000p_write_word(state, 11, (u16) (value & 0xffff));
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
value = dib7000p_read_word(state, 0);
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_read_word(state, 1284);
|
|
|
|
dib7000p_write_word(state, 0, (u16) value);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
|
|
|
u16 irq_pending = dib7000p_read_word(state, 1284);
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
if (irq_pending & 0x1)
|
2006-10-18 19:34:16 +08:00
|
|
|
return 1;
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
if (irq_pending & 0x2)
|
2006-10-18 19:34:16 +08:00
|
|
|
return 2;
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
return 0;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
|
|
|
|
{
|
2011-01-04 15:54:31 +08:00
|
|
|
static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
|
|
|
|
static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
|
|
|
|
24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
|
|
|
|
53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
|
|
|
|
82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
|
|
|
|
107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
|
|
|
|
128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
|
|
|
|
147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
|
|
|
|
166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
|
|
|
|
183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
|
|
|
|
199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
|
|
|
|
213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
|
|
|
|
225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
|
|
|
|
235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
|
|
|
|
244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
|
|
|
|
250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
|
|
|
|
254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
|
|
|
|
255, 255, 255, 255, 255, 255
|
|
|
|
};
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
u32 xtal = state->cfg.bw->xtal_hz / 1000;
|
2009-08-02 03:48:41 +08:00
|
|
|
int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
|
2007-07-27 21:08:51 +08:00
|
|
|
int k;
|
2011-01-04 15:54:31 +08:00
|
|
|
int coef_re[8], coef_im[8];
|
2007-07-27 21:08:51 +08:00
|
|
|
int bw_khz = bw;
|
|
|
|
u32 pha;
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
|
2007-07-27 21:08:51 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
bw_khz /= 100;
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 142, 0x0610);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
for (k = 0; k < 8; k++) {
|
2011-01-04 15:54:31 +08:00
|
|
|
pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (pha == 0) {
|
2007-07-27 21:08:51 +08:00
|
|
|
coef_re[k] = 256;
|
|
|
|
coef_im[k] = 0;
|
2011-01-04 15:54:31 +08:00
|
|
|
} else if (pha < 256) {
|
|
|
|
coef_re[k] = sine[256 - (pha & 0xff)];
|
|
|
|
coef_im[k] = sine[pha & 0xff];
|
2007-07-27 21:08:51 +08:00
|
|
|
} else if (pha == 256) {
|
|
|
|
coef_re[k] = 0;
|
|
|
|
coef_im[k] = 256;
|
|
|
|
} else if (pha < 512) {
|
2011-01-04 15:54:31 +08:00
|
|
|
coef_re[k] = -sine[pha & 0xff];
|
|
|
|
coef_im[k] = sine[256 - (pha & 0xff)];
|
2007-07-27 21:08:51 +08:00
|
|
|
} else if (pha == 512) {
|
|
|
|
coef_re[k] = -256;
|
|
|
|
coef_im[k] = 0;
|
|
|
|
} else if (pha < 768) {
|
2011-01-04 15:54:31 +08:00
|
|
|
coef_re[k] = -sine[256 - (pha & 0xff)];
|
|
|
|
coef_im[k] = -sine[pha & 0xff];
|
2007-07-27 21:08:51 +08:00
|
|
|
} else if (pha == 768) {
|
|
|
|
coef_re[k] = 0;
|
|
|
|
coef_im[k] = -256;
|
|
|
|
} else {
|
2011-01-04 15:54:31 +08:00
|
|
|
coef_re[k] = sine[pha & 0xff];
|
|
|
|
coef_im[k] = -sine[256 - (pha & 0xff)];
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
coef_re[k] *= notch[k];
|
2011-01-04 15:54:31 +08:00
|
|
|
coef_re[k] += (1 << 14);
|
|
|
|
if (coef_re[k] >= (1 << 24))
|
|
|
|
coef_re[k] = (1 << 24) - 1;
|
|
|
|
coef_re[k] /= (1 << 15);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
coef_im[k] *= notch[k];
|
2011-01-04 15:54:31 +08:00
|
|
|
coef_im[k] += (1 << 14);
|
|
|
|
if (coef_im[k] >= (1 << 24))
|
|
|
|
coef_im[k] = (1 << 24) - 1;
|
|
|
|
coef_im[k] /= (1 << 15);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
|
|
|
|
dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
|
|
|
|
dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
|
|
|
|
}
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 143, 0);
|
2007-07-27 21:08:51 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
|
|
|
u16 tmp = 0;
|
|
|
|
|
|
|
|
if (ch != NULL)
|
|
|
|
dib7000p_set_channel(state, ch, 0);
|
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
// restart demod
|
|
|
|
dib7000p_write_word(state, 770, 0x4000);
|
|
|
|
dib7000p_write_word(state, 770, 0x0000);
|
|
|
|
msleep(45);
|
|
|
|
|
|
|
|
/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
|
2007-07-31 18:09:30 +08:00
|
|
|
tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
|
|
|
|
if (state->sfn_workaround_active) {
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("SFN workaround is active");
|
2007-07-31 18:09:30 +08:00
|
|
|
tmp |= (1 << 9);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 166, 0x4000);
|
2007-07-31 18:09:30 +08:00
|
|
|
} else {
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 166, 0x0000);
|
2007-07-31 18:09:30 +08:00
|
|
|
}
|
|
|
|
dib7000p_write_word(state, 29, tmp);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
// never achieved a lock with that bandwidth so far - wait for osc-freq to update
|
|
|
|
if (state->timf == 0)
|
|
|
|
msleep(200);
|
|
|
|
|
|
|
|
/* offset loop parameters */
|
|
|
|
|
|
|
|
/* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
|
|
|
|
tmp = (6 << 8) | 0x80;
|
2007-07-27 21:08:51 +08:00
|
|
|
switch (ch->u.ofdm.transmission_mode) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case TRANSMISSION_MODE_2K:
|
|
|
|
tmp |= (2 << 12);
|
|
|
|
break;
|
2011-01-16 23:01:20 +08:00
|
|
|
case TRANSMISSION_MODE_4K:
|
2011-01-04 15:54:31 +08:00
|
|
|
tmp |= (3 << 12);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case TRANSMISSION_MODE_8K:
|
|
|
|
tmp |= (4 << 12);
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 26, tmp); /* timf_a(6xxx) */
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
|
|
|
|
tmp = (0 << 4);
|
2007-07-27 21:08:51 +08:00
|
|
|
switch (ch->u.ofdm.transmission_mode) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case TRANSMISSION_MODE_2K:
|
|
|
|
tmp |= 0x6;
|
|
|
|
break;
|
2011-01-16 23:01:20 +08:00
|
|
|
case TRANSMISSION_MODE_4K:
|
2011-01-04 15:54:31 +08:00
|
|
|
tmp |= 0x7;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case TRANSMISSION_MODE_8K:
|
|
|
|
tmp |= 0x8;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 32, tmp);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
|
|
|
|
tmp = (0 << 4);
|
2007-07-27 21:08:51 +08:00
|
|
|
switch (ch->u.ofdm.transmission_mode) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case TRANSMISSION_MODE_2K:
|
|
|
|
tmp |= 0x6;
|
|
|
|
break;
|
|
|
|
case TRANSMISSION_MODE_4K:
|
|
|
|
tmp |= 0x7;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case TRANSMISSION_MODE_8K:
|
|
|
|
tmp |= 0x8;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 33, tmp);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
tmp = dib7000p_read_word(state, 509);
|
2006-10-18 19:34:16 +08:00
|
|
|
if (!((tmp >> 6) & 0x1)) {
|
|
|
|
/* restart the fec */
|
2011-01-04 15:54:31 +08:00
|
|
|
tmp = dib7000p_read_word(state, 771);
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_write_word(state, 771, tmp | (1 << 1));
|
|
|
|
dib7000p_write_word(state, 771, tmp);
|
2011-01-04 15:54:31 +08:00
|
|
|
msleep(40);
|
|
|
|
tmp = dib7000p_read_word(state, 509);
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
// we achieved a lock - it's time to update the osc freq
|
2011-01-04 15:54:31 +08:00
|
|
|
if ((tmp >> 6) & 0x1) {
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_update_timf(state);
|
2011-01-04 15:54:31 +08:00
|
|
|
/* P_timf_alpha += 2 */
|
|
|
|
tmp = dib7000p_read_word(state, 26);
|
|
|
|
dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
|
|
|
|
}
|
2007-07-27 21:08:51 +08:00
|
|
|
|
|
|
|
if (state->cfg.spur_protect)
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
|
2006-10-18 19:34:16 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
static int dib7000p_wakeup(struct dvb_frontend *demod)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
|
|
|
dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
|
|
|
|
dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090)
|
|
|
|
dib7000p_sad_calib(state);
|
2007-07-27 21:08:51 +08:00
|
|
|
return 0;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7000p_sleep(struct dvb_frontend *demod)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = demod->demodulator_priv;
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090)
|
|
|
|
return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
|
2006-10-18 19:34:16 +08:00
|
|
|
return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7000p_identify(struct dib7000p_state *st)
|
|
|
|
{
|
|
|
|
u16 value;
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("wrong Vendor ID (read=0x%x)", value);
|
2006-10-18 19:34:16 +08:00
|
|
|
return -EREMOTEIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("wrong Device ID (%x)", value);
|
2006-10-18 19:34:16 +08:00
|
|
|
return -EREMOTEIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
2011-01-04 15:54:31 +08:00
|
|
|
u16 tps = dib7000p_read_word(state, 463);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
fep->inversion = INVERSION_AUTO;
|
|
|
|
|
2008-01-25 18:31:58 +08:00
|
|
|
fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
switch ((tps >> 8) & 0x3) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case 0:
|
|
|
|
fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
|
|
|
|
break;
|
2011-01-16 23:01:20 +08:00
|
|
|
/* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (tps & 0x3) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case 0:
|
|
|
|
fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
switch ((tps >> 14) & 0x3) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case 0:
|
|
|
|
fep->u.ofdm.constellation = QPSK;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
fep->u.ofdm.constellation = QAM_16;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
default:
|
|
|
|
fep->u.ofdm.constellation = QAM_64;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
|
|
|
|
/* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
|
|
|
|
|
|
|
|
fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
|
|
|
|
switch ((tps >> 5) & 0x7) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case 1:
|
|
|
|
fep->u.ofdm.code_rate_HP = FEC_1_2;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
fep->u.ofdm.code_rate_HP = FEC_2_3;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
fep->u.ofdm.code_rate_HP = FEC_3_4;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
fep->u.ofdm.code_rate_HP = FEC_5_6;
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
default:
|
|
|
|
fep->u.ofdm.code_rate_HP = FEC_7_8;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
switch ((tps >> 2) & 0x7) {
|
2011-01-04 15:54:31 +08:00
|
|
|
case 1:
|
|
|
|
fep->u.ofdm.code_rate_LP = FEC_1_2;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
fep->u.ofdm.code_rate_LP = FEC_2_3;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
fep->u.ofdm.code_rate_LP = FEC_3_4;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
fep->u.ofdm.code_rate_LP = FEC_5_6;
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
default:
|
|
|
|
fep->u.ofdm.code_rate_LP = FEC_7_8;
|
|
|
|
break;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* native interleaver: (dib7000p_read_word(state, 464) >> 5) & 0x1 */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
2008-01-25 17:27:06 +08:00
|
|
|
int time, ret;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090) {
|
|
|
|
dib7090_set_diversity_in(fe, 0);
|
|
|
|
dib7090_set_output_mode(fe, OUTMODE_HIGH_Z);
|
2011-01-05 00:08:14 +08:00
|
|
|
} else
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
/* maybe the parameter has been changed */
|
2007-07-31 18:09:30 +08:00
|
|
|
state->sfn_workaround_active = buggy_sfn_workaround;
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
if (fe->ops.tuner_ops.set_params)
|
|
|
|
fe->ops.tuner_ops.set_params(fe, fep);
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
/* start up the AGC */
|
|
|
|
state->agc_state = 0;
|
|
|
|
do {
|
|
|
|
time = dib7000p_agc_startup(fe, fep);
|
|
|
|
if (time != -1)
|
|
|
|
msleep(time);
|
|
|
|
} while (time != -1);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
|
2011-01-04 15:54:31 +08:00
|
|
|
fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
|
2006-10-18 19:34:16 +08:00
|
|
|
int i = 800, found;
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
dib7000p_autosearch_start(fe, fep);
|
2006-10-18 19:34:16 +08:00
|
|
|
do {
|
|
|
|
msleep(1);
|
|
|
|
found = dib7000p_autosearch_is_irq(fe);
|
|
|
|
} while (found == 0 && i--);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("autosearch returns: %d", found);
|
2006-10-18 19:34:16 +08:00
|
|
|
if (found == 0 || found == 1)
|
2011-01-05 00:08:14 +08:00
|
|
|
return 0;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
dib7000p_get_frontend(fe, fep);
|
|
|
|
}
|
|
|
|
|
2008-01-25 17:27:06 +08:00
|
|
|
ret = dib7000p_tune(fe, fep);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
/* make this a config parameter */
|
2011-01-04 15:54:31 +08:00
|
|
|
if (state->version == SOC7090)
|
|
|
|
dib7090_set_output_mode(fe, state->cfg.output_mode);
|
|
|
|
else
|
|
|
|
dib7000p_set_output_mode(state, state->cfg.output_mode);
|
|
|
|
|
|
|
|
return ret;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u16 lock = dib7000p_read_word(state, 509);
|
|
|
|
|
|
|
|
*stat = 0;
|
|
|
|
|
|
|
|
if (lock & 0x8000)
|
|
|
|
*stat |= FE_HAS_SIGNAL;
|
|
|
|
if (lock & 0x3000)
|
|
|
|
*stat |= FE_HAS_CARRIER;
|
|
|
|
if (lock & 0x0100)
|
|
|
|
*stat |= FE_HAS_VITERBI;
|
|
|
|
if (lock & 0x0010)
|
|
|
|
*stat |= FE_HAS_SYNC;
|
2011-01-04 15:54:31 +08:00
|
|
|
if ((lock & 0x0038) == 0x38)
|
2006-10-18 19:34:16 +08:00
|
|
|
*stat |= FE_HAS_LOCK;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
*ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
*unc = dib7000p_read_word(state, 506);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u16 val = dib7000p_read_word(state, 394);
|
|
|
|
*strength = 65535 - val;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
2009-09-15 17:46:52 +08:00
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u16 val;
|
|
|
|
s32 signal_mant, signal_exp, noise_mant, noise_exp;
|
|
|
|
u32 result = 0;
|
|
|
|
|
|
|
|
val = dib7000p_read_word(state, 479);
|
|
|
|
noise_mant = (val >> 4) & 0xff;
|
|
|
|
noise_exp = ((val & 0xf) << 2);
|
|
|
|
val = dib7000p_read_word(state, 480);
|
|
|
|
noise_exp += ((val >> 14) & 0x3);
|
|
|
|
if ((noise_exp & 0x20) != 0)
|
|
|
|
noise_exp -= 0x40;
|
|
|
|
|
|
|
|
signal_mant = (val >> 6) & 0xFF;
|
2011-01-04 15:54:31 +08:00
|
|
|
signal_exp = (val & 0x3F);
|
2009-09-15 17:46:52 +08:00
|
|
|
if ((signal_exp & 0x20) != 0)
|
|
|
|
signal_exp -= 0x40;
|
|
|
|
|
|
|
|
if (signal_mant != 0)
|
2011-01-04 15:54:31 +08:00
|
|
|
result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
|
2009-09-15 17:46:52 +08:00
|
|
|
else
|
|
|
|
result = intlog10(2) * 10 * signal_exp - 100;
|
|
|
|
|
|
|
|
if (noise_mant != 0)
|
2011-01-04 15:54:31 +08:00
|
|
|
result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
|
2009-09-15 17:46:52 +08:00
|
|
|
else
|
|
|
|
result -= intlog10(2) * 10 * noise_exp - 100;
|
|
|
|
|
|
|
|
*snr = result / ((1 << 24) / 10);
|
2006-10-18 19:34:16 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
tune->min_delay_ms = 1000;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dib7000p_release(struct dvb_frontend *demod)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *st = demod->demodulator_priv;
|
|
|
|
dibx000_exit_i2c_master(&st->i2c_master);
|
2011-01-04 15:54:31 +08:00
|
|
|
i2c_del_adapter(&st->dib7090_tuner_adap);
|
2006-10-18 19:34:16 +08:00
|
|
|
kfree(st);
|
|
|
|
}
|
|
|
|
|
|
|
|
int dib7000pc_detection(struct i2c_adapter *i2c_adap)
|
|
|
|
{
|
2011-05-03 23:27:33 +08:00
|
|
|
u8 *tx, *rx;
|
2006-10-18 19:34:16 +08:00
|
|
|
struct i2c_msg msg[2] = {
|
2011-05-03 23:27:33 +08:00
|
|
|
{.addr = 18 >> 1, .flags = 0, .len = 2},
|
|
|
|
{.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
|
2006-10-18 19:34:16 +08:00
|
|
|
};
|
2011-05-03 23:27:33 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
tx = kzalloc(2*sizeof(u8), GFP_KERNEL);
|
|
|
|
if (!tx)
|
|
|
|
return -ENOMEM;
|
|
|
|
rx = kzalloc(2*sizeof(u8), GFP_KERNEL);
|
|
|
|
if (!rx) {
|
|
|
|
goto rx_memory_error;
|
|
|
|
ret = -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
msg[0].buf = tx;
|
|
|
|
msg[1].buf = rx;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
tx[0] = 0x03;
|
|
|
|
tx[1] = 0x00;
|
|
|
|
|
|
|
|
if (i2c_transfer(i2c_adap, msg, 2) == 2)
|
|
|
|
if (rx[0] == 0x01 && rx[1] == 0xb3) {
|
2007-07-27 21:08:51 +08:00
|
|
|
dprintk("-D- DiB7000PC detected");
|
2006-10-18 19:34:16 +08:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
msg[0].addr = msg[1].addr = 0x40;
|
|
|
|
|
|
|
|
if (i2c_transfer(i2c_adap, msg, 2) == 2)
|
|
|
|
if (rx[0] == 0x01 && rx[1] == 0xb3) {
|
2007-07-27 21:08:51 +08:00
|
|
|
dprintk("-D- DiB7000PC detected");
|
2006-10-18 19:34:16 +08:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
dprintk("-D- DiB7000PC not detected");
|
2011-05-03 23:27:33 +08:00
|
|
|
|
|
|
|
kfree(rx);
|
|
|
|
rx_memory_error:
|
|
|
|
kfree(tx);
|
|
|
|
return ret;
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000pc_detection);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dib7000p_state *st = demod->demodulator_priv;
|
|
|
|
return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_get_i2c_master);
|
|
|
|
|
2009-09-18 15:08:43 +08:00
|
|
|
int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
|
|
|
|
{
|
2011-01-04 15:54:31 +08:00
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u16 val = dib7000p_read_word(state, 235) & 0xffef;
|
|
|
|
val |= (onoff & 0x1) << 4;
|
|
|
|
dprintk("PID filter enabled %d", onoff);
|
|
|
|
return dib7000p_write_word(state, 235, val);
|
2009-09-18 15:08:43 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
|
|
|
|
|
|
|
|
int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
|
|
|
|
{
|
2011-01-04 15:54:31 +08:00
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
|
|
|
|
return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
|
2009-09-18 15:08:43 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_pid_filter);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
|
|
|
|
{
|
2010-02-09 07:30:44 +08:00
|
|
|
struct dib7000p_state *dpst;
|
2006-10-18 19:34:16 +08:00
|
|
|
int k = 0;
|
|
|
|
u8 new_addr = 0;
|
|
|
|
|
2010-02-09 07:30:44 +08:00
|
|
|
dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
|
|
|
|
if (!dpst)
|
2010-04-28 06:09:45 +08:00
|
|
|
return -ENOMEM;
|
2010-02-09 07:30:44 +08:00
|
|
|
|
|
|
|
dpst->i2c_adap = i2c;
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
for (k = no_of_demods - 1; k >= 0; k--) {
|
2010-02-09 07:30:44 +08:00
|
|
|
dpst->cfg = cfg[k];
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* designated i2c address */
|
2011-01-04 15:54:31 +08:00
|
|
|
if (cfg[k].default_i2c_addr != 0)
|
|
|
|
new_addr = cfg[k].default_i2c_addr + (k << 1);
|
|
|
|
else
|
|
|
|
new_addr = (0x40 + k) << 1;
|
2010-02-09 07:30:44 +08:00
|
|
|
dpst->i2c_addr = new_addr;
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
|
2010-02-09 07:30:44 +08:00
|
|
|
if (dib7000p_identify(dpst) != 0) {
|
|
|
|
dpst->i2c_addr = default_addr;
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(dpst, 1287, 0x0003); /* sram lead in, rdy */
|
2010-02-09 07:30:44 +08:00
|
|
|
if (dib7000p_identify(dpst) != 0) {
|
2006-10-18 19:34:16 +08:00
|
|
|
dprintk("DiB7000P #%d: not identified\n", k);
|
2010-02-09 07:30:44 +08:00
|
|
|
kfree(dpst);
|
2006-10-18 19:34:16 +08:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* start diversity to pull_down div_str - just for i2c-enumeration */
|
2010-02-09 07:30:44 +08:00
|
|
|
dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* set new i2c address and force divstart */
|
2010-02-09 07:30:44 +08:00
|
|
|
dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
2007-07-27 21:08:51 +08:00
|
|
|
dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
for (k = 0; k < no_of_demods; k++) {
|
2010-02-09 07:30:44 +08:00
|
|
|
dpst->cfg = cfg[k];
|
2011-01-04 15:54:31 +08:00
|
|
|
if (cfg[k].default_i2c_addr != 0)
|
|
|
|
dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
|
|
|
|
else
|
|
|
|
dpst->i2c_addr = (0x40 + k) << 1;
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
// unforce divstr
|
2010-02-09 07:30:44 +08:00
|
|
|
dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
|
2006-10-18 19:34:16 +08:00
|
|
|
|
|
|
|
/* deactivate div - it was just for i2c-enumeration */
|
2010-02-09 07:30:44 +08:00
|
|
|
dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
|
2006-10-18 19:34:16 +08:00
|
|
|
}
|
|
|
|
|
2010-02-09 07:30:44 +08:00
|
|
|
kfree(dpst);
|
2006-10-18 19:34:16 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_i2c_enumeration);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
static const s32 lut_1000ln_mant[] = {
|
|
|
|
6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
|
|
|
|
};
|
|
|
|
|
|
|
|
static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u32 tmp_val = 0, exp = 0, mant = 0;
|
|
|
|
s32 pow_i;
|
|
|
|
u16 buf[2];
|
|
|
|
u8 ix = 0;
|
|
|
|
|
|
|
|
buf[0] = dib7000p_read_word(state, 0x184);
|
|
|
|
buf[1] = dib7000p_read_word(state, 0x185);
|
|
|
|
pow_i = (buf[0] << 16) | buf[1];
|
|
|
|
dprintk("raw pow_i = %d", pow_i);
|
|
|
|
|
|
|
|
tmp_val = pow_i;
|
|
|
|
while (tmp_val >>= 1)
|
|
|
|
exp++;
|
|
|
|
|
|
|
|
mant = (pow_i * 1000 / (1 << exp));
|
|
|
|
dprintk(" mant = %d exp = %d", mant / 1000, exp);
|
|
|
|
|
|
|
|
ix = (u8) ((mant - 1000) / 100); /* index of the LUT */
|
|
|
|
dprintk(" ix = %d", ix);
|
|
|
|
|
|
|
|
pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
|
|
|
|
pow_i = (pow_i << 8) / 1000;
|
|
|
|
dprintk(" pow_i = %d", pow_i);
|
|
|
|
|
|
|
|
return pow_i;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int map_addr_to_serpar_number(struct i2c_msg *msg)
|
|
|
|
{
|
|
|
|
if ((msg->buf[0] <= 15))
|
|
|
|
msg->buf[0] -= 1;
|
|
|
|
else if (msg->buf[0] == 17)
|
|
|
|
msg->buf[0] = 15;
|
|
|
|
else if (msg->buf[0] == 16)
|
|
|
|
msg->buf[0] = 17;
|
|
|
|
else if (msg->buf[0] == 19)
|
|
|
|
msg->buf[0] = 16;
|
|
|
|
else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
|
|
|
|
msg->buf[0] -= 3;
|
|
|
|
else if (msg->buf[0] == 28)
|
|
|
|
msg->buf[0] = 23;
|
2011-01-05 00:08:14 +08:00
|
|
|
else
|
2011-01-04 15:54:31 +08:00
|
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
|
|
|
|
u8 n_overflow = 1;
|
|
|
|
u16 i = 1000;
|
|
|
|
u16 serpar_num = msg[0].buf[0];
|
|
|
|
|
|
|
|
while (n_overflow == 1 && i) {
|
|
|
|
n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
|
|
|
|
i--;
|
|
|
|
if (i == 0)
|
|
|
|
dprintk("Tuner ITF: write busy (overflow)");
|
|
|
|
}
|
|
|
|
dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
|
|
|
|
dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
|
|
|
|
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
|
|
|
|
u8 n_overflow = 1, n_empty = 1;
|
|
|
|
u16 i = 1000;
|
|
|
|
u16 serpar_num = msg[0].buf[0];
|
|
|
|
u16 read_word;
|
|
|
|
|
|
|
|
while (n_overflow == 1 && i) {
|
|
|
|
n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
|
|
|
|
i--;
|
|
|
|
if (i == 0)
|
|
|
|
dprintk("TunerITF: read busy (overflow)");
|
|
|
|
}
|
|
|
|
dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
|
|
|
|
|
|
|
|
i = 1000;
|
|
|
|
while (n_empty == 1 && i) {
|
|
|
|
n_empty = dib7000p_read_word(state, 1984) & 0x1;
|
|
|
|
i--;
|
|
|
|
if (i == 0)
|
|
|
|
dprintk("TunerITF: read busy (empty)");
|
|
|
|
}
|
|
|
|
read_word = dib7000p_read_word(state, 1987);
|
|
|
|
msg[1].buf[0] = (read_word >> 8) & 0xff;
|
|
|
|
msg[1].buf[1] = (read_word) & 0xff;
|
|
|
|
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
|
|
|
|
{
|
|
|
|
if (map_addr_to_serpar_number(&msg[0]) == 0) { /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
|
|
|
|
if (num == 1) { /* write */
|
|
|
|
return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
|
|
|
|
} else { /* read */
|
|
|
|
return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
|
|
|
|
u16 word;
|
|
|
|
|
|
|
|
if (num == 1) { /* write */
|
|
|
|
dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
|
|
|
|
} else {
|
|
|
|
word = dib7000p_read_word(state, apb_address);
|
|
|
|
msg[1].buf[0] = (word >> 8) & 0xff;
|
|
|
|
msg[1].buf[1] = (word) & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
|
|
|
|
|
|
|
|
u16 apb_address = 0, word;
|
|
|
|
int i = 0;
|
|
|
|
switch (msg[0].buf[0]) {
|
|
|
|
case 0x12:
|
|
|
|
apb_address = 1920;
|
|
|
|
break;
|
|
|
|
case 0x14:
|
|
|
|
apb_address = 1921;
|
|
|
|
break;
|
|
|
|
case 0x24:
|
|
|
|
apb_address = 1922;
|
|
|
|
break;
|
|
|
|
case 0x1a:
|
|
|
|
apb_address = 1923;
|
|
|
|
break;
|
|
|
|
case 0x22:
|
|
|
|
apb_address = 1924;
|
|
|
|
break;
|
|
|
|
case 0x33:
|
|
|
|
apb_address = 1926;
|
|
|
|
break;
|
|
|
|
case 0x34:
|
|
|
|
apb_address = 1927;
|
|
|
|
break;
|
|
|
|
case 0x35:
|
|
|
|
apb_address = 1928;
|
|
|
|
break;
|
|
|
|
case 0x36:
|
|
|
|
apb_address = 1929;
|
|
|
|
break;
|
|
|
|
case 0x37:
|
|
|
|
apb_address = 1930;
|
|
|
|
break;
|
|
|
|
case 0x38:
|
|
|
|
apb_address = 1931;
|
|
|
|
break;
|
|
|
|
case 0x39:
|
|
|
|
apb_address = 1932;
|
|
|
|
break;
|
|
|
|
case 0x2a:
|
|
|
|
apb_address = 1935;
|
|
|
|
break;
|
|
|
|
case 0x2b:
|
|
|
|
apb_address = 1936;
|
|
|
|
break;
|
|
|
|
case 0x2c:
|
|
|
|
apb_address = 1937;
|
|
|
|
break;
|
|
|
|
case 0x2d:
|
|
|
|
apb_address = 1938;
|
|
|
|
break;
|
|
|
|
case 0x2e:
|
|
|
|
apb_address = 1939;
|
|
|
|
break;
|
|
|
|
case 0x2f:
|
|
|
|
apb_address = 1940;
|
|
|
|
break;
|
|
|
|
case 0x30:
|
|
|
|
apb_address = 1941;
|
|
|
|
break;
|
|
|
|
case 0x31:
|
|
|
|
apb_address = 1942;
|
|
|
|
break;
|
|
|
|
case 0x32:
|
|
|
|
apb_address = 1943;
|
|
|
|
break;
|
|
|
|
case 0x3e:
|
|
|
|
apb_address = 1944;
|
|
|
|
break;
|
|
|
|
case 0x3f:
|
|
|
|
apb_address = 1945;
|
|
|
|
break;
|
|
|
|
case 0x40:
|
|
|
|
apb_address = 1948;
|
|
|
|
break;
|
|
|
|
case 0x25:
|
|
|
|
apb_address = 914;
|
|
|
|
break;
|
|
|
|
case 0x26:
|
|
|
|
apb_address = 915;
|
|
|
|
break;
|
|
|
|
case 0x27:
|
|
|
|
apb_address = 916;
|
|
|
|
break;
|
|
|
|
case 0x28:
|
|
|
|
apb_address = 917;
|
|
|
|
break;
|
|
|
|
case 0x1d:
|
|
|
|
i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
|
|
|
|
word = dib7000p_read_word(state, 384 + i);
|
|
|
|
msg[1].buf[0] = (word >> 8) & 0xff;
|
|
|
|
msg[1].buf[1] = (word) & 0xff;
|
|
|
|
return num;
|
|
|
|
case 0x1f:
|
|
|
|
if (num == 1) { /* write */
|
|
|
|
word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
|
|
|
|
word &= 0x3;
|
2011-01-05 00:08:14 +08:00
|
|
|
word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 72, word); /* Set the proper input */
|
|
|
|
return num;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (apb_address != 0) /* R/W acces via APB */
|
|
|
|
return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
|
|
|
|
else /* R/W access via SERPAR */
|
|
|
|
return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
|
|
|
|
{
|
|
|
|
return I2C_FUNC_I2C;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct i2c_algorithm dib7090_tuner_xfer_algo = {
|
|
|
|
.master_xfer = dib7090_tuner_xfer,
|
|
|
|
.functionality = dib7000p_i2c_func,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *st = fe->demodulator_priv;
|
|
|
|
return &st->dib7090_tuner_adap;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7090_get_i2c_tuner);
|
|
|
|
|
|
|
|
static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
|
|
|
/* drive host bus 2, 3, 4 */
|
|
|
|
reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
|
|
|
|
reg |= (drive << 12) | (drive << 6) | drive;
|
|
|
|
dib7000p_write_word(state, 1798, reg);
|
|
|
|
|
|
|
|
/* drive host bus 5,6 */
|
|
|
|
reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
|
|
|
|
reg |= (drive << 8) | (drive << 2);
|
|
|
|
dib7000p_write_word(state, 1799, reg);
|
|
|
|
|
|
|
|
/* drive host bus 7, 8, 9 */
|
|
|
|
reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
|
|
|
|
reg |= (drive << 12) | (drive << 6) | drive;
|
|
|
|
dib7000p_write_word(state, 1800, reg);
|
|
|
|
|
|
|
|
/* drive host bus 10, 11 */
|
|
|
|
reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
|
|
|
|
reg |= (drive << 8) | (drive << 2);
|
|
|
|
dib7000p_write_word(state, 1801, reg);
|
|
|
|
|
|
|
|
/* drive host bus 12, 13, 14 */
|
|
|
|
reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
|
|
|
|
reg |= (drive << 12) | (drive << 6) | drive;
|
|
|
|
dib7000p_write_word(state, 1802, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
|
|
|
|
{
|
|
|
|
u32 quantif = 3;
|
|
|
|
u32 nom = (insertExtSynchro * P_Kin + syncSize);
|
|
|
|
u32 denom = P_Kout;
|
|
|
|
u32 syncFreq = ((nom << quantif) / denom);
|
|
|
|
|
|
|
|
if ((syncFreq & ((1 << quantif) - 1)) != 0)
|
|
|
|
syncFreq = (syncFreq >> quantif) + 1;
|
|
|
|
else
|
|
|
|
syncFreq = (syncFreq >> quantif);
|
|
|
|
|
|
|
|
if (syncFreq != 0)
|
|
|
|
syncFreq = syncFreq - 1;
|
|
|
|
|
|
|
|
return syncFreq;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
|
|
|
|
{
|
|
|
|
u8 index_buf;
|
|
|
|
u16 rx_copy_buf[22];
|
|
|
|
|
|
|
|
dprintk("Configure DibStream Tx");
|
2011-01-05 00:08:14 +08:00
|
|
|
for (index_buf = 0; index_buf < 22; index_buf++)
|
2011-01-04 15:54:31 +08:00
|
|
|
rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
|
|
|
|
|
|
|
|
dib7000p_write_word(state, 1615, 1);
|
|
|
|
dib7000p_write_word(state, 1603, P_Kin);
|
|
|
|
dib7000p_write_word(state, 1605, P_Kout);
|
|
|
|
dib7000p_write_word(state, 1606, insertExtSynchro);
|
|
|
|
dib7000p_write_word(state, 1608, synchroMode);
|
|
|
|
dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
|
|
|
|
dib7000p_write_word(state, 1610, syncWord & 0xffff);
|
|
|
|
dib7000p_write_word(state, 1612, syncSize);
|
|
|
|
dib7000p_write_word(state, 1615, 0);
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
for (index_buf = 0; index_buf < 22; index_buf++)
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
|
|
|
|
u32 dataOutRate)
|
|
|
|
{
|
|
|
|
u32 syncFreq;
|
|
|
|
|
|
|
|
dprintk("Configure DibStream Rx");
|
2011-01-05 00:08:14 +08:00
|
|
|
if ((P_Kin != 0) && (P_Kout != 0)) {
|
2011-01-04 15:54:31 +08:00
|
|
|
syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
|
|
|
|
dib7000p_write_word(state, 1542, syncFreq);
|
|
|
|
}
|
|
|
|
dib7000p_write_word(state, 1554, 1);
|
|
|
|
dib7000p_write_word(state, 1536, P_Kin);
|
|
|
|
dib7000p_write_word(state, 1537, P_Kout);
|
|
|
|
dib7000p_write_word(state, 1539, synchroMode);
|
|
|
|
dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
|
|
|
|
dib7000p_write_word(state, 1541, syncWord & 0xffff);
|
|
|
|
dib7000p_write_word(state, 1543, syncSize);
|
|
|
|
dib7000p_write_word(state, 1544, dataOutRate);
|
|
|
|
dib7000p_write_word(state, 1554, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_enDivOnHostBus(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
|
|
|
dprintk("Enable Diversity on host bus");
|
2011-01-05 00:08:14 +08:00
|
|
|
reg = (1 << 8) | (1 << 5);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1288, reg);
|
|
|
|
|
|
|
|
return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
|
|
|
dprintk("Enable ADC on host bus");
|
2011-01-05 00:08:14 +08:00
|
|
|
reg = (1 << 7) | (1 << 5);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1288, reg);
|
|
|
|
|
|
|
|
return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
|
|
|
dprintk("Enable Mpeg on host bus");
|
2011-01-05 00:08:14 +08:00
|
|
|
reg = (1 << 9) | (1 << 5);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1288, reg);
|
|
|
|
|
|
|
|
return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_enMpegInput(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
dprintk("Enable Mpeg input");
|
|
|
|
return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
|
|
|
|
{
|
|
|
|
u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
|
|
|
|
|
|
|
|
dprintk("Enable Mpeg mux");
|
|
|
|
dib7000p_write_word(state, 1287, reg);
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
reg &= ~(1 << 7);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1287, reg);
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
reg = (1 << 4);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1288, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_disableMpegMux(struct dib7000p_state *state)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
|
|
|
dprintk("Disable Mpeg mux");
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1288, 0);
|
2011-01-04 15:54:31 +08:00
|
|
|
|
|
|
|
reg = dib7000p_read_word(state, 1287);
|
2011-01-05 00:08:14 +08:00
|
|
|
reg &= ~(1 << 7);
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(state, 1287, reg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
switch (mode) {
|
|
|
|
case INPUT_MODE_DIVERSITY:
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("Enable diversity INPUT");
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
|
2011-01-04 15:54:31 +08:00
|
|
|
break;
|
2011-01-05 00:08:14 +08:00
|
|
|
case INPUT_MODE_MPEG:
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("Enable Mpeg INPUT");
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
|
2011-01-04 15:54:31 +08:00
|
|
|
break;
|
2011-01-05 00:08:14 +08:00
|
|
|
case INPUT_MODE_OFF:
|
|
|
|
default:
|
2011-01-04 15:54:31 +08:00
|
|
|
dprintk("Disable INPUT");
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
|
2011-01-04 15:54:31 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
|
|
|
|
{
|
|
|
|
switch (onoff) {
|
|
|
|
case 0: /* only use the internal way - not the diversity input */
|
|
|
|
dib7090_set_input_mode(fe, INPUT_MODE_MPEG);
|
|
|
|
break;
|
|
|
|
case 1: /* both ways */
|
|
|
|
case 2: /* only the diversity input */
|
|
|
|
dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
|
|
|
|
u16 outreg, smo_mode, fifo_threshold;
|
|
|
|
u8 prefer_mpeg_mux_use = 1;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
dib7090_host_bus_drive(state, 1);
|
|
|
|
|
|
|
|
fifo_threshold = 1792;
|
|
|
|
smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
|
|
|
|
outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case OUTMODE_HIGH_Z:
|
|
|
|
outreg = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OUTMODE_MPEG2_SERIAL:
|
|
|
|
if (prefer_mpeg_mux_use) {
|
|
|
|
dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux");
|
|
|
|
dib7090_enMpegOnHostBus(state);
|
|
|
|
dib7090_enMpegInput(state);
|
|
|
|
if (state->cfg.enMpegOutput == 1)
|
|
|
|
dib7090_enMpegMux(state, 3, 1, 1);
|
|
|
|
|
|
|
|
} else { /* Use Smooth block */
|
|
|
|
dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
|
|
|
|
dib7090_disableMpegMux(state);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1288, (1 << 6));
|
2011-01-04 15:54:31 +08:00
|
|
|
outreg |= (2 << 6) | (0 << 1);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OUTMODE_MPEG2_PAR_GATED_CLK:
|
|
|
|
if (prefer_mpeg_mux_use) {
|
|
|
|
dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
|
|
|
|
dib7090_enMpegOnHostBus(state);
|
|
|
|
dib7090_enMpegInput(state);
|
|
|
|
if (state->cfg.enMpegOutput == 1)
|
|
|
|
dib7090_enMpegMux(state, 2, 0, 0);
|
|
|
|
} else { /* Use Smooth block */
|
|
|
|
dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block");
|
|
|
|
dib7090_disableMpegMux(state);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1288, (1 << 6));
|
2011-01-04 15:54:31 +08:00
|
|
|
outreg |= (0 << 6);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
|
|
|
|
dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block");
|
|
|
|
dib7090_disableMpegMux(state);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1288, (1 << 6));
|
2011-01-04 15:54:31 +08:00
|
|
|
outreg |= (1 << 6);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OUTMODE_MPEG2_FIFO: /* Using Smooth block because not supported by new Mpeg Mux bloc */
|
|
|
|
dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block");
|
|
|
|
dib7090_disableMpegMux(state);
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1288, (1 << 6));
|
2011-01-04 15:54:31 +08:00
|
|
|
outreg |= (5 << 6);
|
|
|
|
smo_mode |= (3 << 1);
|
|
|
|
fifo_threshold = 512;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OUTMODE_DIVERSITY:
|
|
|
|
dprintk("Sip 7090P setting output mode MODE_DIVERSITY");
|
|
|
|
dib7090_disableMpegMux(state);
|
|
|
|
dib7090_enDivOnHostBus(state);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OUTMODE_ANALOG_ADC:
|
|
|
|
dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC");
|
|
|
|
dib7090_enAdcOnHostBus(state);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (state->cfg.output_mpeg2_in_188_bytes)
|
|
|
|
smo_mode |= (1 << 5);
|
|
|
|
|
|
|
|
ret |= dib7000p_write_word(state, 235, smo_mode);
|
|
|
|
ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
|
|
|
|
ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10)); /* allways set Dout active = 1 !!! */
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
|
|
|
u16 en_cur_state;
|
|
|
|
|
|
|
|
dprintk("sleep dib7090: %d", onoff);
|
|
|
|
|
|
|
|
en_cur_state = dib7000p_read_word(state, 1922);
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
if (en_cur_state > 0xff)
|
2011-01-04 15:54:31 +08:00
|
|
|
state->tuner_enable = en_cur_state;
|
|
|
|
|
|
|
|
if (onoff)
|
2011-01-05 00:08:14 +08:00
|
|
|
en_cur_state &= 0x00ff;
|
2011-01-04 15:54:31 +08:00
|
|
|
else {
|
|
|
|
if (state->tuner_enable != 0)
|
|
|
|
en_cur_state = state->tuner_enable;
|
|
|
|
}
|
|
|
|
|
|
|
|
dib7000p_write_word(state, 1922, en_cur_state);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7090_tuner_sleep);
|
|
|
|
|
|
|
|
int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
|
|
|
|
{
|
|
|
|
dprintk("AGC restart callback: %d", restart);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7090_agc_restart);
|
|
|
|
|
|
|
|
int dib7090_get_adc_power(struct dvb_frontend *fe)
|
|
|
|
{
|
|
|
|
return dib7000p_get_adc_power(fe);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7090_get_adc_power);
|
|
|
|
|
|
|
|
int dib7090_slave_reset(struct dvb_frontend *fe)
|
|
|
|
{
|
|
|
|
struct dib7000p_state *state = fe->demodulator_priv;
|
2011-01-05 00:08:14 +08:00
|
|
|
u16 reg;
|
2011-01-04 15:54:31 +08:00
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
reg = dib7000p_read_word(state, 1794);
|
|
|
|
dib7000p_write_word(state, 1794, reg | (4 << 12));
|
2011-01-04 15:54:31 +08:00
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
dib7000p_write_word(state, 1032, 0xffff);
|
|
|
|
return 0;
|
2011-01-04 15:54:31 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7090_slave_reset);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
static struct dvb_frontend_ops dib7000p_ops;
|
2011-01-04 15:54:31 +08:00
|
|
|
struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
|
2006-10-18 19:34:16 +08:00
|
|
|
{
|
|
|
|
struct dvb_frontend *demod;
|
|
|
|
struct dib7000p_state *st;
|
|
|
|
st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
|
|
|
|
if (st == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
|
|
|
|
st->i2c_adap = i2c_adap;
|
|
|
|
st->i2c_addr = i2c_addr;
|
|
|
|
st->gpio_val = cfg->gpio_val;
|
|
|
|
st->gpio_dir = cfg->gpio_dir;
|
|
|
|
|
2008-04-23 02:37:01 +08:00
|
|
|
/* Ensure the output mode remains at the previous default if it's
|
|
|
|
* not specifically set by the caller.
|
|
|
|
*/
|
2011-01-04 15:54:31 +08:00
|
|
|
if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
|
2008-04-23 02:37:01 +08:00
|
|
|
st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
demod = &st->demod;
|
2006-10-18 19:34:16 +08:00
|
|
|
demod->demodulator_priv = st;
|
|
|
|
memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
dib7000p_write_word(st, 1287, 0x0003); /* sram lead in, rdy */
|
2009-09-24 00:41:27 +08:00
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
if (dib7000p_identify(st) != 0)
|
|
|
|
goto error;
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
st->version = dib7000p_read_word(st, 897);
|
|
|
|
|
2009-10-01 09:59:09 +08:00
|
|
|
/* FIXME: make sure the dev.parent field is initialized, or else
|
2011-01-04 15:54:31 +08:00
|
|
|
request_firmware() will hit an OOPS (this should be moved somewhere
|
|
|
|
more common) */
|
2009-10-01 09:59:09 +08:00
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
/* init 7090 tuner adapter */
|
|
|
|
strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
|
|
|
|
st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
|
|
|
|
st->dib7090_tuner_adap.algo_data = NULL;
|
|
|
|
st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
|
|
|
|
i2c_set_adapdata(&st->dib7090_tuner_adap, st);
|
|
|
|
i2c_add_adapter(&st->dib7090_tuner_adap);
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
dib7000p_demod_reset(st);
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
if (st->version == SOC7090) {
|
|
|
|
dib7090_set_output_mode(demod, st->cfg.output_mode);
|
|
|
|
dib7090_set_diversity_in(demod, 0);
|
|
|
|
}
|
|
|
|
|
2006-10-18 19:34:16 +08:00
|
|
|
return demod;
|
|
|
|
|
2011-01-05 00:08:14 +08:00
|
|
|
error:
|
2006-10-18 19:34:16 +08:00
|
|
|
kfree(st);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dib7000p_attach);
|
|
|
|
|
|
|
|
static struct dvb_frontend_ops dib7000p_ops = {
|
|
|
|
.info = {
|
2011-01-04 15:54:31 +08:00
|
|
|
.name = "DiBcom 7000PC",
|
|
|
|
.type = FE_OFDM,
|
|
|
|
.frequency_min = 44250000,
|
|
|
|
.frequency_max = 867250000,
|
|
|
|
.frequency_stepsize = 62500,
|
|
|
|
.caps = FE_CAN_INVERSION_AUTO |
|
|
|
|
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
|
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
|
|
|
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
|
|
|
FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
|
|
|
|
},
|
|
|
|
|
|
|
|
.release = dib7000p_release,
|
|
|
|
|
|
|
|
.init = dib7000p_wakeup,
|
|
|
|
.sleep = dib7000p_sleep,
|
|
|
|
|
|
|
|
.set_frontend = dib7000p_set_frontend,
|
|
|
|
.get_tune_settings = dib7000p_fe_get_tune_settings,
|
|
|
|
.get_frontend = dib7000p_get_frontend,
|
|
|
|
|
|
|
|
.read_status = dib7000p_read_status,
|
|
|
|
.read_ber = dib7000p_read_ber,
|
2006-10-18 19:34:16 +08:00
|
|
|
.read_signal_strength = dib7000p_read_signal_strength,
|
2011-01-04 15:54:31 +08:00
|
|
|
.read_snr = dib7000p_read_snr,
|
|
|
|
.read_ucblocks = dib7000p_read_unc_blocks,
|
2006-10-18 19:34:16 +08:00
|
|
|
};
|
|
|
|
|
2011-01-04 15:54:31 +08:00
|
|
|
MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
|
2006-10-18 19:34:16 +08:00
|
|
|
MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
|
|
|
|
MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
|
|
|
|
MODULE_LICENSE("GPL");
|