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linux-next/drivers/clocksource/rockchip_timer.c

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clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
/*
* Rockchip timer support
*
* Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#define TIMER_NAME "rk_timer"
clocksource/drivers/rockchip: Make the driver more readable Let's checkstyle to clean up the macros with such trivial details. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-09-25 10:14:56 +08:00
#define TIMER_LOAD_COUNT0 0x00
#define TIMER_LOAD_COUNT1 0x04
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
#define TIMER_CONTROL_REG3288 0x10
#define TIMER_CONTROL_REG3399 0x1c
clocksource/drivers/rockchip: Make the driver more readable Let's checkstyle to clean up the macros with such trivial details. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-09-25 10:14:56 +08:00
#define TIMER_INT_STATUS 0x18
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
clocksource/drivers/rockchip: Make the driver more readable Let's checkstyle to clean up the macros with such trivial details. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-09-25 10:14:56 +08:00
#define TIMER_DISABLE 0x0
#define TIMER_ENABLE 0x1
#define TIMER_MODE_FREE_RUNNING (0 << 1)
#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
#define TIMER_INT_UNMASK (1 << 2)
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
struct bc_timer {
struct clock_event_device ce;
void __iomem *base;
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
void __iomem *ctrl;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
u32 freq;
};
static struct bc_timer bc_timer;
static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
{
return container_of(ce, struct bc_timer, ce);
}
static inline void __iomem *rk_base(struct clock_event_device *ce)
{
return rk_timer(ce)->base;
}
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
{
return rk_timer(ce)->ctrl;
}
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
static inline void rk_timer_disable(struct clock_event_device *ce)
{
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
{
writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
rk_ctrl(ce));
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
static void rk_timer_update_counter(unsigned long cycles,
struct clock_event_device *ce)
{
writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
}
static void rk_timer_interrupt_clear(struct clock_event_device *ce)
{
writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
}
static inline int rk_timer_set_next_event(unsigned long cycles,
struct clock_event_device *ce)
{
rk_timer_disable(ce);
rk_timer_update_counter(cycles, ce);
rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
return 0;
}
clockevents/drivers/rockchip: Migrate to new 'set-state' interface Migrate rockchip driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything for oneshot or resume modes, and so the callbacks aren't provided. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-06-18 18:54:32 +08:00
static int rk_timer_shutdown(struct clock_event_device *ce)
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
{
clockevents/drivers/rockchip: Migrate to new 'set-state' interface Migrate rockchip driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything for oneshot or resume modes, and so the callbacks aren't provided. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-06-18 18:54:32 +08:00
rk_timer_disable(ce);
return 0;
}
static int rk_timer_set_periodic(struct clock_event_device *ce)
{
rk_timer_disable(ce);
rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
return 0;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *ce = dev_id;
rk_timer_interrupt_clear(ce);
clockevents/drivers/rockchip: Migrate to new 'set-state' interface Migrate rockchip driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything for oneshot or resume modes, and so the callbacks aren't provided. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-06-18 18:54:32 +08:00
if (clockevent_state_oneshot(ce))
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
rk_timer_disable(ce);
ce->event_handler(ce);
return IRQ_HANDLED;
}
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
{
struct clock_event_device *ce = &bc_timer.ce;
struct clk *timer_clk;
struct clk *pclk;
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
int ret = -EINVAL, irq;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
bc_timer.base = of_iomap(np, 0);
if (!bc_timer.base) {
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
return -ENXIO;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
bc_timer.ctrl = bc_timer.base + ctrl_reg;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
pclk = of_clk_get_by_name(np, "pclk");
if (IS_ERR(pclk)) {
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
ret = PTR_ERR(pclk);
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
goto out_unmap;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
ret = clk_prepare_enable(pclk);
if (ret) {
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
goto out_unmap;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
timer_clk = of_clk_get_by_name(np, "timer");
if (IS_ERR(timer_clk)) {
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
ret = PTR_ERR(timer_clk);
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
goto out_timer_clk;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
ret = clk_prepare_enable(timer_clk);
if (ret) {
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
pr_err("Failed to enable timer clock\n");
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
goto out_timer_clk;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
bc_timer.freq = clk_get_rate(timer_clk);
irq = irq_of_parse_and_map(np, 0);
clocksource/drivers/rockchip: Fix bad NO_IRQ usage The current code assumes the 'irq_of_parse_and_map' will return NO_IRQ in case of failure. Unfortunately, the NO_IRQ is not consistent across the different architectures and we must not rely on it. NO_IRQ is equal to '-1' on ARM and 'irq_of_parse_and_map' returns '0' in case of an error. Hence, the latter won't be detected and will lead to a crash. Fix this by just checking 'irq' is different from zero. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-09-20 22:00:10 +08:00
if (!irq) {
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
ret = -EINVAL;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
goto out_irq;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
ce->name = TIMER_NAME;
clocksource/drivers/rockchip: Add the dynamic irq flag to the timer The rockchip timer is a broadcast timer. Add the CLOCK_EVT_FEAT_DYNIRQ flag and set the cpumask to all possible cpus to save power by avoiding unnecessary wakeups and IPIs. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 21:57:53 +08:00
ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_DYNIRQ;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
ce->set_next_event = rk_timer_set_next_event;
clockevents/drivers/rockchip: Migrate to new 'set-state' interface Migrate rockchip driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We weren't doing anything for oneshot or resume modes, and so the callbacks aren't provided. Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-06-18 18:54:32 +08:00
ce->set_state_shutdown = rk_timer_shutdown;
ce->set_state_periodic = rk_timer_set_periodic;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
ce->irq = irq;
clocksource/drivers/rockchip: Add the dynamic irq flag to the timer The rockchip timer is a broadcast timer. Add the CLOCK_EVT_FEAT_DYNIRQ flag and set the cpumask to all possible cpus to save power by avoiding unnecessary wakeups and IPIs. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 21:57:53 +08:00
ce->cpumask = cpu_possible_mask;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
ce->rating = 250;
rk_timer_interrupt_clear(ce);
rk_timer_disable(ce);
ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
if (ret) {
pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
goto out_irq;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
return 0;
clocksource/drivers/rockchip: Add err handle for rk_timer_init Currently rockchip_timer doesn't do some basic cleanup work when failing to init the timer. Let's add err handle routine to deal with all the err cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-02-15 09:02:09 +08:00
out_irq:
clk_disable_unprepare(timer_clk);
out_timer_clk:
clk_disable_unprepare(pclk);
out_unmap:
iounmap(bc_timer.base);
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
return ret;
clockevents: rockchip: Add rockchip timer for rk3288 The rk3288 board uses the architected timers and these ones are shutdown when the cpu is powered down. There is a need of a broadcast timer in this case to ensure proper wakeup when the cpus are in sleep mode and a timer expires. This driver provides the basic timer functionnality as a backup for the local timers at sleep time. The timer belongs to the alive subsystem. It includes two programmables 64 bits timer channels but the driver only uses 32bits. It works with two operations mode: free running and user defined count. Programing sequence: 1. Timer initialization: * Disable the timer by writing '0' to the CONTROLREG register * Program the timer mode by writing the mode to the CONTROLREG register * Set the interrupt mask 2. Setting the count value: * Load the count value to the registers COUNT0 and COUNT1 (not used). 3. Enable the timer * Write '1' to the CONTROLREG register with the mode (free running or user) Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
2015-01-26 05:06:02 +08:00
}
clocksource/drivers/rockchip: Make the driver more readable Let's checkstyle to clean up the macros with such trivial details. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2015-09-25 10:14:56 +08:00
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
static int __init rk3288_timer_init(struct device_node *np)
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
{
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
return rk_timer_init(np, TIMER_CONTROL_REG3288);
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
}
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
static int __init rk3399_timer_init(struct device_node *np)
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
{
clocksource/drivers/rockchip_timer: Convert init function to return error The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> on a rk3399-evb Tested-by: Heiko Stuebner <heiko@sntech.de>
2016-05-31 23:28:55 +08:00
return rk_timer_init(np, TIMER_CONTROL_REG3399);
clocksource/drivers/rockchip: Add support for the rk3399 SoC The only difference between the rk3399 SoC and the other ones is the control register offset which is different. Add a new field to store the control register address depending on the SoC and use it instead of the <base> + <control offset>. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-16 22:00:08 +08:00
}
clocksources: Switch back to the clksrc table All the clocksource drivers's init function are now converted to return an error code. CLOCKSOURCE_OF_DECLARE is no longer used as well as the clksrc-of table. Let's convert back the names: - CLOCKSOURCE_OF_DECLARE_RET => CLOCKSOURCE_OF_DECLARE - clksrc-of-ret => clksrc-of Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> For exynos_mct and samsung_pwm_timer: Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> For arch/arc: Acked-by: Vineet Gupta <vgupta@synopsys.com> For mediatek driver: Acked-by: Matthias Brugger <matthias.bgg@gmail.com> For the Rockchip-part Acked-by: Heiko Stuebner <heiko@sntech.de> For STi : Acked-by: Patrice Chotard <patrice.chotard@st.com> For the mps2-timer.c and versatile.c changes: Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> For the OXNAS part : Acked-by: Neil Armstrong <narmstrong@baylibre.com> For LPC32xx driver: Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> For Broadcom Kona timer change: Acked-by: Ray Jui <ray.jui@broadcom.com> For Sun4i and Sun5i: Acked-by: Chen-Yu Tsai <wens@csie.org> For Meson6: Acked-by: Carlo Caione <carlo@caione.org> For Keystone: Acked-by: Santosh Shilimkar <ssantosh@kernel.org> For NPS: Acked-by: Noam Camus <noamca@mellanox.com> For bcm2835: Acked-by: Eric Anholt <eric@anholt.net>
2016-06-07 06:27:44 +08:00
CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
rk3288_timer_init);
CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
rk3399_timer_init);
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