2012-11-26 22:46:12 +08:00
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/*
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* Copyright 2012 Stefan Roese
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* Stefan Roese <sr@denx.de>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2013-03-14 03:07:37 +08:00
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/include/ "skeleton.dtsi"
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2012-11-26 22:46:12 +08:00
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/ {
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2013-03-14 03:07:37 +08:00
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interrupt-parent = <&intc>;
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2013-11-17 02:17:29 +08:00
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aliases {
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ethernet0 = &emac;
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2013-11-17 17:03:04 +08:00
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serial0 = &uart0;
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serial1 = &uart1;
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2014-01-03 05:05:04 +08:00
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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2013-11-17 02:17:29 +08:00
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};
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2013-03-14 03:07:37 +08:00
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cpus {
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2013-06-10 22:48:36 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-03-14 03:07:37 +08:00
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cpu@0 {
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2013-04-19 01:41:57 +08:00
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device_type = "cpu";
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2013-03-14 03:07:37 +08:00
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compatible = "arm,cortex-a8";
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2013-04-19 01:41:57 +08:00
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reg = <0x0>;
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2013-03-14 03:07:37 +08:00
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};
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};
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2012-11-26 22:46:12 +08:00
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memory {
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reg = <0x40000000 0x80000000>;
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};
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2013-01-26 22:36:54 +08:00
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2013-03-14 03:07:37 +08:00
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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2014-02-03 09:51:41 +08:00
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osc24M: clk@01c20050 {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-osc-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20050 0x4>;
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2013-04-09 21:48:04 +08:00
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clock-frequency = <24000000>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "osc24M";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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osc32k: clk@0 {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "osc32k";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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pll1: clk@01c20000 {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-pll1-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "pll1";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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pll4: clk@01c20018 {
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2013-12-23 11:32:35 +08:00
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-pll1-clk";
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2013-12-23 11:32:35 +08:00
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "pll4";
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2013-12-23 11:32:35 +08:00
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};
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2014-02-03 09:51:41 +08:00
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pll5: clk@01c20020 {
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2013-12-23 11:32:38 +08:00
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#clock-cells = <1>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-pll5-clk";
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2013-12-23 11:32:38 +08:00
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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2014-02-03 09:51:41 +08:00
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pll6: clk@01c20028 {
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2013-12-23 11:32:38 +08:00
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#clock-cells = <1>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-pll6-clk";
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2013-12-23 11:32:38 +08:00
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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2013-03-14 03:07:37 +08:00
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-cpu-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "cpu";
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2013-03-14 03:07:37 +08:00
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-axi-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "axi";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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axi_gates: clk@01c2005c {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <1>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-axi-gates-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-ahb-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "ahb";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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ahb_gates: clk@01c20060 {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <1>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-ahb-gates-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
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"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
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"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
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"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
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"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
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"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
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"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_mp", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-apb0-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "apb0";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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apb0_gates: clk@01c20068 {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <1>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-apb0-gates-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
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"apb0_ir1", "apb0_keypad";
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};
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-apb1-mux-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20058 0x4>;
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2013-12-23 11:32:38 +08:00
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "apb1_mux";
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2013-03-14 03:07:37 +08:00
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-apb1-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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2014-02-03 09:51:41 +08:00
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clock-output-names = "apb1";
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2013-03-14 03:07:37 +08:00
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};
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2014-02-03 09:51:41 +08:00
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apb1_gates: clk@01c2006c {
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2013-03-14 03:07:37 +08:00
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#clock-cells = <1>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-apb1-gates-clk";
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2013-03-14 03:07:37 +08:00
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_can", "apb1_scr",
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"apb1_ps20", "apb1_ps21", "apb1_uart0",
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"apb1_uart1", "apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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2013-12-23 11:32:41 +08:00
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-23 11:32:41 +08:00
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-23 11:32:41 +08:00
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-23 11:32:41 +08:00
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-23 11:32:41 +08:00
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-23 11:32:41 +08:00
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-23 11:32:41 +08:00
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3";
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};
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ts_clk: clk@01c20098 {
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#clock-cells = <0>;
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2014-02-06 16:55:58 +08:00
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|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c20098 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "ts";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ss_clk: clk@01c2009c {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c2009c 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "ss";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi0_clk: clk@01c200a0 {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200a0 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "spi0";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1_clk: clk@01c200a4 {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200a4 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "spi1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi2_clk: clk@01c200a8 {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200a8 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "spi2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pata_clk: clk@01c200ac {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200ac 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "pata";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ir0_clk: clk@01c200b0 {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200b0 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "ir0";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ir1_clk: clk@01c200b4 {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200b4 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "ir1";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-07 23:21:51 +08:00
|
|
|
usb_clk: clk@01c200cc {
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
compatible = "allwinner,sun4i-a10-usb-clk";
|
|
|
|
|
reg = <0x01c200cc 0x4>;
|
|
|
|
|
clocks = <&pll6 1>;
|
|
|
|
|
clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-23 11:32:41 +08:00
|
|
|
spi3_clk: clk@01c200d4 {
|
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 16:55:58 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-23 11:32:41 +08:00
|
|
|
reg = <0x01c200d4 0x4>;
|
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
|
clock-output-names = "spi3";
|
|
|
|
|
};
|
2013-03-14 03:07:37 +08:00
|
|
|
};
|
|
|
|
|
|
2013-08-03 22:07:36 +08:00
|
|
|
soc@01c00000 {
|
2013-03-14 03:07:37 +08:00
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
2014-02-23 05:35:55 +08:00
|
|
|
spi0: spi@01c05000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
|
reg = <0x01c05000 0x1000>;
|
|
|
|
|
interrupts = <10>;
|
|
|
|
|
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
|
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi1: spi@01c06000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
|
reg = <0x01c06000 0x1000>;
|
|
|
|
|
interrupts = <11>;
|
|
|
|
|
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
|
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-05-30 11:49:23 +08:00
|
|
|
emac: ethernet@01c0b000 {
|
|
|
|
|
compatible = "allwinner,sun4i-emac";
|
|
|
|
|
reg = <0x01c0b000 0x1000>;
|
|
|
|
|
interrupts = <55>;
|
|
|
|
|
clocks = <&ahb_gates 17>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mdio@01c0b080 {
|
|
|
|
|
compatible = "allwinner,sun4i-mdio";
|
|
|
|
|
reg = <0x01c0b080 0x14>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-23 05:35:55 +08:00
|
|
|
spi2: spi@01c17000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
|
reg = <0x01c17000 0x1000>;
|
|
|
|
|
interrupts = <12>;
|
|
|
|
|
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
|
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi3: spi@01c1f000 {
|
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
|
reg = <0x01c1f000 0x1000>;
|
|
|
|
|
interrupts = <50>;
|
|
|
|
|
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
|
|
|
|
clock-names = "ahb", "mod";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-14 03:07:37 +08:00
|
|
|
intc: interrupt-controller@01c20400 {
|
2013-03-25 02:20:52 +08:00
|
|
|
compatible = "allwinner,sun4i-ic";
|
2013-03-14 03:07:37 +08:00
|
|
|
reg = <0x01c20400 0x400>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-28 02:26:05 +08:00
|
|
|
pio: pinctrl@01c20800 {
|
2013-01-26 22:36:54 +08:00
|
|
|
compatible = "allwinner,sun4i-a10-pinctrl";
|
|
|
|
|
reg = <0x01c20800 0x400>;
|
2013-04-06 21:00:48 +08:00
|
|
|
interrupts = <28>;
|
2013-03-28 05:20:41 +08:00
|
|
|
clocks = <&apb0_gates 5>;
|
2013-01-28 02:26:05 +08:00
|
|
|
gpio-controller;
|
2013-04-06 21:00:48 +08:00
|
|
|
interrupt-controller;
|
2013-01-26 22:36:54 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2013-01-28 02:26:05 +08:00
|
|
|
#gpio-cells = <3>;
|
2013-01-26 22:36:55 +08:00
|
|
|
|
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
|
|
|
allwinner,pins = "PB22", "PB23";
|
|
|
|
|
allwinner,function = "uart0";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart0_pins_b: uart0@1 {
|
|
|
|
|
allwinner,pins = "PF2", "PF4";
|
|
|
|
|
allwinner,function = "uart0";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart1_pins_a: uart1@0 {
|
|
|
|
|
allwinner,pins = "PA10", "PA11";
|
|
|
|
|
allwinner,function = "uart1";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
2013-03-10 20:44:38 +08:00
|
|
|
|
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
|
|
|
allwinner,pins = "PB0", "PB1";
|
|
|
|
|
allwinner,function = "i2c0";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
|
|
|
allwinner,pins = "PB18", "PB19";
|
|
|
|
|
allwinner,function = "i2c1";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
|
|
|
allwinner,pins = "PB20", "PB21";
|
|
|
|
|
allwinner,function = "i2c2";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller:
"This is a re-do of the net-next pull request for the current merge
window. The only difference from the one I made the other day is that
this has Eliezer's interface renames and the timeout handling changes
made based upon your feedback, as well as a few bug fixes that have
trickeled in.
Highlights:
1) Low latency device polling, eliminating the cost of interrupt
handling and context switches. Allows direct polling of a network
device from socket operations, such as recvmsg() and poll().
Currently ixgbe, mlx4, and bnx2x support this feature.
Full high level description, performance numbers, and design in
commit 0a4db187a999 ("Merge branch 'll_poll'")
From Eliezer Tamir.
2) With the routing cache removed, ip_check_mc_rcu() gets exercised
more than ever before in the case where we have lots of multicast
addresses. Use a hash table instead of a simple linked list, from
Eric Dumazet.
3) Add driver for Atheros CQA98xx 802.11ac wireless devices, from
Bartosz Markowski, Janusz Dziedzic, Kalle Valo, Marek Kwaczynski,
Marek Puzyniak, Michal Kazior, and Sujith Manoharan.
4) Support reporting the TUN device persist flag to userspace, from
Pavel Emelyanov.
5) Allow controlling network device VF link state using netlink, from
Rony Efraim.
6) Support GRE tunneling in openvswitch, from Pravin B Shelar.
7) Adjust SOCK_MIN_RCVBUF and SOCK_MIN_SNDBUF for modern times, from
Daniel Borkmann and Eric Dumazet.
8) Allow controlling of TCP quickack behavior on a per-route basis,
from Cong Wang.
9) Several bug fixes and improvements to vxlan from Stephen
Hemminger, Pravin B Shelar, and Mike Rapoport. In particular,
support receiving on multiple UDP ports.
10) Major cleanups, particular in the area of debugging and cookie
lifetime handline, to the SCTP protocol code. From Daniel
Borkmann.
11) Allow packets to cross network namespaces when traversing tunnel
devices. From Nicolas Dichtel.
12) Allow monitoring netlink traffic via AF_PACKET sockets, in a
manner akin to how we monitor real network traffic via ptype_all.
From Daniel Borkmann.
13) Several bug fixes and improvements for the new alx device driver,
from Johannes Berg.
14) Fix scalability issues in the netem packet scheduler's time queue,
by using an rbtree. From Eric Dumazet.
15) Several bug fixes in TCP loss recovery handling, from Yuchung
Cheng.
16) Add support for GSO segmentation of MPLS packets, from Simon
Horman.
17) Make network notifiers have a real data type for the opaque
pointer that's passed into them. Use this to properly handle
network device flag changes in arp_netdev_event(). From Jiri
Pirko and Timo Teräs.
18) Convert several drivers over to module_pci_driver(), from Peter
Huewe.
19) tcp_fixup_rcvbuf() can loop 500 times over loopback, just use a
O(1) calculation instead. From Eric Dumazet.
20) Support setting of explicit tunnel peer addresses in ipv6, just
like ipv4. From Nicolas Dichtel.
21) Protect x86 BPF JIT against spraying attacks, from Eric Dumazet.
22) Prevent a single high rate flow from overruning an individual cpu
during RX packet processing via selective flow shedding. From
Willem de Bruijn.
23) Don't use spinlocks in TCP md5 signing fast paths, from Eric
Dumazet.
24) Don't just drop GSO packets which are above the TBF scheduler's
burst limit, chop them up so they are in-bounds instead. Also
from Eric Dumazet.
25) VLAN offloads are missed when configured on top of a bridge, fix
from Vlad Yasevich.
26) Support IPV6 in ping sockets. From Lorenzo Colitti.
27) Receive flow steering targets should be updated at poll() time
too, from David Majnemer.
28) Fix several corner case regressions in PMTU/redirect handling due
to the routing cache removal, from Timo Teräs.
29) We have to be mindful of ipv4 mapped ipv6 sockets in
upd_v6_push_pending_frames(). From Hannes Frederic Sowa.
30) Fix L2TP sequence number handling bugs, from James Chapman."
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1214 commits)
drivers/net: caif: fix wrong rtnl_is_locked() usage
drivers/net: enic: release rtnl_lock on error-path
vhost-net: fix use-after-free in vhost_net_flush
net: mv643xx_eth: do not use port number as platform device id
net: sctp: confirm route during forward progress
virtio_net: fix race in RX VQ processing
virtio: support unlocked queue poll
net/cadence/macb: fix bug/typo in extracting gem_irq_read_clear bit
Documentation: Fix references to defunct linux-net@vger.kernel.org
net/fs: change busy poll time accounting
net: rename low latency sockets functions to busy poll
bridge: fix some kernel warning in multicast timer
sfc: Fix memory leak when discarding scattered packets
sit: fix tunnel update via netlink
dt:net:stmmac: Add dt specific phy reset callback support.
dt:net:stmmac: Add support to dwmac version 3.610 and 3.710
dt:net:stmmac: Allocate platform data only if its NULL.
net:stmmac: fix memleak in the open method
ipv6: rt6_check_neigh should successfully verify neigh if no NUD information are available
net: ipv6: fix wrong ping_v6_sendmsg return value
...
2013-07-10 09:24:39 +08:00
|
|
|
|
2013-05-30 11:49:22 +08:00
|
|
|
emac_pins_a: emac0@0 {
|
|
|
|
|
allwinner,pins = "PA0", "PA1", "PA2",
|
|
|
|
|
"PA3", "PA4", "PA5", "PA6",
|
|
|
|
|
"PA7", "PA8", "PA9", "PA10",
|
|
|
|
|
"PA11", "PA12", "PA13", "PA14",
|
|
|
|
|
"PA15", "PA16";
|
|
|
|
|
allwinner,function = "emac";
|
|
|
|
|
allwinner,drive = <0>;
|
|
|
|
|
allwinner,pull = <0>;
|
|
|
|
|
};
|
2013-01-26 22:36:54 +08:00
|
|
|
};
|
2013-02-21 09:25:03 +08:00
|
|
|
|
2013-03-14 03:07:37 +08:00
|
|
|
timer@01c20c00 {
|
2013-03-25 02:00:17 +08:00
|
|
|
compatible = "allwinner,sun4i-timer";
|
2013-03-14 03:07:37 +08:00
|
|
|
reg = <0x01c20c00 0x90>;
|
|
|
|
|
interrupts = <22>;
|
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wdt: watchdog@01c20c90 {
|
2013-03-25 02:32:34 +08:00
|
|
|
compatible = "allwinner,sun4i-wdt";
|
2013-03-14 03:07:37 +08:00
|
|
|
reg = <0x01c20c90 0x10>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-17 02:30:26 +08:00
|
|
|
rtc: rtc@01c20d00 {
|
|
|
|
|
compatible = "allwinner,sun4i-rtc";
|
|
|
|
|
reg = <0x01c20d00 0x20>;
|
|
|
|
|
interrupts = <24>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-09-03 18:33:28 +08:00
|
|
|
sid: eeprom@01c23800 {
|
|
|
|
|
compatible = "allwinner,sun4i-sid";
|
|
|
|
|
reg = <0x01c23800 0x10>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-01-01 00:20:50 +08:00
|
|
|
rtp: rtp@01c25000 {
|
|
|
|
|
compatible = "allwinner,sun4i-ts";
|
|
|
|
|
reg = <0x01c25000 0x100>;
|
|
|
|
|
interrupts = <29>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-21 09:25:03 +08:00
|
|
|
uart0: serial@01c28000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28000 0x400>;
|
|
|
|
|
interrupts = <1>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2013-03-28 05:20:39 +08:00
|
|
|
clocks = <&apb1_gates 16>;
|
2013-02-21 09:25:03 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-02-21 09:38:27 +08:00
|
|
|
|
2013-03-14 03:07:37 +08:00
|
|
|
uart1: serial@01c28400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28400 0x400>;
|
|
|
|
|
interrupts = <2>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&apb1_gates 17>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-21 09:38:27 +08:00
|
|
|
uart2: serial@01c28800 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28800 0x400>;
|
|
|
|
|
interrupts = <3>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2013-03-28 05:20:39 +08:00
|
|
|
clocks = <&apb1_gates 18>;
|
2013-02-21 09:38:27 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-14 03:07:37 +08:00
|
|
|
uart3: serial@01c28c00 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c28c00 0x400>;
|
|
|
|
|
interrupts = <4>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
clocks = <&apb1_gates 19>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-21 09:38:27 +08:00
|
|
|
uart4: serial@01c29000 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29000 0x400>;
|
|
|
|
|
interrupts = <17>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2013-03-28 05:20:39 +08:00
|
|
|
clocks = <&apb1_gates 20>;
|
2013-02-21 09:38:27 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart5: serial@01c29400 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29400 0x400>;
|
|
|
|
|
interrupts = <18>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2013-03-28 05:20:39 +08:00
|
|
|
clocks = <&apb1_gates 21>;
|
2013-02-21 09:38:27 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart6: serial@01c29800 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29800 0x400>;
|
|
|
|
|
interrupts = <19>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2013-03-28 05:20:39 +08:00
|
|
|
clocks = <&apb1_gates 22>;
|
2013-02-21 09:38:27 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart7: serial@01c29c00 {
|
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
|
reg = <0x01c29c00 0x400>;
|
|
|
|
|
interrupts = <20>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
2013-03-28 05:20:39 +08:00
|
|
|
clocks = <&apb1_gates 23>;
|
2013-02-21 09:38:27 +08:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-03-10 20:34:36 +08:00
|
|
|
|
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
|
|
|
compatible = "allwinner,sun4i-i2c";
|
|
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
|
|
interrupts = <7>;
|
|
|
|
|
clocks = <&apb1_gates 0>;
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
|
|
|
compatible = "allwinner,sun4i-i2c";
|
|
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
|
|
interrupts = <8>;
|
|
|
|
|
clocks = <&apb1_gates 1>;
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
|
|
|
compatible = "allwinner,sun4i-i2c";
|
|
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
|
|
interrupts = <9>;
|
|
|
|
|
clocks = <&apb1_gates 2>;
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-01-26 22:36:54 +08:00
|
|
|
};
|
2012-11-26 22:46:12 +08:00
|
|
|
};
|
