2011-05-10 00:56:46 +08:00
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#ifndef LINUX_BCMA_DRIVER_CC_H_
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#define LINUX_BCMA_DRIVER_CC_H_
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/** ChipCommon core registers. **/
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#define BCMA_CC_ID 0x0000
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#define BCMA_CC_ID_ID 0x0000FFFF
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#define BCMA_CC_ID_ID_SHIFT 0
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#define BCMA_CC_ID_REV 0x000F0000
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#define BCMA_CC_ID_REV_SHIFT 16
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#define BCMA_CC_ID_PKG 0x00F00000
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#define BCMA_CC_ID_PKG_SHIFT 20
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#define BCMA_CC_ID_NRCORES 0x0F000000
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#define BCMA_CC_ID_NRCORES_SHIFT 24
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#define BCMA_CC_ID_TYPE 0xF0000000
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#define BCMA_CC_ID_TYPE_SHIFT 28
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#define BCMA_CC_CAP 0x0004 /* Capabilities */
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#define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
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#define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
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#define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */
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#define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
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#define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
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#define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */
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#define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */
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#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
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#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
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#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
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2011-07-23 07:20:09 +08:00
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#define BCMA_CC_FLASHT_NFLASH 0x00000200
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
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#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
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#define BCMA_PLLTYPE_NONE 0x00000000
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#define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
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#define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
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#define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
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#define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
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#define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
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#define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
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#define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
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#define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */
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#define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */
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#define BCMA_CC_CAP_OTPS_SHIFT 19
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#define BCMA_CC_CAP_OTPS_BASE 5
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#define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */
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#define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */
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#define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
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#define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
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#define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
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#define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */
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#define BCMA_CC_CORECTL 0x0008
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#define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
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#define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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#define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
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#define BCMA_CC_BIST 0x000C
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#define BCMA_CC_OTPS 0x0010 /* OTP status */
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#define BCMA_CC_OTPS_PROGFAIL 0x80000000
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#define BCMA_CC_OTPS_PROTECT 0x00000007
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#define BCMA_CC_OTPS_HW_PROTECT 0x00000001
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#define BCMA_CC_OTPS_SW_PROTECT 0x00000002
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#define BCMA_CC_OTPS_CID_PROTECT 0x00000004
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2012-03-06 22:50:48 +08:00
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#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
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#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
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#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_OTPC 0x0014 /* OTP control */
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#define BCMA_CC_OTPC_RECWAIT 0xFF000000
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#define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
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#define BCMA_CC_OTPC_PRW_SHIFT 8
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#define BCMA_CC_OTPC_MAXFAIL 0x00000038
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#define BCMA_CC_OTPC_VSEL 0x00000006
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#define BCMA_CC_OTPC_SELVL 0x00000001
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#define BCMA_CC_OTPP 0x0018 /* OTP prog */
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#define BCMA_CC_OTPP_COL 0x000000FF
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#define BCMA_CC_OTPP_ROW 0x0000FF00
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#define BCMA_CC_OTPP_ROW_SHIFT 8
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#define BCMA_CC_OTPP_READERR 0x10000000
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#define BCMA_CC_OTPP_VALUE 0x20000000
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#define BCMA_CC_OTPP_READ 0x40000000
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#define BCMA_CC_OTPP_START 0x80000000
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#define BCMA_CC_OTPP_BUSY 0x80000000
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2012-03-06 22:50:48 +08:00
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#define BCMA_CC_OTPL 0x001C /* OTP layout */
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#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_IRQSTAT 0x0020
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#define BCMA_CC_IRQMASK 0x0024
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#define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
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#define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
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#define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
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#define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
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#define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
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2012-03-06 22:50:48 +08:00
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#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
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#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
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#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
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#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
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#define BCMA_CC_JCMD_START 0x80000000
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#define BCMA_CC_JCMD_BUSY 0x80000000
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#define BCMA_CC_JCMD_PAUSE 0x40000000
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#define BCMA_CC_JCMD0_ACC_MASK 0x0000F000
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#define BCMA_CC_JCMD0_ACC_IRDR 0x00000000
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#define BCMA_CC_JCMD0_ACC_DR 0x00001000
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#define BCMA_CC_JCMD0_ACC_IR 0x00002000
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#define BCMA_CC_JCMD0_ACC_RESET 0x00003000
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#define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000
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#define BCMA_CC_JCMD0_ACC_PDR 0x00005000
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#define BCMA_CC_JCMD0_IRW_MASK 0x00000F00
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#define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
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#define BCMA_CC_JCMD_ACC_IRDR 0x00000000
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#define BCMA_CC_JCMD_ACC_DR 0x00010000
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#define BCMA_CC_JCMD_ACC_IR 0x00020000
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#define BCMA_CC_JCMD_ACC_RESET 0x00030000
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#define BCMA_CC_JCMD_ACC_IRPDR 0x00040000
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#define BCMA_CC_JCMD_ACC_PDR 0x00050000
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#define BCMA_CC_JCMD_IRW_MASK 0x00001F00
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#define BCMA_CC_JCMD_IRW_SHIFT 8
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#define BCMA_CC_JCMD_DRW_MASK 0x0000003F
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#define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */
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#define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */
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#define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */
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#define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */
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#define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */
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#define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */
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#define BCMA_CC_FLASHCTL 0x0040
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#define BCMA_CC_FLASHCTL_START 0x80000000
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#define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START
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#define BCMA_CC_FLASHADDR 0x0044
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#define BCMA_CC_FLASHDATA 0x0048
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#define BCMA_CC_BCAST_ADDR 0x0050
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#define BCMA_CC_BCAST_DATA 0x0054
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2011-05-11 08:08:09 +08:00
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#define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */
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#define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_GPIOIN 0x0060
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#define BCMA_CC_GPIOOUT 0x0064
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#define BCMA_CC_GPIOOUTEN 0x0068
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#define BCMA_CC_GPIOCTL 0x006C
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#define BCMA_CC_GPIOPOL 0x0070
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#define BCMA_CC_GPIOIRQ 0x0074
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#define BCMA_CC_WATCHDOG 0x0080
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#define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
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2011-05-11 08:08:09 +08:00
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#define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF
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#define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0
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#define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16
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#define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
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#define BCMA_CC_CLOCK_N 0x0090
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#define BCMA_CC_CLOCK_SB 0x0094
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#define BCMA_CC_CLOCK_PCI 0x0098
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#define BCMA_CC_CLOCK_M2 0x009C
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#define BCMA_CC_CLOCK_MIPS 0x00A0
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#define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */
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#define BCMA_CC_CLKDIV_SFLASH 0x0F000000
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#define BCMA_CC_CLKDIV_SFLASH_SHIFT 24
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#define BCMA_CC_CLKDIV_OTP 0x000F0000
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#define BCMA_CC_CLKDIV_OTP_SHIFT 16
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#define BCMA_CC_CLKDIV_JTAG 0x00000F00
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#define BCMA_CC_CLKDIV_JTAG_SHIFT 8
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#define BCMA_CC_CLKDIV_UART 0x000000FF
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#define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
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#define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
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#define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
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#define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
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#define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
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#define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
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#define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
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#define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
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#define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
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#define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
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#define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
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#define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
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#define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
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#define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
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#define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
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#define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16
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#define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
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#define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
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#define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
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#define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
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#define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
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#define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
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#define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
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#define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16
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#define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */
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#define BCMA_CC_EROM 0x00FC
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#define BCMA_CC_PCMCIA_CFG 0x0100
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#define BCMA_CC_PCMCIA_MEMWAIT 0x0104
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#define BCMA_CC_PCMCIA_ATTRWAIT 0x0108
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#define BCMA_CC_PCMCIA_IOWAIT 0x010C
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#define BCMA_CC_IDE_CFG 0x0110
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#define BCMA_CC_IDE_MEMWAIT 0x0114
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#define BCMA_CC_IDE_ATTRWAIT 0x0118
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#define BCMA_CC_IDE_IOWAIT 0x011C
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#define BCMA_CC_PROG_CFG 0x0120
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#define BCMA_CC_PROG_WAITCNT 0x0124
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#define BCMA_CC_FLASH_CFG 0x0128
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2011-07-23 07:20:09 +08:00
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#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_FLASH_WAITCNT 0x012C
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2012-01-31 07:03:37 +08:00
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#define BCMA_CC_SROM_CONTROL 0x0190
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#define BCMA_CC_SROM_CONTROL_START 0x80000000
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#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
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#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
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#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
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#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
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#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
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#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
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#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
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#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
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#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
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#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
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#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
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#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
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#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
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#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
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2011-07-17 00:43:36 +08:00
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/* 0x1E0 is defined as shared BCMA_CLKCTLST */
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
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#define BCMA_CC_UART0_DATA 0x0300
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#define BCMA_CC_UART0_IMR 0x0304
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#define BCMA_CC_UART0_FCR 0x0308
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#define BCMA_CC_UART0_LCR 0x030C
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#define BCMA_CC_UART0_MCR 0x0310
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#define BCMA_CC_UART0_LSR 0x0314
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#define BCMA_CC_UART0_MSR 0x0318
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#define BCMA_CC_UART0_SCRATCH 0x031C
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#define BCMA_CC_UART1_DATA 0x0400
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#define BCMA_CC_UART1_IMR 0x0404
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#define BCMA_CC_UART1_FCR 0x0408
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#define BCMA_CC_UART1_LCR 0x040C
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#define BCMA_CC_UART1_MCR 0x0410
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#define BCMA_CC_UART1_LSR 0x0414
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#define BCMA_CC_UART1_MSR 0x0418
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#define BCMA_CC_UART1_SCRATCH 0x041C
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/* PMU registers (rev >= 20) */
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#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
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#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
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#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
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2011-12-09 01:02:22 +08:00
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#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
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2011-05-10 00:56:46 +08:00
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#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
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#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
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#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
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#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
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#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
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#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
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#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
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#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
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#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
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#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
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#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
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#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
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#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
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#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
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#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
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#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
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#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
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#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
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#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
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#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
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#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
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#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
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#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
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#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
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#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
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#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
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#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
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#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
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#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
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#define BCMA_CC_CHIPCTL_ADDR 0x0650
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#define BCMA_CC_CHIPCTL_DATA 0x0654
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#define BCMA_CC_REGCTL_ADDR 0x0658
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#define BCMA_CC_REGCTL_DATA 0x065C
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#define BCMA_CC_PLLCTL_ADDR 0x0660
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#define BCMA_CC_PLLCTL_DATA 0x0664
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2011-07-17 17:00:59 +08:00
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#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
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2011-05-10 00:56:46 +08:00
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2011-07-23 07:20:11 +08:00
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/* Divider allocation in 4716/47162/5356 */
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#define BCMA_CC_PMU5_MAINPLL_CPU 1
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#define BCMA_CC_PMU5_MAINPLL_MEM 2
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#define BCMA_CC_PMU5_MAINPLL_SSB 3
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/* PLL usage in 4716/47162 */
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#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
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/* PLL usage in 5356/5357 */
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#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
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#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
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/* 4706 PMU */
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#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
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2011-07-23 07:20:10 +08:00
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/* ALP clock on pre-PMU chips */
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#define BCMA_CC_PMU_ALP_CLOCK 20000000
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2011-07-23 07:20:11 +08:00
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/* HT clock for systems with PMU-enabled chipcommon */
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#define BCMA_CC_PMU_HT_CLOCK 80000000
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/* PMU rev 5 (& 6) */
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#define BCMA_CC_PPL_P1P2_OFF 0
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#define BCMA_CC_PPL_P1_MASK 0x0f000000
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#define BCMA_CC_PPL_P1_SHIFT 24
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#define BCMA_CC_PPL_P2_MASK 0x00f00000
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#define BCMA_CC_PPL_P2_SHIFT 20
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#define BCMA_CC_PPL_M14_OFF 1
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#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
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#define BCMA_CC_PPL_MDIV_WIDTH 8
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#define BCMA_CC_PPL_NM5_OFF 2
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#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
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#define BCMA_CC_PPL_NDIV_SHIFT 20
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#define BCMA_CC_PPL_FMAB_OFF 3
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#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
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#define BCMA_CC_PPL_MRAT_SHIFT 28
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#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
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#define BCMA_CC_PPL_ABRAT_SHIFT 27
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#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
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#define BCMA_CC_PPL_PLLCTL_OFF 4
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#define BCMA_CC_PPL_PCHI_OFF 5
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#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
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2011-07-23 07:20:10 +08:00
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2011-08-12 05:46:44 +08:00
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/* BCM4331 ChipControl numbers. */
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#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
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#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
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#define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */
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#define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */
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#define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */
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#define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */
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#define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */
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#define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */
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#define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */
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#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
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#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
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#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
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#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
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#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
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2011-05-10 00:56:46 +08:00
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/* Data for the PMU, if available.
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* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
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*/
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struct bcma_chipcommon_pmu {
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u8 rev; /* PMU revision */
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u32 crystalfreq; /* The active crystal frequency (in kHz) */
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};
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2011-07-23 07:20:09 +08:00
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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struct bcma_pflash {
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u8 buswidth;
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u32 window;
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u32 window_size;
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};
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2011-07-23 07:20:10 +08:00
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struct bcma_serial_port {
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void *regs;
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unsigned long clockspeed;
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unsigned int irq;
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unsigned int baud_base;
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unsigned int reg_shift;
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};
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2011-07-23 07:20:09 +08:00
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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2011-05-10 00:56:46 +08:00
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struct bcma_drv_cc {
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struct bcma_device *core;
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u32 status;
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u32 capabilities;
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u32 capabilities_ext;
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2011-07-23 07:20:07 +08:00
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u8 setup_done:1;
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2011-05-10 00:56:46 +08:00
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/* Fast Powerup Delay constant */
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u16 fast_pwrup_delay;
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struct bcma_chipcommon_pmu pmu;
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2011-07-23 07:20:09 +08:00
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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struct bcma_pflash pflash;
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2011-07-23 07:20:10 +08:00
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int nr_serial_ports;
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struct bcma_serial_port serial_ports[4];
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2011-07-23 07:20:09 +08:00
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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2011-05-10 00:56:46 +08:00
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};
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/* Register access */
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#define bcma_cc_read32(cc, offset) \
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bcma_read32((cc)->core, offset)
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#define bcma_cc_write32(cc, offset, val) \
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bcma_write32((cc)->core, offset, val)
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#define bcma_cc_mask32(cc, offset, mask) \
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bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask))
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#define bcma_cc_set32(cc, offset, set) \
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bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set))
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#define bcma_cc_maskset32(cc, offset, mask, set) \
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bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
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extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
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extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
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extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
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2011-08-12 05:46:44 +08:00
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void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
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2011-05-10 00:56:46 +08:00
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extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
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u32 ticks);
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void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
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/* Chipcommon GPIO pin access. */
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u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask);
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u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
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u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
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/* PMU support */
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extern void bcma_pmu_init(struct bcma_drv_cc *cc);
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2011-09-16 18:33:58 +08:00
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extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
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u32 value);
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extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset,
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u32 mask, u32 set);
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extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set);
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extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set);
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2011-05-10 00:56:46 +08:00
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#endif /* LINUX_BCMA_DRIVER_CC_H_ */
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