2007-07-17 19:04:13 +08:00
|
|
|
|
/*
|
|
|
|
|
* OMAP2 McSPI controller driver
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2005, 2006 Nokia Corporation
|
|
|
|
|
* Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
|
2011-02-02 20:22:14 +08:00
|
|
|
|
* Juha Yrj<EFBFBD>l<EFBFBD> <juha.yrjola@nokia.com>
|
2007-07-17 19:04:13 +08:00
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
|
* (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
|
#include <linux/device.h>
|
|
|
|
|
#include <linux/delay.h>
|
|
|
|
|
#include <linux/dma-mapping.h>
|
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
|
#include <linux/err.h>
|
|
|
|
|
#include <linux/clk.h>
|
|
|
|
|
#include <linux/io.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
|
|
|
|
#include <linux/slab.h>
|
2011-02-02 20:22:15 +08:00
|
|
|
|
#include <linux/pm_runtime.h>
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
#include <linux/spi/spi.h>
|
|
|
|
|
|
2009-10-21 00:40:47 +08:00
|
|
|
|
#include <plat/dma.h>
|
|
|
|
|
#include <plat/clock.h>
|
2010-04-13 18:41:51 +08:00
|
|
|
|
#include <plat/mcspi.h>
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
#define OMAP2_MCSPI_MAX_FREQ 48000000
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
|
|
|
|
|
#define OMAP2_MCSPI_MAX_CTRL 4
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
#define OMAP2_MCSPI_REVISION 0x00
|
|
|
|
|
#define OMAP2_MCSPI_SYSSTATUS 0x14
|
|
|
|
|
#define OMAP2_MCSPI_IRQSTATUS 0x18
|
|
|
|
|
#define OMAP2_MCSPI_IRQENABLE 0x1c
|
|
|
|
|
#define OMAP2_MCSPI_WAKEUPENABLE 0x20
|
|
|
|
|
#define OMAP2_MCSPI_SYST 0x24
|
|
|
|
|
#define OMAP2_MCSPI_MODULCTRL 0x28
|
|
|
|
|
|
|
|
|
|
/* per-channel banks, 0x14 bytes each, first is: */
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF0 0x2c
|
|
|
|
|
#define OMAP2_MCSPI_CHSTAT0 0x30
|
|
|
|
|
#define OMAP2_MCSPI_CHCTRL0 0x34
|
|
|
|
|
#define OMAP2_MCSPI_TX0 0x38
|
|
|
|
|
#define OMAP2_MCSPI_RX0 0x3c
|
|
|
|
|
|
|
|
|
|
/* per-register bitmasks: */
|
|
|
|
|
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
|
|
|
|
|
#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
|
|
|
|
|
#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_POL BIT(1)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_IS BIT(18)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
|
|
|
|
|
#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
|
|
|
|
|
#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
|
|
|
|
|
#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2009-09-23 07:45:58 +08:00
|
|
|
|
#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* We have 2 DMA channels per CS, one for RX and one for TX */
|
|
|
|
|
struct omap2_mcspi_dma {
|
|
|
|
|
int dma_tx_channel;
|
|
|
|
|
int dma_rx_channel;
|
|
|
|
|
|
|
|
|
|
int dma_tx_sync_dev;
|
|
|
|
|
int dma_rx_sync_dev;
|
|
|
|
|
|
|
|
|
|
struct completion dma_tx_completion;
|
|
|
|
|
struct completion dma_rx_completion;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
|
|
|
|
|
* cache operations; better heuristics consider wordsize and bitrate.
|
|
|
|
|
*/
|
2010-04-12 17:07:54 +08:00
|
|
|
|
#define DMA_MIN_BYTES 160
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
struct omap2_mcspi {
|
|
|
|
|
struct work_struct work;
|
|
|
|
|
/* lock protects queue and registers */
|
|
|
|
|
spinlock_t lock;
|
|
|
|
|
struct list_head msg_queue;
|
|
|
|
|
struct spi_master *master;
|
|
|
|
|
/* Virtual base address of the controller */
|
|
|
|
|
void __iomem *base;
|
2008-09-02 04:51:50 +08:00
|
|
|
|
unsigned long phys;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
/* SPI1 has 4 channels, while SPI2 has 2 */
|
|
|
|
|
struct omap2_mcspi_dma *dma_channels;
|
2011-02-02 20:22:15 +08:00
|
|
|
|
struct device *dev;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct omap2_mcspi_cs {
|
|
|
|
|
void __iomem *base;
|
2008-09-02 04:51:50 +08:00
|
|
|
|
unsigned long phys;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
int word_len;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
struct list_head node;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
/* Context save and restore shadow register */
|
|
|
|
|
u32 chconf0;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* used for context save and restore, structure members to be updated whenever
|
|
|
|
|
* corresponding registers are modified.
|
|
|
|
|
*/
|
|
|
|
|
struct omap2_mcspi_regs {
|
|
|
|
|
u32 modulctrl;
|
|
|
|
|
u32 wakeupenable;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
struct list_head cs;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
};
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static struct workqueue_struct *omap2_mcspi_wq;
|
|
|
|
|
|
|
|
|
|
#define MOD_REG_BIT(val, mask, set) do { \
|
|
|
|
|
if (set) \
|
|
|
|
|
val |= mask; \
|
|
|
|
|
else \
|
|
|
|
|
val &= ~mask; \
|
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
|
|
static inline void mcspi_write_reg(struct spi_master *master,
|
|
|
|
|
int idx, u32 val)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
|
|
__raw_writel(val, mcspi->base + idx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
|
|
return __raw_readl(mcspi->base + idx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void mcspi_write_cs_reg(const struct spi_device *spi,
|
|
|
|
|
int idx, u32 val)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
|
|
|
|
|
__raw_writel(val, cs->base + idx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
|
|
|
|
|
return __raw_readl(cs->base + idx);
|
|
|
|
|
}
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
|
|
|
|
|
return cs->chconf0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
|
|
|
|
|
cs->chconf0 = val;
|
|
|
|
|
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
|
2010-03-15 17:06:28 +08:00
|
|
|
|
mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
|
|
|
|
|
int is_read, int enable)
|
|
|
|
|
{
|
|
|
|
|
u32 l, rw;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
if (is_read) /* 1 is read, 0 write */
|
|
|
|
|
rw = OMAP2_MCSPI_CHCONF_DMAR;
|
|
|
|
|
else
|
|
|
|
|
rw = OMAP2_MCSPI_CHCONF_DMAW;
|
|
|
|
|
|
|
|
|
|
MOD_REG_BIT(l, rw, enable);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
mcspi_write_chconf0(spi, l);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
|
|
|
|
|
{
|
|
|
|
|
u32 l;
|
|
|
|
|
|
|
|
|
|
l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
|
|
|
|
|
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
|
2010-04-13 18:41:51 +08:00
|
|
|
|
/* Flash post-writes */
|
|
|
|
|
mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
|
|
|
|
|
{
|
|
|
|
|
u32 l;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
mcspi_write_chconf0(spi, l);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_set_master_mode(struct spi_master *master)
|
|
|
|
|
{
|
|
|
|
|
u32 l;
|
|
|
|
|
|
|
|
|
|
/* setup when switching from (reset default) slave mode
|
|
|
|
|
* to single-channel master mode
|
|
|
|
|
*/
|
|
|
|
|
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
|
|
|
|
|
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
|
|
|
|
|
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
|
|
|
|
|
MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
|
|
|
|
|
omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *spi_cntrl;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
struct omap2_mcspi_cs *cs;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
spi_cntrl = mcspi->master;
|
|
|
|
|
|
|
|
|
|
/* McSPI: context restore */
|
|
|
|
|
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
|
|
|
|
|
omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
|
|
|
|
|
|
|
|
|
|
mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
|
|
|
|
|
omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
|
2009-09-23 07:46:17 +08:00
|
|
|
|
|
|
|
|
|
list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
|
|
|
|
|
node)
|
|
|
|
|
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
}
|
|
|
|
|
static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
|
|
|
|
|
{
|
2011-02-02 20:22:15 +08:00
|
|
|
|
pm_runtime_put_sync(mcspi->dev);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
|
|
|
|
|
{
|
2011-02-02 20:22:15 +08:00
|
|
|
|
return pm_runtime_get_sync(mcspi->dev);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2010-10-19 22:07:31 +08:00
|
|
|
|
static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
|
|
|
|
|
{
|
|
|
|
|
unsigned long timeout;
|
|
|
|
|
|
|
|
|
|
timeout = jiffies + msecs_to_jiffies(1000);
|
|
|
|
|
while (!(__raw_readl(reg) & bit)) {
|
|
|
|
|
if (time_after(jiffies, timeout))
|
|
|
|
|
return -1;
|
|
|
|
|
cpu_relax();
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static unsigned
|
|
|
|
|
omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
unsigned int count, c;
|
|
|
|
|
unsigned long base, tx_reg, rx_reg;
|
|
|
|
|
int word_len, data_type, element_count;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
int elements;
|
|
|
|
|
u32 l;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
u8 * rx;
|
|
|
|
|
const u8 * tx;
|
2010-10-19 22:07:31 +08:00
|
|
|
|
void __iomem *chstat_reg;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
2010-04-13 18:41:51 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2010-10-19 22:07:31 +08:00
|
|
|
|
chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
count = xfer->len;
|
|
|
|
|
c = count;
|
|
|
|
|
word_len = cs->word_len;
|
|
|
|
|
|
2008-09-02 04:51:50 +08:00
|
|
|
|
base = cs->phys;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
tx_reg = base + OMAP2_MCSPI_TX0;
|
|
|
|
|
rx_reg = base + OMAP2_MCSPI_RX0;
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
|
|
|
|
|
if (word_len <= 8) {
|
|
|
|
|
data_type = OMAP_DMA_DATA_TYPE_S8;
|
|
|
|
|
element_count = count;
|
|
|
|
|
} else if (word_len <= 16) {
|
|
|
|
|
data_type = OMAP_DMA_DATA_TYPE_S16;
|
|
|
|
|
element_count = count >> 1;
|
|
|
|
|
} else /* word_len <= 32 */ {
|
|
|
|
|
data_type = OMAP_DMA_DATA_TYPE_S32;
|
|
|
|
|
element_count = count >> 2;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
|
|
|
|
|
data_type, element_count, 1,
|
|
|
|
|
OMAP_DMA_SYNC_ELEMENT,
|
|
|
|
|
mcspi_dma->dma_tx_sync_dev, 0);
|
|
|
|
|
|
|
|
|
|
omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
|
|
|
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
|
|
|
tx_reg, 0, 0);
|
|
|
|
|
|
|
|
|
|
omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
|
|
|
|
|
OMAP_DMA_AMODE_POST_INC,
|
|
|
|
|
xfer->tx_dma, 0, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (rx != NULL) {
|
2010-04-13 18:41:51 +08:00
|
|
|
|
elements = element_count - 1;
|
|
|
|
|
if (l & OMAP2_MCSPI_CHCONF_TURBO)
|
|
|
|
|
elements--;
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
|
2010-04-13 18:41:51 +08:00
|
|
|
|
data_type, elements, 1,
|
2007-07-17 19:04:13 +08:00
|
|
|
|
OMAP_DMA_SYNC_ELEMENT,
|
|
|
|
|
mcspi_dma->dma_rx_sync_dev, 1);
|
|
|
|
|
|
|
|
|
|
omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
|
|
|
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
|
|
|
rx_reg, 0, 0);
|
|
|
|
|
|
|
|
|
|
omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
|
|
|
|
|
OMAP_DMA_AMODE_POST_INC,
|
|
|
|
|
xfer->rx_dma, 0, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
omap_start_dma(mcspi_dma->dma_tx_channel);
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 0, 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
omap_start_dma(mcspi_dma->dma_rx_channel);
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 1, 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
wait_for_completion(&mcspi_dma->dma_tx_completion);
|
2011-01-07 23:49:20 +08:00
|
|
|
|
dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
|
2010-10-19 22:07:31 +08:00
|
|
|
|
|
|
|
|
|
/* for TX_ONLY mode, be sure all words have shifted out */
|
|
|
|
|
if (rx == NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0)
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
else if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_EOT) < 0)
|
|
|
|
|
dev_err(&spi->dev, "EOT timed out\n");
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
wait_for_completion(&mcspi_dma->dma_rx_completion);
|
2011-01-07 23:49:20 +08:00
|
|
|
|
dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
|
2009-07-30 06:02:12 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (l & OMAP2_MCSPI_CHCONF_TURBO) {
|
|
|
|
|
|
|
|
|
|
if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
|
|
|
|
|
& OMAP2_MCSPI_CHSTAT_RXS)) {
|
|
|
|
|
u32 w;
|
|
|
|
|
|
|
|
|
|
w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
|
|
|
|
|
if (word_len <= 8)
|
|
|
|
|
((u8 *)xfer->rx_buf)[elements++] = w;
|
|
|
|
|
else if (word_len <= 16)
|
|
|
|
|
((u16 *)xfer->rx_buf)[elements++] = w;
|
|
|
|
|
else /* word_len <= 32 */
|
|
|
|
|
((u32 *)xfer->rx_buf)[elements++] = w;
|
|
|
|
|
} else {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"DMA RX penultimate word empty");
|
|
|
|
|
count -= (word_len <= 8) ? 2 :
|
|
|
|
|
(word_len <= 16) ? 4 :
|
|
|
|
|
/* word_len <= 32 */ 8;
|
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2009-07-30 06:02:12 +08:00
|
|
|
|
if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
|
|
|
|
|
& OMAP2_MCSPI_CHSTAT_RXS)) {
|
|
|
|
|
u32 w;
|
|
|
|
|
|
|
|
|
|
w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
|
|
|
|
|
if (word_len <= 8)
|
2010-04-13 18:41:51 +08:00
|
|
|
|
((u8 *)xfer->rx_buf)[elements] = w;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
else if (word_len <= 16)
|
2010-04-13 18:41:51 +08:00
|
|
|
|
((u16 *)xfer->rx_buf)[elements] = w;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
else /* word_len <= 32 */
|
2010-04-13 18:41:51 +08:00
|
|
|
|
((u32 *)xfer->rx_buf)[elements] = w;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
} else {
|
|
|
|
|
dev_err(&spi->dev, "DMA RX last word empty");
|
|
|
|
|
count -= (word_len <= 8) ? 1 :
|
|
|
|
|
(word_len <= 16) ? 2 :
|
|
|
|
|
/* word_len <= 32 */ 4;
|
|
|
|
|
}
|
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
|
omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
unsigned int count, c;
|
|
|
|
|
u32 l;
|
|
|
|
|
void __iomem *base = cs->base;
|
|
|
|
|
void __iomem *tx_reg;
|
|
|
|
|
void __iomem *rx_reg;
|
|
|
|
|
void __iomem *chstat_reg;
|
|
|
|
|
int word_len;
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
count = xfer->len;
|
|
|
|
|
c = count;
|
|
|
|
|
word_len = cs->word_len;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* We store the pre-calculated register addresses on stack to speed
|
|
|
|
|
* up the transfer loop. */
|
|
|
|
|
tx_reg = base + OMAP2_MCSPI_TX0;
|
|
|
|
|
rx_reg = base + OMAP2_MCSPI_RX0;
|
|
|
|
|
chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
|
|
|
|
|
|
|
|
|
|
if (word_len <= 8) {
|
|
|
|
|
u8 *rx;
|
|
|
|
|
const u8 *tx;
|
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
|
|
|
|
|
do {
|
2008-01-25 06:00:40 +08:00
|
|
|
|
c -= 1;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "write-%d %02x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *tx);
|
|
|
|
|
__raw_writel(*tx++, tx_reg);
|
|
|
|
|
}
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (c == 1 && tx == NULL &&
|
|
|
|
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
*rx++ = __raw_readl(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
2010-04-13 18:41:51 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
c = 0;
|
|
|
|
|
} else if (c == 0 && tx == NULL) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
*rx++ = __raw_readl(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
}
|
|
|
|
|
} while (c);
|
|
|
|
|
} else if (word_len <= 16) {
|
|
|
|
|
u16 *rx;
|
|
|
|
|
const u16 *tx;
|
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
do {
|
2008-01-25 06:00:40 +08:00
|
|
|
|
c -= 2;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "write-%d %04x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *tx);
|
|
|
|
|
__raw_writel(*tx++, tx_reg);
|
|
|
|
|
}
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (c == 2 && tx == NULL &&
|
|
|
|
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
*rx++ = __raw_readl(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
2010-04-13 18:41:51 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
c = 0;
|
|
|
|
|
} else if (c == 0 && tx == NULL) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
*rx++ = __raw_readl(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
}
|
|
|
|
|
} while (c);
|
|
|
|
|
} else if (word_len <= 32) {
|
|
|
|
|
u32 *rx;
|
|
|
|
|
const u32 *tx;
|
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
do {
|
2008-01-25 06:00:40 +08:00
|
|
|
|
c -= 4;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "write-%d %08x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *tx);
|
|
|
|
|
__raw_writel(*tx++, tx_reg);
|
|
|
|
|
}
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (c == 4 && tx == NULL &&
|
|
|
|
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
*rx++ = __raw_readl(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
2010-04-13 18:41:51 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
c = 0;
|
|
|
|
|
} else if (c == 0 && tx == NULL) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
*rx++ = __raw_readl(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
}
|
|
|
|
|
} while (c);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* for TX_ONLY mode, be sure all words have shifted out */
|
|
|
|
|
if (xfer->rx_buf == NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
} else if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_EOT) < 0)
|
|
|
|
|
dev_err(&spi->dev, "EOT timed out\n");
|
2010-10-19 18:03:27 +08:00
|
|
|
|
|
|
|
|
|
/* disable chan to purge rx datas received in TX_ONLY transfer,
|
|
|
|
|
* otherwise these rx datas will affect the direct following
|
|
|
|
|
* RX_ONLY transfer.
|
|
|
|
|
*/
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
out:
|
2010-04-13 18:41:51 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return count - c;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* called only when no transfer is active to this device */
|
|
|
|
|
static int omap2_mcspi_setup_transfer(struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *t)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
struct spi_master *spi_cntrl;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
u32 l = 0, div = 0;
|
|
|
|
|
u8 word_len = spi->bits_per_word;
|
2010-03-11 05:23:13 +08:00
|
|
|
|
u32 speed_hz = spi->max_speed_hz;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
spi_cntrl = mcspi->master;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
if (t != NULL && t->bits_per_word)
|
|
|
|
|
word_len = t->bits_per_word;
|
|
|
|
|
|
|
|
|
|
cs->word_len = word_len;
|
|
|
|
|
|
2010-03-11 05:23:13 +08:00
|
|
|
|
if (t && t->speed_hz)
|
|
|
|
|
speed_hz = t->speed_hz;
|
|
|
|
|
|
|
|
|
|
if (speed_hz) {
|
2007-07-17 19:04:13 +08:00
|
|
|
|
while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
|
2010-03-11 05:23:13 +08:00
|
|
|
|
> speed_hz)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
div++;
|
|
|
|
|
} else
|
|
|
|
|
div = 15;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
|
|
|
|
|
* REVISIT: this controller could support SPI_3WIRE mode.
|
|
|
|
|
*/
|
|
|
|
|
l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_DPE0;
|
|
|
|
|
|
|
|
|
|
/* wordlength */
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
|
|
|
|
|
l |= (word_len - 1) << 7;
|
|
|
|
|
|
|
|
|
|
/* set chipselect polarity; manage with FORCE */
|
|
|
|
|
if (!(spi->mode & SPI_CS_HIGH))
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_EPOL;
|
|
|
|
|
|
|
|
|
|
/* set clock divisor */
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
|
|
|
|
|
l |= div << 2;
|
|
|
|
|
|
|
|
|
|
/* set SPI mode 0..3 */
|
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_POL;
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_POL;
|
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_PHA;
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_PHA;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
mcspi_write_chconf0(spi, l);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
|
|
|
|
|
OMAP2_MCSPI_MAX_FREQ / (1 << div),
|
|
|
|
|
(spi->mode & SPI_CPHA) ? "trailing" : "leading",
|
|
|
|
|
(spi->mode & SPI_CPOL) ? "inverted" : "normal");
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct spi_device *spi = data;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
|
|
|
|
|
|
|
|
|
|
complete(&mcspi_dma->dma_rx_completion);
|
|
|
|
|
|
|
|
|
|
/* We must disable the DMA RX request */
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 1, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct spi_device *spi = data;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
|
|
|
|
|
|
|
|
|
|
complete(&mcspi_dma->dma_tx_completion);
|
|
|
|
|
|
|
|
|
|
/* We must disable the DMA TX request */
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 0, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int omap2_mcspi_request_dma(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *master = spi->master;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
mcspi_dma = mcspi->dma_channels + spi->chip_select;
|
|
|
|
|
|
|
|
|
|
if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
|
|
|
|
|
omap2_mcspi_dma_rx_callback, spi,
|
|
|
|
|
&mcspi_dma->dma_rx_channel)) {
|
|
|
|
|
dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
|
|
|
|
|
return -EAGAIN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
|
|
|
|
|
omap2_mcspi_dma_tx_callback, spi,
|
|
|
|
|
&mcspi_dma->dma_tx_channel)) {
|
|
|
|
|
omap_free_dma(mcspi_dma->dma_rx_channel);
|
|
|
|
|
mcspi_dma->dma_rx_channel = -1;
|
|
|
|
|
dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
|
|
|
|
|
return -EAGAIN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
init_completion(&mcspi_dma->dma_rx_completion);
|
|
|
|
|
init_completion(&mcspi_dma->dma_tx_completion);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int omap2_mcspi_setup(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
|
2009-06-18 07:26:03 +08:00
|
|
|
|
if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
|
2007-07-17 19:04:13 +08:00
|
|
|
|
dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
|
|
|
|
|
spi->bits_per_word);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
if (!cs) {
|
|
|
|
|
cs = kzalloc(sizeof *cs, GFP_KERNEL);
|
|
|
|
|
if (!cs)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
cs->base = mcspi->base + spi->chip_select * 0x14;
|
2008-09-02 04:51:50 +08:00
|
|
|
|
cs->phys = mcspi->phys + spi->chip_select * 0x14;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
cs->chconf0 = 0;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
spi->controller_state = cs;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
/* Link this to context save list */
|
|
|
|
|
list_add_tail(&cs->node,
|
|
|
|
|
&omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mcspi_dma->dma_rx_channel == -1
|
|
|
|
|
|| mcspi_dma->dma_tx_channel == -1) {
|
|
|
|
|
ret = omap2_mcspi_request_dma(spi);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
ret = omap2_mcspi_enable_clocks(mcspi);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
|
2007-10-16 16:27:45 +08:00
|
|
|
|
ret = omap2_mcspi_setup_transfer(spi, NULL);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_cleanup(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
struct omap2_mcspi_cs *cs;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
|
2010-03-11 05:22:45 +08:00
|
|
|
|
if (spi->controller_state) {
|
|
|
|
|
/* Unlink controller state from context save list */
|
|
|
|
|
cs = spi->controller_state;
|
|
|
|
|
list_del(&cs->node);
|
2009-09-23 07:46:17 +08:00
|
|
|
|
|
2010-03-11 05:22:45 +08:00
|
|
|
|
kfree(spi->controller_state);
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2010-05-24 22:20:27 +08:00
|
|
|
|
if (spi->chip_select < spi->master->num_chipselect) {
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
if (mcspi_dma->dma_rx_channel != -1) {
|
|
|
|
|
omap_free_dma(mcspi_dma->dma_rx_channel);
|
|
|
|
|
mcspi_dma->dma_rx_channel = -1;
|
|
|
|
|
}
|
|
|
|
|
if (mcspi_dma->dma_tx_channel != -1) {
|
|
|
|
|
omap_free_dma(mcspi_dma->dma_tx_channel);
|
|
|
|
|
mcspi_dma->dma_tx_channel = -1;
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_work(struct work_struct *work)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
|
|
|
|
|
mcspi = container_of(work, struct omap2_mcspi, work);
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
if (omap2_mcspi_enable_clocks(mcspi) < 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
spin_lock_irq(&mcspi->lock);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* We only enable one channel at a time -- the one whose message is
|
|
|
|
|
* at the head of the queue -- although this controller would gladly
|
|
|
|
|
* arbitrate among multiple channels. This corresponds to "single
|
|
|
|
|
* channel" master mode. As a side effect, we need to manage the
|
|
|
|
|
* chipselect with the FORCE bit ... CS != channel enable.
|
|
|
|
|
*/
|
|
|
|
|
while (!list_empty(&mcspi->msg_queue)) {
|
|
|
|
|
struct spi_message *m;
|
|
|
|
|
struct spi_device *spi;
|
|
|
|
|
struct spi_transfer *t = NULL;
|
|
|
|
|
int cs_active = 0;
|
|
|
|
|
struct omap2_mcspi_cs *cs;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
struct omap2_mcspi_device_config *cd;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
int par_override = 0;
|
|
|
|
|
int status = 0;
|
|
|
|
|
u32 chconf;
|
|
|
|
|
|
|
|
|
|
m = container_of(mcspi->msg_queue.next, struct spi_message,
|
|
|
|
|
queue);
|
|
|
|
|
|
|
|
|
|
list_del_init(&m->queue);
|
|
|
|
|
spin_unlock_irq(&mcspi->lock);
|
|
|
|
|
|
|
|
|
|
spi = m->spi;
|
|
|
|
|
cs = spi->controller_state;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
cd = spi->controller_data;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
|
|
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
|
|
|
if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
|
|
|
|
|
status = -EINVAL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (par_override || t->speed_hz || t->bits_per_word) {
|
|
|
|
|
par_override = 1;
|
|
|
|
|
status = omap2_mcspi_setup_transfer(spi, t);
|
|
|
|
|
if (status < 0)
|
|
|
|
|
break;
|
|
|
|
|
if (!t->speed_hz && !t->bits_per_word)
|
|
|
|
|
par_override = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!cs_active) {
|
|
|
|
|
omap2_mcspi_force_cs(spi, 1);
|
|
|
|
|
cs_active = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
chconf = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (t->tx_buf == NULL)
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
|
|
|
|
|
else if (t->rx_buf == NULL)
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (cd && cd->turbo_mode && t->tx_buf == NULL) {
|
|
|
|
|
/* Turbo mode is for more than one word */
|
|
|
|
|
if (t->len > ((cs->word_len + 7) >> 3))
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_TURBO;
|
|
|
|
|
}
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
mcspi_write_chconf0(spi, chconf);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
if (t->len) {
|
|
|
|
|
unsigned count;
|
|
|
|
|
|
|
|
|
|
/* RX_ONLY mode needs dummy data in TX reg */
|
|
|
|
|
if (t->tx_buf == NULL)
|
|
|
|
|
__raw_writel(0, cs->base
|
|
|
|
|
+ OMAP2_MCSPI_TX0);
|
|
|
|
|
|
|
|
|
|
if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
|
|
|
|
|
count = omap2_mcspi_txrx_dma(spi, t);
|
|
|
|
|
else
|
|
|
|
|
count = omap2_mcspi_txrx_pio(spi, t);
|
|
|
|
|
m->actual_length += count;
|
|
|
|
|
|
|
|
|
|
if (count != t->len) {
|
|
|
|
|
status = -EIO;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (t->delay_usecs)
|
|
|
|
|
udelay(t->delay_usecs);
|
|
|
|
|
|
|
|
|
|
/* ignore the "leave it on after last xfer" hint */
|
|
|
|
|
if (t->cs_change) {
|
|
|
|
|
omap2_mcspi_force_cs(spi, 0);
|
|
|
|
|
cs_active = 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Restore defaults if they were overriden */
|
|
|
|
|
if (par_override) {
|
|
|
|
|
par_override = 0;
|
|
|
|
|
status = omap2_mcspi_setup_transfer(spi, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cs_active)
|
|
|
|
|
omap2_mcspi_force_cs(spi, 0);
|
|
|
|
|
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
|
|
|
|
|
m->status = status;
|
|
|
|
|
m->complete(m->context);
|
|
|
|
|
|
|
|
|
|
spin_lock_irq(&mcspi->lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spin_unlock_irq(&mcspi->lock);
|
2011-02-02 20:22:15 +08:00
|
|
|
|
|
|
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
struct spi_transfer *t;
|
|
|
|
|
|
|
|
|
|
m->actual_length = 0;
|
|
|
|
|
m->status = 0;
|
|
|
|
|
|
|
|
|
|
/* reject invalid messages and transfers */
|
|
|
|
|
if (list_empty(&m->transfers) || !m->complete)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
|
|
|
const void *tx_buf = t->tx_buf;
|
|
|
|
|
void *rx_buf = t->rx_buf;
|
|
|
|
|
unsigned len = t->len;
|
|
|
|
|
|
|
|
|
|
if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
|
|
|
|
|
|| (len && !(rx_buf || tx_buf))
|
|
|
|
|
|| (t->bits_per_word &&
|
|
|
|
|
( t->bits_per_word < 4
|
|
|
|
|
|| t->bits_per_word > 32))) {
|
|
|
|
|
dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
|
|
|
|
|
t->speed_hz,
|
|
|
|
|
len,
|
|
|
|
|
tx_buf ? "tx" : "",
|
|
|
|
|
rx_buf ? "rx" : "",
|
|
|
|
|
t->bits_per_word);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
|
|
|
|
|
dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
|
|
|
|
|
t->speed_hz,
|
|
|
|
|
OMAP2_MCSPI_MAX_FREQ/(1<<16));
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (m->is_dma_mapped || len < DMA_MIN_BYTES)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (tx_buf != NULL) {
|
|
|
|
|
t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
|
|
|
|
|
len, DMA_TO_DEVICE);
|
2008-07-26 10:44:49 +08:00
|
|
|
|
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
|
2007-07-17 19:04:13 +08:00
|
|
|
|
dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
|
|
|
|
|
'T', len);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (rx_buf != NULL) {
|
|
|
|
|
t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
|
|
|
|
|
DMA_FROM_DEVICE);
|
2008-07-26 10:44:49 +08:00
|
|
|
|
if (dma_mapping_error(&spi->dev, t->rx_dma)) {
|
2007-07-17 19:04:13 +08:00
|
|
|
|
dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
|
|
|
|
|
'R', len);
|
|
|
|
|
if (tx_buf != NULL)
|
2011-01-07 23:49:20 +08:00
|
|
|
|
dma_unmap_single(&spi->dev, t->tx_dma,
|
2007-07-17 19:04:13 +08:00
|
|
|
|
len, DMA_TO_DEVICE);
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&mcspi->lock, flags);
|
|
|
|
|
list_add_tail(&m->queue, &mcspi->msg_queue);
|
|
|
|
|
queue_work(omap2_mcspi_wq, &mcspi->work);
|
|
|
|
|
spin_unlock_irqrestore(&mcspi->lock, flags);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
|
|
|
|
struct spi_master *master = mcspi->master;
|
|
|
|
|
u32 tmp;
|
2011-02-02 20:22:15 +08:00
|
|
|
|
int ret = 0;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
ret = omap2_mcspi_enable_clocks(mcspi);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
2009-07-30 06:02:11 +08:00
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
|
|
|
|
|
omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
omap2_mcspi_set_master_mode(master);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
static int omap_mcspi_runtime_resume(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct spi_master *master;
|
|
|
|
|
|
|
|
|
|
master = dev_get_drvdata(dev);
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
omap2_mcspi_restore_ctx(mcspi);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-06 17:38:16 +08:00
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static int __init omap2_mcspi_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *master;
|
2011-02-02 20:22:14 +08:00
|
|
|
|
struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct resource *r;
|
|
|
|
|
int status = 0, i;
|
|
|
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
|
|
|
|
|
if (master == NULL) {
|
|
|
|
|
dev_dbg(&pdev->dev, "master allocation failed\n");
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
|
2009-06-18 07:26:04 +08:00
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (pdev->id != -1)
|
|
|
|
|
master->bus_num = pdev->id;
|
|
|
|
|
|
|
|
|
|
master->setup = omap2_mcspi_setup;
|
|
|
|
|
master->transfer = omap2_mcspi_transfer;
|
|
|
|
|
master->cleanup = omap2_mcspi_cleanup;
|
2011-02-02 20:22:14 +08:00
|
|
|
|
master->num_chipselect = pdata->num_cs;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
dev_set_drvdata(&pdev->dev, master);
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
mcspi->master = master;
|
|
|
|
|
|
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
if (r == NULL) {
|
|
|
|
|
status = -ENODEV;
|
|
|
|
|
goto err1;
|
|
|
|
|
}
|
|
|
|
|
if (!request_mem_region(r->start, (r->end - r->start) + 1,
|
2009-03-25 07:38:21 +08:00
|
|
|
|
dev_name(&pdev->dev))) {
|
2007-07-17 19:04:13 +08:00
|
|
|
|
status = -EBUSY;
|
|
|
|
|
goto err1;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-02 20:22:14 +08:00
|
|
|
|
r->start += pdata->regs_offset;
|
|
|
|
|
r->end += pdata->regs_offset;
|
2008-09-02 04:51:50 +08:00
|
|
|
|
mcspi->phys = r->start;
|
2008-09-04 21:07:22 +08:00
|
|
|
|
mcspi->base = ioremap(r->start, r->end - r->start + 1);
|
|
|
|
|
if (!mcspi->base) {
|
|
|
|
|
dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
|
|
|
|
|
status = -ENOMEM;
|
2011-02-02 20:22:15 +08:00
|
|
|
|
goto err2;
|
2008-09-04 21:07:22 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
mcspi->dev = &pdev->dev;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
INIT_WORK(&mcspi->work, omap2_mcspi_work);
|
|
|
|
|
|
|
|
|
|
spin_lock_init(&mcspi->lock);
|
|
|
|
|
INIT_LIST_HEAD(&mcspi->msg_queue);
|
2009-09-23 07:46:17 +08:00
|
|
|
|
INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi->dma_channels = kcalloc(master->num_chipselect,
|
|
|
|
|
sizeof(struct omap2_mcspi_dma),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
|
|
if (mcspi->dma_channels == NULL)
|
2011-02-02 20:22:15 +08:00
|
|
|
|
goto err2;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2011-02-02 20:22:14 +08:00
|
|
|
|
for (i = 0; i < master->num_chipselect; i++) {
|
|
|
|
|
char dma_ch_name[14];
|
|
|
|
|
struct resource *dma_res;
|
|
|
|
|
|
|
|
|
|
sprintf(dma_ch_name, "rx%d", i);
|
|
|
|
|
dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
|
|
|
|
|
dma_ch_name);
|
|
|
|
|
if (!dma_res) {
|
|
|
|
|
dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
|
|
|
|
|
status = -ENODEV;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
mcspi->dma_channels[i].dma_rx_channel = -1;
|
2011-02-02 20:22:14 +08:00
|
|
|
|
mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
|
|
|
|
|
sprintf(dma_ch_name, "tx%d", i);
|
|
|
|
|
dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
|
|
|
|
|
dma_ch_name);
|
|
|
|
|
if (!dma_res) {
|
|
|
|
|
dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
|
|
|
|
|
status = -ENODEV;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
mcspi->dma_channels[i].dma_tx_channel = -1;
|
2011-02-02 20:22:14 +08:00
|
|
|
|
mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
|
|
|
|
if (status || omap2_mcspi_master_setup(mcspi) < 0)
|
|
|
|
|
goto err3;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
status = spi_register_master(master);
|
|
|
|
|
if (status < 0)
|
|
|
|
|
goto err4;
|
|
|
|
|
|
|
|
|
|
return status;
|
|
|
|
|
|
|
|
|
|
err4:
|
2011-02-02 20:22:15 +08:00
|
|
|
|
spi_master_put(master);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
err3:
|
2011-02-02 20:22:15 +08:00
|
|
|
|
kfree(mcspi->dma_channels);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
err2:
|
|
|
|
|
release_mem_region(r->start, (r->end - r->start) + 1);
|
2011-02-02 20:22:15 +08:00
|
|
|
|
iounmap(mcspi->base);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
err1:
|
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __exit omap2_mcspi_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *master;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *dma_channels;
|
|
|
|
|
struct resource *r;
|
2008-09-04 21:07:22 +08:00
|
|
|
|
void __iomem *base;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
master = dev_get_drvdata(&pdev->dev);
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
dma_channels = mcspi->dma_channels;
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
release_mem_region(r->start, (r->end - r->start) + 1);
|
|
|
|
|
|
2008-09-04 21:07:22 +08:00
|
|
|
|
base = mcspi->base;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
spi_unregister_master(master);
|
2008-09-04 21:07:22 +08:00
|
|
|
|
iounmap(base);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
kfree(dma_channels);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2008-04-11 12:29:20 +08:00
|
|
|
|
/* work with hotplug and coldplug */
|
|
|
|
|
MODULE_ALIAS("platform:omap2_mcspi");
|
|
|
|
|
|
2010-12-29 18:52:53 +08:00
|
|
|
|
#ifdef CONFIG_SUSPEND
|
|
|
|
|
/*
|
|
|
|
|
* When SPI wake up from off-mode, CS is in activate state. If it was in
|
|
|
|
|
* unactive state when driver was suspend, then force it to unactive state at
|
|
|
|
|
* wake up.
|
|
|
|
|
*/
|
|
|
|
|
static int omap2_mcspi_resume(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
struct omap2_mcspi_cs *cs;
|
|
|
|
|
|
|
|
|
|
omap2_mcspi_enable_clocks(mcspi);
|
|
|
|
|
list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
|
|
|
|
|
node) {
|
|
|
|
|
if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We need to toggle CS state for OMAP take this
|
|
|
|
|
* change in account.
|
|
|
|
|
*/
|
|
|
|
|
MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
|
|
|
|
|
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
|
|
|
|
|
__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
omap2_mcspi_disable_clocks(mcspi);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#else
|
|
|
|
|
#define omap2_mcspi_resume NULL
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static const struct dev_pm_ops omap2_mcspi_pm_ops = {
|
|
|
|
|
.resume = omap2_mcspi_resume,
|
2011-02-02 20:22:15 +08:00
|
|
|
|
.runtime_resume = omap_mcspi_runtime_resume,
|
2010-12-29 18:52:53 +08:00
|
|
|
|
};
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static struct platform_driver omap2_mcspi_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "omap2_mcspi",
|
|
|
|
|
.owner = THIS_MODULE,
|
2010-12-29 18:52:53 +08:00
|
|
|
|
.pm = &omap2_mcspi_pm_ops
|
2007-07-17 19:04:13 +08:00
|
|
|
|
},
|
|
|
|
|
.remove = __exit_p(omap2_mcspi_remove),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int __init omap2_mcspi_init(void)
|
|
|
|
|
{
|
|
|
|
|
omap2_mcspi_wq = create_singlethread_workqueue(
|
|
|
|
|
omap2_mcspi_driver.driver.name);
|
|
|
|
|
if (omap2_mcspi_wq == NULL)
|
|
|
|
|
return -1;
|
|
|
|
|
return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
|
|
|
|
|
}
|
|
|
|
|
subsys_initcall(omap2_mcspi_init);
|
|
|
|
|
|
|
|
|
|
static void __exit omap2_mcspi_exit(void)
|
|
|
|
|
{
|
|
|
|
|
platform_driver_unregister(&omap2_mcspi_driver);
|
|
|
|
|
|
|
|
|
|
destroy_workqueue(omap2_mcspi_wq);
|
|
|
|
|
}
|
|
|
|
|
module_exit(omap2_mcspi_exit);
|
|
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|