2007-10-16 07:41:44 +08:00
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/* atomic.S: These things are too big to do inline.
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2005-04-17 06:20:36 +08:00
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*
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2007-10-16 07:41:44 +08:00
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* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
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2005-04-17 06:20:36 +08:00
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*/
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2012-05-12 11:33:22 +08:00
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#include <linux/linkage.h>
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2005-04-17 06:20:36 +08:00
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#include <asm/asi.h>
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2007-10-16 07:41:44 +08:00
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#include <asm/backoff.h>
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2005-04-17 06:20:36 +08:00
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.text
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/* Two versions of the atomic routines, one that
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* does not return a value and does not perform
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* memory barriers, and a second which returns
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* a value and does the barriers.
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*/
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic_add) /* %o0 = increment, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: lduw [%o1], %g1
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add %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %icc, BACKOFF_LABEL(2f, 1b)
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2005-04-17 06:20:36 +08:00
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nop
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retl
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nop
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic_add)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic_sub) /* %o0 = decrement, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: lduw [%o1], %g1
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sub %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %icc, BACKOFF_LABEL(2f, 1b)
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2005-04-17 06:20:36 +08:00
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nop
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retl
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nop
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic_sub)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic_add_ret) /* %o0 = increment, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: lduw [%o1], %g1
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add %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %icc, BACKOFF_LABEL(2f, 1b)
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2010-08-18 16:03:37 +08:00
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add %g1, %o0, %g1
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2005-04-17 06:20:36 +08:00
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retl
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2010-08-18 16:03:37 +08:00
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sra %g1, 0, %o0
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic_add_ret)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: lduw [%o1], %g1
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sub %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %icc, BACKOFF_LABEL(2f, 1b)
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2010-08-18 16:03:37 +08:00
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sub %g1, %o0, %g1
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2005-04-17 06:20:36 +08:00
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retl
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2010-08-18 16:03:37 +08:00
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sra %g1, 0, %o0
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic_sub_ret)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic64_add) /* %o0 = increment, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: ldx [%o1], %g1
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add %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %xcc, BACKOFF_LABEL(2f, 1b)
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2005-04-17 06:20:36 +08:00
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nop
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retl
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nop
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic64_add)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic64_sub) /* %o0 = decrement, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: ldx [%o1], %g1
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sub %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %xcc, BACKOFF_LABEL(2f, 1b)
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2005-04-17 06:20:36 +08:00
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nop
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retl
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nop
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic64_sub)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic64_add_ret) /* %o0 = increment, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: ldx [%o1], %g1
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add %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %xcc, BACKOFF_LABEL(2f, 1b)
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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nop
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2010-08-18 16:03:37 +08:00
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retl
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add %g1, %o0, %o0
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic64_add_ret)
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2005-04-17 06:20:36 +08:00
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2012-05-12 11:33:22 +08:00
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ENTRY(atomic64_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */
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2007-10-16 07:41:44 +08:00
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BACKOFF_SETUP(%o2)
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2005-04-17 06:20:36 +08:00
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1: ldx [%o1], %g1
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sub %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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2010-08-19 13:53:26 +08:00
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bne,pn %xcc, BACKOFF_LABEL(2f, 1b)
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[SPARC64]: Avoid membar instructions in delay slots.
In particular, avoid membar instructions in the delay
slot of a jmpl instruction.
UltraSPARC-I, II, IIi, and IIe have a bug, documented in
the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
The long and short of it is that if the IMU unit misses
on a branch or jmpl, and there is a store buffer synchronizing
membar in the delay slot, the chip can stop fetching instructions.
If interrupts are enabled or some other trap is enabled, the
chip will unwedge itself, but performance will suffer.
We already had a workaround for this bug in a few spots, but
it's better to have the entire tree sanitized for this rule.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-06-28 06:42:04 +08:00
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nop
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2010-08-18 16:03:37 +08:00
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retl
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sub %g1, %o0, %o0
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2007-10-16 07:41:44 +08:00
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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2012-05-12 11:33:22 +08:00
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ENDPROC(atomic64_sub_ret)
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