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# EDK2 UEFI Firmware For Xiaomi MI 8 (Dipper)
Attempt to create a normal EDK2 for Xiaomi MI8 - dipper.
Based on zhuowei's port for [Pixel3XL](https://github.com/Pixel3Dev/edk2-pixel3/).
[![FOSSA Status](https://app.fossa.com/api/projects/git%2Bgithub.com%2FNekokeCore%2Fedk2-dipper.svg?type=shield)](https://app.fossa.com/projects/git%2Bgithub.com%2FNekokeCore%2Fedk2-dipper?ref=badge_shield)
[![FOSSA Status](https://app.fossa.com/api/projects/git%2Bgithub.com%2FNekokeCore%2Fedk2-dipper.svg?type=small)](https://app.fossa.com/projects/git%2Bgithub.com%2FNekokeCore%2Fedk2-dipper?ref=badge_small)
## The Most Important
DO NOT FLASH THIS UEFI FIRMWARE IN YOUR MAIN PHONE !!!
It's very unstable and you may lost your data.
## Status
UFS WORK！
Can boot Linux Arm
Clock WORK!
Test ACPI etc. tables removeed.
And can load Windows PE.
## Dev Logs
2020.1.6 Fix 5 compiler error.
2020.1.7 Start work and successfully run on my phone.
2020.1.8 Fix Display.
2020.4.17 Fix UFS drive and Fix MemoryMap（Thanks [Lemon1Ice](https://github.com/Lemon1Ice)）.
2020.4.19 Add ACPI etc. Tables and Fix DSDT 24 Errors. （PS.The ACPI and SSDT etc. Tables Provided by [5超级菜鸟5](https://github.com/sunshuyu)
2020.4.24 Fix Clock and The Clock is work well && Add SmemDxe SPI SPMI HWIODxeDriver PmicDxe ButtonsDxe ChipInfoDxe to Binary && Add USB driver
2020.4.30 Re added MemoryMap and can boot Windows to BlueScreen（Stop Code：Memory Managent） and （Stop Code：IRQL NOT LESS OR EQUAL）
2020.5.6 Fix A Lot but Nothing.
2020.5.8 Fix A Lot but Nothing.
2020.5.10 Can boot WindowsPE . Thank for [Lemon1Ice](https://github.com/Lemon1Ice) patience and great help！
## To-Do
1.Fix fts touchscreen
2.Fix ACPI tables
3.Partition UFS
4.make USB work
## Dependencies
Ubuntu 18.04:
```
sudo apt update
sudo apt install build-essential uuid-dev iasl git nasm python3-distutils gcc-aarch64-linux-gnu
```
Or
```
sudo apt update
sudo apt install build-essential
sudo apt install uuid-dev
sudo apt install iasl
sudo apt install git
sudo apt install nasm
sudo apt install python3-distutils
sudo apt install gcc-aarch64-linux-gnu
```
## Building
1.Clone edk2 and edk2-platforms (Place three directories side by side.)
edk2:
```
commit:3a3713e62cfad00d78bb938b0d9fb1eedaeff314
```
edk2-platforms:
```
commit:cfdc7f907d545b14302295b819ea078bc36c6a40
```
```
mkdir workspaceedk2
cd workspaceedk2
git clone https://github.com/tianocore/edk2.git --recursive
git clone https://github.com/tianocore/edk2-platforms.git
cd edk2
git checkout 3a3713e62cfad00d78bb938b0d9fb1eedaeff314
cd ..
cd edk2-platforms
git checkout cfdc7f907d545b14302295b819ea078bc36c6a40
```
2.Clone this project
```
git clone https://github.com/NekokeCore/edk2-dipper.git
```
3.Build eenvironment
```
cd edk2-dipper
mkdir workspace
bash firstrun.sh
```
4.Build this project
```
bash build.sh
```
5.Debug and use
```
fastboot boot uefi.img
```
## Credits
MemoryMap thanks [Lemon1Ice](https://github.com/Lemon1Ice).
ACPI etc. tables thanks [5超级菜鸟5](https://github.com/sunshuyu)
Orther edk2 project [EngLearnsh](https://github.com/EngLearnsh/edk2-dipper).
SimpleFbDxe screen driver is from imbushuo's [Lumia950XLPkg](https://github.com/WOA-Project/Lumia950XLPkg).
Also thanks [edk2 website](https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC#Install_required_software_from_apt).

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bootsize =
pagesize = 0x1000
kerneladdr = 0x8000
ramdiskaddr = 0x1000000
secondaddr = 0xf00000
tagsaddr = 0x100
name = thisconfig
cmdline =

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#!/bin/bash
# based on the instructions from edk2-platform
echo cleanning BuidFiles
rm -rf boot_polaris.img
echo Done.
set -e
. firstrun_common.sh
# not actually GCC5; it's GCC7 on Ubuntu 18.04.
GCC5_AARCH64_PREFIX=aarch64-linux-gnu- build -s -n 0 -a AARCH64 -t GCC5 -p sdm845Pkg/sdm845Pkg.dsc
gzip -c < workspace/Build/sdm845Pkg/DEBUG_GCC5/FV/sdm845PKG_UEFI.fd >uefi_img
cat ./device_specific/polaris.dtb >>uefi_img
abootimg --create boot_polaris.img -k uefi_img -r ramdisk -f bootimg.cfg
rm -rf ./uefi_img

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#!/bin/bash
# based on the instructions from edk2-platform
# do this first:
# https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Native-GCC#Install_required_software_from_apt
set -e
. firstrun_common.sh
make -C ../edk2/BaseTools

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export PACKAGES_PATH=$PWD/../edk2:$PWD/../edk2-platforms:$PWD
export WORKSPACE=$PWD/workspace
. ../edk2/edksetup.sh

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fake

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/** @file
Differentiated System Description Table Fields (SSDT)
Copyright (c) 2014-2015, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "ArmPlatform.h"
/*
See ACPI 6.1 Section 6.2.13
There are two ways that _PRT can be used. ...
In the first model, a PCI Link device is used to provide additional
configuration information such as whether the interrupt is Level or
Edge triggered, it is active High or Low, Shared or Exclusive, etc.
In the second model, the PCI interrupts are hardwired to specific
interrupt inputs on the interrupt controller and are not
configurable. In this case, the Source field in _PRT does not
reference a device, but instead contains the value zero, and the
Source Index field contains the global system interrupt to which the
PCI interrupt is hardwired.
We use the first model with link indirection to set the correct
interrupt type as PCI defaults (Level Triggered, Active Low) are not
compatible with GICv2.
*/
#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
Device(Link_Name) { \
Name(_HID, EISAID("PNP0C0F")) \
Name(_UID, Unique_Id) \
Name(_PRS, ResourceTemplate() { \
Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
}) \
Method (_CRS, 0) { Return (_PRS) } \
Method (_SRS, 1) { } \
Method (_DIS) { } \
}
#define PRT_ENTRY(Address, Pin, Link) \
Package (4) { \
Address, /* uses the same format as _ADR */ \
Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
Link, /* Interrupt allocated via Link device. */ \
Zero /* global system interrupt number (no used) */ \
}
/*
See Reference [1] 6.1.1
"High word–Device #, Low word–Function #. (for example, device 3, function 2 is
0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
*/
#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
// Device 0 for Bridge.
DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
Scope(_SB) {
//
// PCI Root Complex
//
LNK_DEVICE(1, LNKA, 168)
LNK_DEVICE(2, LNKB, 169)
LNK_DEVICE(3, LNKC, 170)
LNK_DEVICE(4, LNKD, 171)
Device(PCI0)
{
Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
Name(_SEG, Zero) // PCI Segment Group number
Name(_BBN, Zero) // PCI Base Bus Number
Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1)
// Root Complex 0
Device (RP0) {
Name(_ADR, 0xF0000000) // Dev 0, Func 0
}
// PCI Routing Table
Name(_PRT, Package() {
ROOT_PRT_ENTRY(0, LNKA), // INTA
ROOT_PRT_ENTRY(1, LNKB), // INTB
ROOT_PRT_ENTRY(2, LNKC), // INTC
ROOT_PRT_ENTRY(3, LNKD), // INTD
})
// Root complex resources
Method (_CRS, 0, Serialized) {
Name (RBUF, ResourceTemplate () {
WordBusNumber ( // Bus numbers assigned to this root
ResourceProducer,
MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
0, // AddressMinimum - Minimum Bus Number
255, // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
256 // RangeLength - Number of Busses
)
DWordMemory ( // 32-bit BAR Windows
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
0x50000000, // Min Base Address
0x57FFFFFF, // Max Base Address
0x00000000, // Translate
0x08000000 // Length
)
QWordMemory ( // 64-bit BAR Windows
ResourceProducer, PosDecode,
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
0x4000000000, // Min Base Address
0x40FFFFFFFF, // Max Base Address
0x00000000, // Translate
0x100000000 // Length
)
DWordIo ( // IO window
ResourceProducer,
MinFixed,
MaxFixed,
PosDecode,
EntireRange,
0x00000000, // Granularity
0x00000000, // Min Base Address
0x007fffff, // Max Base Address
0x5f800000, // Translate
0x00800000, // Length
,,,TypeTranslation
)
}) // Name(RBUF)
Return (RBUF)
} // Method(_CRS)
//
// OS Control Handoff
//
Name(SUPP, Zero) // PCI _OSC Support Field value
Name(CTRL, Zero) // PCI _OSC Control Field value
/*
See [1] 6.2.10, [2] 4.5
*/
Method(_OSC,4) {
// Check for proper UUID
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
// Create DWord-adressable fields from the Capabilities Buffer
CreateDWordField(Arg3,0,CDW1)
CreateDWordField(Arg3,4,CDW2)
CreateDWordField(Arg3,8,CDW3)
// Save Capabilities DWord2 & 3
Store(CDW2,SUPP)
Store(CDW3,CTRL)
// Only allow native hot plug control if OS supports:
// * ASPM
// * Clock PM
// * MSI/MSI-X
If(LNotEqual(And(SUPP, 0x16), 0x16)) {
And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
}
// Always allow native PME, AER (no dependencies)
// Never allow SHPC (no SHPC controller in this system)
And(CTRL,0x1D,CTRL)
#if 0
If(LNot(And(CDW1,1))) { // Query flag clear?
// Disable GPEs for features granted native control.
If(And(CTRL,0x01)) { // Hot plug control granted?
Store(0,HPCE) // clear the hot plug SCI enable bit
Store(1,HPCS) // clear the hot plug SCI status bit
}
If(And(CTRL,0x04)) { // PME control granted?
Store(0,PMCE) // clear the PME SCI enable bit
Store(1,PMCS) // clear the PME SCI status bit
}
If(And(CTRL,0x10)) { // OS restoring PCIe cap structure?
// Set status to not restore PCIe cap structure
// upon resume from S3
Store(1,S3CR)
}
}
#endif
If(LNotEqual(Arg1,One)) { // Unknown revision
Or(CDW1,0x08,CDW1)
}
If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
Or(CDW1,0x10,CDW1)
}
// Update DWORD3 in the buffer
Store(CTRL,CDW3)
Return(Arg3)
} Else {
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
} // End _OSC
} // PCI0
}
}

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## @file
#
# ACPI table data and ASL sources required to boot the platform.
#
# Copyright (c) 2014-2017, ARM Ltd. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = sdm845AcpiTables
FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD # Must be this
MODULE_TYPE = USER_DEFINED
VERSION_STRING = 1.0
[Sources]
Dsdt.asl
Dbg2.aslc
#Spcr.aslc
Fadt.aslc
Gtdt.aslc
Madt.aslc
#AcpiSsdtRootPci.asl # Juno R1 specific
[Packages]
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
sdm845Pkg/sdm845Pkg.dec
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdCoreCount
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
#
# PL011 UART Settings for Serial Port Console Redirection
#
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gArmPlatformTokenSpaceGuid.PL011UartClkInHz
gArmPlatformTokenSpaceGuid.PL011UartInterrupt
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
gArmPlatformTokenSpaceGuid.PcdWatchdogCount

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/** @file
* DBG2 Table
*
* Copyright (c) 2012-2016, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmPlatform.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/DebugPort2Table.h>
#pragma pack(1)
#define DBG2_NUM_DEBUG_PORTS 0
#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1
#define DBG2_NAMESPACESTRING_FIELD_SIZE 8
#define PL011_UART_LENGTH 0x1000
#define NAME_STR_UART1 {'C', 'O', 'M', '1', '\0', '\0', '\0', '\0'}
typedef struct {
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;
EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;
UINT32 AddressSize;
UINT8 NameSpaceString[DBG2_NAMESPACESTRING_FIELD_SIZE];
} DBG2_DEBUG_DEVICE_INFORMATION;
typedef struct {
EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;
DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo[DBG2_NUM_DEBUG_PORTS];
} DBG2_TABLE;
#define DBG2_DEBUG_PORT_DDI(NumReg, SubType, UartBase, UartAddrLen, UartNameStr) { \
{ \
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, /* UINT8 Revision */ \
sizeof (DBG2_DEBUG_DEVICE_INFORMATION), /* UINT16 Length */ \
NumReg, /* UINT8 NumberofGenericAddressRegisters */ \
DBG2_NAMESPACESTRING_FIELD_SIZE, /* UINT16 NameSpaceStringLength */ \
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), /* UINT16 NameSpaceStringOffset */ \
0, /* UINT16 OemDataLength */ \
0, /* UINT16 OemDataOffset */ \
EFI_ACPI_DBG2_PORT_TYPE_SERIAL, /* UINT16 Port Type */ \
SubType, /* UINT16 Port Subtype */ \
{EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, /* UINT8 Reserved[2] */ \
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), /* UINT16 BaseAddressRegister Offset */ \
OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) /* UINT16 AddressSize Offset */ \
}, \
ARM_GAS32 (UartBase), /* EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister */ \
UartAddrLen, /* UINT32 AddressSize */ \
UartNameStr /* UINT8 NameSpaceString[MAX_DBG2_NAME_LEN] */ \
}
STATIC DBG2_TABLE Dbg2 = {
{
ARM_ACPI_HEADER (EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE,
DBG2_TABLE,
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION),
OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),
DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */
},
{
#if 0
/*
* Kernel Debug Port
*/
DBG2_DEBUG_PORT_DDI (DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS,
EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
FixedPcdGet64 (PcdSerialDbgRegisterBase),
PL011_UART_LENGTH,
NAME_STR_UART1),
#endif
}
};
#pragma pack()
//
// Reference the table being generated to prevent the optimizer from removing
// the data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Dbg2;

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/** @file
Differentiated System Description Table Fields (DSDT)
Copyright (c) 2014-2018, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "ArmPlatform.h"
DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_OEM_REVISION) {
Scope(_SB) {
//
// A57x2-A53x4 Processor declaration
//
Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities
CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
#if 0
If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) {
If (!(Arg1 == One)) {
STS0 &= ~0x1F
STS0 |= 0x0A
} Else {
If ((CAP0 & 0x100)) {
CAP0 &= ~0x100 /* No support for OS Initiated LPI */
STS0 &= ~0x1F
STS0 |= 0x12
}
}
} Else {
STS0 &= ~0x1F
STS0 |= 0x06
}
#endif // platformwide
Return (Arg3)
}
Device (CLU0) { // Cluster0 state
Name(_HID, "ACPI0010")
Name(_UID, 1)
#if 0
Name (_LPI, Package() {
0, // Version
0, // Level Index
1, // Count
Package() { // Power Gating state for Cluster
2500, // Min residency (uS)
1150, // Wake latency (uS)
1, // Flags
1, // Arch Context Flags
100, //Residency Counter Frequency
0, // No Parent State
0x01000000, // Integer Entry method
ResourceTemplate() { // Null Residency Counter
Register (SystemMemory, 0, 0, 0, 0)
},
ResourceTemplate() { // Null Usage Counter
Register (SystemMemory, 0, 0, 0, 0)
},
"CluPwrDn"
},
})
Name(PLPI, Package() {
0, // Version
0, // Level Index
2, // Count
Package() { // WFI for CPU
1, // Min residency (uS)
1, // Wake latency (uS)
1, // Flags
0, // Arch Context Flags
100, //Residency Counter Frequency
0, // No parent state
ResourceTemplate () {
// Register Entry method
Register (FFixedHW,
0x20, // Bit Width
0x00, // Bit Offset
0xFFFFFFFF, // Address
0x03, // Access Size
)
},
ResourceTemplate() { // Null Residency Counter
Register (SystemMemory, 0, 0, 0, 0)
},
ResourceTemplate() { // Null Usage Counter
Register (SystemMemory, 0, 0, 0, 0)
},
"WFI",
},
Package() { // Power Gating state for CPU
150, // Min residency (uS)
350, // Wake latency (uS)
1, // Flags
1, // Arch Context Flags
100, //Residency Counter Frequency
1, // Parent node can be in any state
ResourceTemplate () {
// Register Entry method
Register (FFixedHW,
0x20, // Bit Width
0x00, // Bit Offset
0x00010000, // Address
0x03, // Access Size
)
},
ResourceTemplate() { // Null Residency Counter
Register (SystemMemory, 0, 0, 0, 0)
},
ResourceTemplate() { // Null Usage Counter
Register (SystemMemory, 0, 0, 0, 0)
},
"CorePwrDn"
},
})
#endif // power
Device(CPU0) { // A57-0: Cluster 0, Cpu 0
Name(_HID, "ACPI0007")
Name(_UID, 0)
#if 0
Method (_LPI, 0, NotSerialized) {
return(PLPI)
}
#endif
}
#if 0
Device(CPU1) { // A57-1: Cluster 0, Cpu 1
Name(_HID, "ACPI0007")
Name(_UID, 5)
Method (_LPI, 0, NotSerialized) {
return(PLPI)
}
}
#endif // cpu 0
}
#if 0
Device (CLU1) { // Cluster1 state
Name(_HID, "ACPI0010")
Name(_UID, 2)
Name (_LPI, Package() {
0, // Version
0, // Level Index
1, // Count
Package() { // Power Gating state for Cluster
2500, // Min residency (uS)
1150, // Wake latency (uS)
1, // Flags
1, // Arch Context Flags
100, //Residency Counter Frequency
0, // No Parent State
0x01000000, // Integer Entry method
ResourceTemplate() { // Null Residency Counter
Register (SystemMemory, 0, 0, 0, 0)
},
ResourceTemplate() { // Null Usage Counter
Register (SystemMemory, 0, 0, 0, 0)
},
"CluPwrDn"
},
})
Name(PLPI, Package() {
0, // Version
0, // Level Index
2, // Count
Package() { // WFI for CPU
1, // Min residency (uS)
1, // Wake latency (uS)
1, // Flags
0, // Arch Context Flags
100, //Residency Counter Frequency
0, // No parent state
ResourceTemplate () {
// Register Entry method
Register (FFixedHW,
0x20, // Bit Width
0x00, // Bit Offset
0xFFFFFFFF, // Address
0x03, // Access Size
)
},
ResourceTemplate() { // Null Residency Counter
Register (SystemMemory, 0, 0, 0, 0)
},
ResourceTemplate() { // Null Usage Counter
Register (SystemMemory, 0, 0, 0, 0)
},
"WFI",
},
Package() { // Power Gating state for CPU
150, // Min residency (uS)
350, // Wake latency (uS)
1, // Flags
1, // Arch Context Flags
100, //Residency Counter Frequency
1, // Parent node can be in any state
ResourceTemplate () {
// Register Entry method
Register (FFixedHW,
0x20, // Bit Width
0x00, // Bit Offset
0x00010000, // Address
0x03, // Access Size
)
},
ResourceTemplate() { // Null Residency Counter
Register (SystemMemory, 0, 0, 0, 0)
},
ResourceTemplate() { // Null Usage Counter
Register (SystemMemory, 0, 0, 0, 0)
},
"CorePwrDn"
},
})
Device(CPU2) { // A53-0: Cluster 1, Cpu 0
Name(_HID, "ACPI0007")
Name(_UID, 0)
Method (_LPI, 0, NotSerialized) {
return(PLPI)
}
}
Device(CPU3) { // A53-1: Cluster 1, Cpu 1
Name(_HID, "ACPI0007")
Name(_UID, 1)
Method (_LPI, 0, NotSerialized) {
return(PLPI)
}
}
Device(CPU4) { // A53-2: Cluster 1, Cpu 2
Name(_HID, "ACPI0007")
Name(_UID, 2)
Method (_LPI, 0, NotSerialized) {
return(PLPI)
}
}
Device(CPU5) { // A53-3: Cluster 1, Cpu 3
Name(_HID, "ACPI0007")
Name(_UID, 3)
Method (_LPI, 0, NotSerialized) {
return(PLPI)
}
}
}
#endif // cluster 1
#if 0
//
// Keyboard and Mouse
//
Device(KMI0) {
Name(_HID, "ARMH0501")
Name(_CID, "PL050_KBD")
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x1C060008, 0x4)
Memory32Fixed(ReadWrite, 0x1C060000, 0x4)
Memory32Fixed(ReadOnly, 0x1C060004, 0x4)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 }
})
}
//
// LAN9118 Ethernet
//
Device(ETH0) {
Name(_HID, "ARMH9118")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x18000000, 0x1000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 192 }
})
Name(_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package() {
Package(2) {"phy-mode", "mii"},
Package(2) {"reg-io-width", 4 },
Package(2) {"smsc,irq-active-high",1},
Package(2) {"smsc,irq-push-pull",1}
}
}) // _DSD()
}
// UART PL011
Device(COM0) {
Name(_HID, "ARMH0011")
Name(_CID, "PL011")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x7FF80000, 0x1000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 }
})
}
//
// USB EHCI Host Controller
//
Device(USB0){
Name(_HID, "ARMH0D20")
Name(_CID, "PNP0D20")
Name(_UID, 2)
Name(_CCA, 0) //EHCI on this platform is not coherent!
Method(_CRS, 0x0, Serialized){
Name(RBUF, ResourceTemplate(){
Memory32Fixed(ReadWrite, 0x7FFC0000, 0x10000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {149} // INT ID=149 GIC IRQ ID=117 for Juno SoC USB EHCI Controller
})
Return(RBUF)
}
//
// Root Hub
//
Device(RHUB){
Name(_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec
//
// Ports connected to Root Hub
//
Device(HUB1){
Name(_ADR, 0x00000001)
Name(_UPC, Package(){
0x00, // Port is NOT connectable
0xFF, // Don't care
0x00000000, // Reserved 0 must be zero
0x00000000 // Reserved 1 must be zero
})
Device(PRT1){
Name(_ADR, 0x00000001)
Name(_UPC, Package(){
0xFF, // Port is connectable
0x00, // Port connector is A
0x00000000,
0x00000000
})
Name(_PLD, Package(){
Buffer(0x10){
0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
})
} // USB0_RHUB_HUB1_PRT1
Device(PRT2){
Name(_ADR, 0x00000002)
Name(_UPC, Package(){
0xFF, // Port is connectable
0x00, // Port connector is A
0x00000000,
0x00000000
})
Name(_PLD, Package(){
Buffer(0x10){
0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
})
} // USB0_RHUB_HUB1_PRT2
Device(PRT3){
Name(_ADR, 0x00000003)
Name(_UPC, Package(){
0xFF, // Port is connectable
0x00, // Port connector is A
0x00000000,
0x00000000
})
Name(_PLD, Package(){
Buffer(0x10){
0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
})
} // USB0_RHUB_HUB1_PRT3
Device(PRT4){
Name(_ADR, 0x00000004)
Name(_UPC, Package(){
0xFF, // Port is connectable
0x00, // Port connector is A
0x00000000,
0x00000000
})
Name(_PLD, Package(){
Buffer(0x10){
0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
})
} // USB0_RHUB_HUB1_PRT4
} // USB0_RHUB_HUB1
} // USB0_RHUB
} // USB0
#endif
} // Scope(_SB)
}

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/** @file
* Fixed ACPI Description Table (FADT)
*
* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmPlatform.h"
#include <Library/AcpiLib.h>
#include <IndustryStandard/Acpi.h>
#ifdef ARM_JUNO_ACPI_5_0
EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
ARM_ACPI_HEADER (
EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE,
EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
),
#else
EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
ARM_ACPI_HEADER (
EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
),
#endif
0, // UINT32 FirmwareCtrl
0, // UINT32 Dsdt
EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
0, // UINT16 SciInt
0, // UINT32 SmiCmd
0, // UINT8 AcpiEnable
0, // UINT8 AcpiDisable
0, // UINT8 S4BiosReq
0, // UINT8 PstateCnt
0, // UINT32 Pm1aEvtBlk
0, // UINT32 Pm1bEvtBlk
0, // UINT32 Pm1aCntBlk
0, // UINT32 Pm1bCntBlk
0, // UINT32 Pm2CntBlk
0, // UINT32 PmTmrBlk
0, // UINT32 Gpe0Blk
0, // UINT32 Gpe1Blk
0, // UINT8 Pm1EvtLen
0, // UINT8 Pm1CntLen
0, // UINT8 Pm2CntLen
0, // UINT8 PmTmrLen
0, // UINT8 Gpe0BlkLen
0, // UINT8 Gpe1BlkLen
0, // UINT8 Gpe1Base
0, // UINT8 CstCnt
0, // UINT16 PLvl2Lat
0, // UINT16 PLvl3Lat
0, // UINT16 FlushSize
0, // UINT16 FlushStride
0, // UINT8 DutyOffset
0, // UINT8 DutyWidth
0, // UINT8 DayAlrm
0, // UINT8 MonAlrm
0, // UINT8 Century
0, // UINT16 IaPcBootArch
0, // UINT8 Reserved1
EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
0, // UINT8 ResetValue
#ifdef ARM_JUNO_ACPI_5_0
{EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE,EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved2[3]
#else
EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
#endif
0, // UINT64 XFirmwareCtrl
0, // UINT64 XDsdt
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
};
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Fadt;

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/** @file
* Generic Timer Description Table (GTDT)
*
* Copyright (c) 2012 - 2017, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmPlatform.h"
#include <Library/AcpiLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>
#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
#define GTDT_GLOBAL_FLAGS_LEVEL 0
// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
#ifdef SYSTEM_TIMER_BASE_ADDRESS
#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
#else
#define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
#endif
#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
#define GTDT_TIMER_LEVEL_TRIGGERED 0
#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
#define GTDT_TIMER_ACTIVE_HIGH 0
#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
#define JUNO_WATCHDOG_COUNT FixedPcdGet32 (PcdWatchdogCount)
#ifdef ARM_JUNO_ACPI_5_0
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
ARM_ACPI_HEADER(
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE,
EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
),
SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
GTDT_GLOBAL_FLAGS, // UINT32 GlobalFlags
FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
GTDT_GTIMER_FLAGS // UINT32 NonSecurePL2TimerFlags
};
#else
#pragma pack (1)
typedef struct {
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
#if (JUNO_WATCHDOG_COUNT != 0)
EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[JUNO_WATCHDOG_COUNT];
#endif
} GENERIC_TIMER_DESCRIPTION_TABLE;
#pragma pack ()
GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
{
ARM_ACPI_HEADER(
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
GENERIC_TIMER_DESCRIPTION_TABLE,
EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
),
SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
0, // UINT32 Reserved
FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
JUNO_WATCHDOG_COUNT, // UINT32 PlatformTimerCount
#if (JUNO_WATCHDOG_COUNT != 0)
sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
#else
0
#endif
},
#if (JUNO_WATCHDOG_COUNT != 0)
{
EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
FixedPcdGet64 (PcdGenericWatchdogRefreshBase),
FixedPcdGet64 (PcdGenericWatchdogControlBase),
93,
0),
EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
FixedPcdGet64 (PcdGenericWatchdogRefreshBase),
FixedPcdGet64 (PcdGenericWatchdogControlBase),
94,
EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
}
#endif
};
#endif
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Gtdt;

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/** @file
* Multiple APIC Description Table (MADT)
*
* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmPlatform.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>
//
// Multiple APIC Description Table
//
#ifdef ARM_JUNO_ACPI_5_0
#pragma pack (1)
typedef struct {
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
EFI_ACPI_5_0_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
//
// MADT specific fields
//
0, // LocalApicAddress
0, // Flags
},
{
// Format: EFI_ACPI_5_0_GIC_STRUCTURE_INIT(GicId, AcpiCpuId, Flags, PmuIrq, GicBase)
// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GIC Structure of
// ACPI v5.0).
// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
// For now we leave CPU2 (A53-0) at the first position.
// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
EFI_ACPI_5_0_GIC_STRUCTURE_INIT(2, 0, EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-0
EFI_ACPI_5_0_GIC_STRUCTURE_INIT(3, 1, EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-1
EFI_ACPI_5_0_GIC_STRUCTURE_INIT(4, 2, EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-2
EFI_ACPI_5_0_GIC_STRUCTURE_INIT(5, 3, EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A53-3
EFI_ACPI_5_0_GIC_STRUCTURE_INIT(0, 4, EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase)), // A57-0
EFI_ACPI_5_0_GIC_STRUCTURE_INIT(1, 5, EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase)) // A57-1
},
EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0)
};
#else
#pragma pack (1)
typedef struct {
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[FixedPcdGet32 (PcdCoreCount)];
EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
#if 0
EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE MsiFrame;
#endif
EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
} MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
MULTIPLE_APIC_DESCRIPTION_TABLE,
EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
//
// MADT specific fields
//
0, // LocalApicAddress
0, // Flags
},
{
// Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, MpIdr, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
// GsivId, GicRBase)
// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
// ACPI v5.1).
// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
// Trusted Firmware. When supported, we will need to code to dynamically change the ordering.
// For now we leave CPU2 (A53-0) at the first position.
// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
0, 0, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0 /* GicVBase */, 0 /*GicHBase */, 25, 0 /* GicRBase */),
#if 0
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-2
4, 2, GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 58, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-3
5, 3, GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 62, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-0
0, 4, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 34, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1
1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
#endif
},
// Format: EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion)
EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)
#if 0
EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)
#endif
/* GIC Redistributor */
{
EFI_ACPI_6_1_GICR, // UINT8 Type
sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length
EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
0x00100000, // UINT32 DiscoveryRangeLength
}
};
#endif
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Madt;

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/** @file
* SPCR Table
*
* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
*
* This program and the accompanying materials are licensed and made available
* under the terms and conditions of the BSD License which accompanies this
* distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include "ArmPlatform.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
/**
* References:
* Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
**/
///
/// SPCR Flow Control
///
#define SPCR_FLOW_CONTROL_NONE 0
STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
// UINT8 InterfaceType;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
// UINT8 Reserved1[3];
{
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE
},
// EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
// UINT8 InterruptType;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
// UINT8 Irq;
0, // Not used on ARM
// UINT32 GlobalSystemInterrupt;
FixedPcdGet32 (PL011UartInterrupt),
// UINT8 BaudRate;
#if (FixedPcdGet64 (PcdUartDefaultBaudRate) == 9600)
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600,
#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 19200)
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200,
#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 57600)
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600,
#elif (FixedPcdGet64 (PcdUartDefaultBaudRate) == 115200)
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
#else
#error Unsupported SPCR Baud Rate
#endif
// UINT8 Parity;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
// UINT8 StopBits;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
// UINT8 FlowControl;
SPCR_FLOW_CONTROL_NONE,
// UINT8 TerminalType;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
// UINT8 Reserved2;
EFI_ACPI_RESERVED_BYTE,
// UINT16 PciDeviceId;
0xFFFF,
// UINT16 PciVendorId;
0xFFFF,
// UINT8 PciBusNumber;
0x00,
// UINT8 PciDeviceNumber;
0x00,
// UINT8 PciFunctionNumber;
0x00,
// UINT32 PciFlags;
0x00000000,
// UINT8 PciSegment;
0x00,
// UINT32 Reserved3;
EFI_ACPI_RESERVED_DWORD
};
//
// Reference the table being generated to prevent the optimizer from removing the
// data structure from the executable
//
VOID* CONST ReferenceAcpiTable = &Spcr;

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