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Add initial support for building DSDT from source

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Signed-off-by: Sophon <strongtz@yeah.net>
This commit is contained in:
Sophon 2021-07-26 14:31:28 +08:00
parent d96ecfaece
commit a8f8d38047
92 changed files with 38847 additions and 0 deletions
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1
DSDT/.gitignore vendored Normal file
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*.aml

156
DSDT/common/HoyaSmmu.asl Normal file
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//
// SMMU Driver
//
// SMT vector diagram: \\brewmp4\public\Istari\
//
// Need to change Device Name in resorce file
// Currently Marking CP-P, CP-NP as CP_Pixel only need to add these VM
// to SMMU driver and need to update
Device (MMU0)
{
// ATCU
Name (_HID, "QCOM0212")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Name (_DEP, Package ()
{
\_SB_.MMU1
})
Method (_CRS, 0x0, NotSerialized)
{
Return (ResourceTemplate ()
{
// a-TCU register address space
Memory32Fixed (ReadWrite, 0x15000000, 0x7FFB8)
// TLBI HW SPINLOCK BASE ADDRESS
Memory32Fixed (ReadWrite, 0x1F46000, 0x4)
// a-TCU: there is one interrupt for each CB handled by HLOS clients (only non-secure CBs)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {128} // CB 0
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {129} // CB 1
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {130} // CB 2
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {131} // CB 3
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {132} // CB 4
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {133} // CB 5
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {134} // CB 6
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {135} // CB 7
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {136} // CB 8
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {137} // CB 9
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {138} // CB 10
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {139} // CB 11
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {140} // CB 12
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {141} // CB 13
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {142} // CB 14
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {143} // CB 15
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {144} // CB 16
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {145} // CB 17
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {146} // CB 18
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {147} // CB 19
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {148} // CB 20
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {149} // CB 21
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {150} // CB 22
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {213} // CB 23
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {214} // CB 24
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {215} // CB 25
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {216} // CB 26
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {217} // CB 27
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {218} // CB 28
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {219} // CB 29
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {220} // CB 30
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {221} // CB 31
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {222} // CB 32
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {223} // CB 33
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {224} // CB 34
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {347} // CB 35
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {348} // CB 36
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {349} // CB 37
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {350} // CB 38
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {351} // CB 39
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {352} // CB 40
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {353} // CB 41
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {354} // CB 42
// Not used for mapping
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {355} // CB 43
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {356} // CB 44
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {357} // CB 45
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {358} // CB 46
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {359} // CB 47
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {360} // CB 48
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {361} // CB 49
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {362} // CB 50
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {363} // CB 51
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {364} // CB 52
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {365} // CB 53
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {366} // CB 54
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {367} // CB 55
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {368} // CB 56
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {369} // CB 57
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {370} // CB 58
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {371} // CB 59
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {372} // CB 60
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {373} // CB 61
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {374} // CB 62
// Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {375} // CB 63
})
}
}
Device (MMU1)
{
// This is the SMMU for Oxili/GFX
Name (_HID, "QCOM0212")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
Name (_DEP, Package()
{
\_SB_.PEP0
})
// When testing on 8960, delete the _CRS method. This will cause
// the driver to use a chunk of RAM.
Method (_CRS, 0x0, NotSerialized)
{
Return (ResourceTemplate ()
{
//g-TCU register address space
Memory32Fixed (ReadWrite, 0x05040000, 0x10000)
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {396} // CB 0
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {397} // CB 1
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {398} // CB 2
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {399} // CB 3
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {400} // CB 4
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {401} // CB 5
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {402} // CB 6
Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {403} // CB 7
})
}
}
Device (IMM0)
{
// ATCU
Name (_HID, "QCOM030B")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
}
Device (IMM1)
{
// This is the SMMU for Oxili/GFX
Name (_HID, "QCOM030B")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
}

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DSDT/common/HoyaSmmu_resources.asl Normal file
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//===========================================================================
// <HoyaSmmu_resources.asl>
// DESCRIPTION
// This file contans the resources needed by SMMU driver.
//
//===========================================================================
Scope(\_SB.PEP0){
// SMMU
Method(SMMD){
Return(SMMC)
}
Name(SMMC,
Package(){
// SMMU MNOC Resources
Package(){
"DEVICE",
"\\_SB.MMU0",
//--------------------------------------------------------------------------------------
// Component 0 -
//--------------------------------------------------------------------------------------
//
Package(){
"COMPONENT",
0,
Package(){
"FSTATE",
0,
// Action: 1 == ENABLE
//
// Domain Name Action
// ---------------- ------
// Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_mmu_tcu_gds", 1, },},
// Action: 1 == ENABLE
// MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST
//
// Clock Name Action
// -------------------- ------
Package() { "CLOCK", Package() { "gcc_hlos1_vote_mmu_tcu_clk", 1 }}
},
Package(){
"FSTATE",
1,
// Action: 2 == DISABLE
// MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST
//
// Clock Name Action
// -------------------- ------
Package() { "CLOCK", Package() { "gcc_hlos1_vote_mmu_tcu_clk", 2 }},
// Action: 2 == DISABLE
//
// Domain Name Action
// ---------------- ------
// Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_mmu_tcu_gds", 2, },},
},
},
},
// A5x/GFX SMMU Resources
Package(){
"DEVICE",
"\\_SB.MMU1",
//--------------------------------------------------------------------------------------
// Component 0 -
//--------------------------------------------------------------------------------------
//
Package(){
"COMPONENT",
0,
Package(){
"FSTATE",
0,
// Vote for the frequencies we need otherwise these clocks may not be configured properly
// Action: 1 == ENABLE
//
// Domain Name Action
// ---------------- ------
Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_gpu_smmu_gds", 1 }},
// Action: 1 == ENABLE
// MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST
//
// Clock Name Action
// -------------------- ------
Package() { "CLOCK", Package() { "gcc_hlos1_vote_gpu_smmu_clk", 1 }},
},
Package(){
"FSTATE",
1,
// Action: 2 == DISABLE
// MatchType: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST
//
// Clock Name Action
// -------------------- ------
Package() { "CLOCK", Package() { "gcc_hlos1_vote_gpu_smmu_clk", 2 }},
// Action: 2 == DISABLE
//
// Domain Name Action
// ---------------- ------
Package() { "FOOTSWITCH", Package() { "gcc_hlos1_vote_gpu_smmu_gds", 2 }},
},
},
},
})
}

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DSDT/common/Pep_lpi.asl Normal file
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Device (SYSM) {
Name (_HID, "ACPI0010")
Name (_UID, 0x100000)
Name (_LPI, Package() {
0, // Version
0x1000000, // Level ID
2, // Count
// State F1 - Cx retention + AOSS Sleep
Package () {
9500, // Min residency (us)
6000, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP.
0, // Residency counter frequency
0, // Enabled parent state
0x3300, // Integer entry method E2+F1
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"platform.F1" // Name
},
// State F2 - Cx collapse + AOSS Sleep + LLC deactivate
Package () {
10000, // Min residency (us)
6600, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP.
0, // Residency counter frequency
0, // Enabled parent state
0xC300, // Integer entry method E2+F2
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"platform.F2" // Name
}
}) // End of _LPI
Device (CLUS) {
Name (_HID, "ACPI0010")
Name (_UID, 0x10)
Name (_LPI, Package() {
0, // Version
0x1000000,
2, // Count
// State 0: D2
Package () {
5900, // Min residency (us)
3000, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
0x20, // Integer entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"L3Cluster.D2" // Name
},
// State 1: D4
Package () {
6000, // Min residency (us)
3300, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Till F2)
0x40, // Integer entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"L3Cluster.D4" // Name
},
}) // End of _LPI
Device (CPU0) // Kyro Silver CPU0 < SYSM.APSS.CPU0
{
Name (_HID, "ACPI0007")
Name (_UID, 0x0)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver0.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver0.C2" // Name
},
// C3
Package () {
5000, // Min residency (us)
500, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4) 0x40000003
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver0.C3" // Name
},
// C4
Package () {
5100, // Min residency (us)
550, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables D4) 0x40000003
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver0.C4" // Name
},
}) // End of _LPI
} // End of CPU0
Device (CPU1) // Kyro Silver CPU1
{
Name (_HID, "ACPI0007")
Name (_UID, 0x1)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver1.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver1.C2" // Name
},
// C3
Package () {
5000, // Min residency (us)
500, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver1.C3" // Name
},
// C4
Package () {
5100, // Min residency (us)
550, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables LLC)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver1.C4" // Name
},
}) // End of _LPI
} // End of CPU1
Device (CPU2) // Kyro Silver CPU2
{
Name (_HID, "ACPI0007")
Name (_UID, 0x2)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver2.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver2.C2" // Name
},
// C3
Package () {
5000, // Min residency (us)
500, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver2.C3" // Name
},
// C4
Package () {
5100, // Min residency (us)
550, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables LLC)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver2.C4" // Name
},
}) // End of _LPI
} // End of CPU2
Device (CPU3) // Kyro Silver CPU3
{
Name (_HID, "ACPI0007")
Name (_UID, 0x3)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver3.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver3.C2" // Name
},
// C3
Package () {
5000, // Min residency (us)
500, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver3.C3" // Name
},
// C4
Package () {
5100, // Min residency (us)
550, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables LLC)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoSilver3.C4" // Name
},
}) // End of _LPI
} // End of CPU3
Device (CPU4) // Kyro Gold CPU0
{
Name (_HID, "ACPI0007")
Name (_UID, 0x4)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold0.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold0.C2" // Name
},
// C3
Package () {
1000, // Min residency (us)
650, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold0.C3" // Name
},
// C4
Package () {
1500, // Min residency (us)
1100, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables LLC)
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold0.C4" // Name
},
}) // End of _LPI
} // End of CPU4
Device (CPU5) // Kyro Gold CPU1
{
Name (_HID, "ACPI0007")
Name (_UID, 0x5)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold1.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold1.C2" // Name
},
// C3
Package () {
1000, // Min residency (us)
650, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4) 0x40000003
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold1.C3" // Name
},
// C4
Package () {
1500, // Min residency (us)
1100, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables D4) 0x40000003
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold1.C4" // Name
},
}) // End of _LPI
} // End of CPU5
Device (CPU6) // Kyro Gold CPU2
{
Name (_HID, "ACPI0007")
Name (_UID, 0x6)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold2.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold2.C2" // Name
},
// C3
Package () {
1000, // Min residency (us)
650, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4) 0x40000003
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold2.C3" // Name
},
// C4
Package () {
1500, // Min residency (us)
1100, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables D4) 0x40000004
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold2.C4" // Name
},
}) // End of _LPI
} // End of CPU6
Device (CPU7) // Kyro Gold CPU3
{
Name (_HID, "ACPI0007")
Name (_UID, 0x7)
Method(_STA){ Return (0xF) }
Name (_LPI, Package() {
0, // Version
0, // Level ID
4, // Count
// Core Clock Gate - C1
Package () {
0, // Min residency (us)
0, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
0, // Enabled parent state
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold3.C1" // Name
},
// C2
Package () {
400, // Min residency (us)
100, // Wake latency (us)
0, // Flags, set bit0 to 1 to enable this state
0, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state
// Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName)
ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold3.C2" // Name
},
// C3
Package () {
1000, // Min residency (us)
650, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
1, // Enabled parent state (Enables D4) 0x40000003
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold3.C3" // Name
},
// C4
Package () {
1500, // Min residency (us)
1100, // Wake latency (us)
1, // Flags, set bit0 to 1 to enable this state
1, // Arch context last flags
0, // Residency counter frequency
2, // Enabled parent state (Enables D4) 0x40000004
ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse.
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register
ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register
"KryoGold3.C4" // Name
},
}) // End of _LPI
} // End of CPU7
} // End of CLUS
} // End of SYSM

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//===========================================================================
// <qdss.asl>
// DESCRIPTION
// This file contans the resources needed by qdss driver.
//
//
//===========================================================================
// You won't have qdss on your phone xD

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//
// Secure Channel Manager (SCM) Driver
//
Device (SCM0)
{
Name (_HID, "QCOM0214")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
}
//
// TrEE Driver
//
// Device (TREE)
// {
// Name (_HID, "QCOM02BB")
// Alias(\_SB.PSUB, _SUB)
// Name (_UID, 0)
// Method (IMPT)
// {
// Name(TPPK, Package()
// {
// Package ()
// {
// // Holds whether TPM is seperate app or not
// 0x00000000, // Will be filled by TPMA
// // Holds TPM type
// 0x00000000, // Will be filled by TDTV
// // Holds TrEE Carveout address
// 0x00000000, // Will be filled by TCMA
// // Holds TrEE Carveout length
// 0x00000000 // Will be filled by TCML
// }
// })
// // Copy ACPI globals for Address for this subsystem into above package for use in driver
// Store (TPMA, Index(DeRefOf(Index (TPPK, 0)), 0))
// Store (TDTV, Index(DeRefOf(Index (TPPK, 0)), 1))
// Store (TCMA, Index(DeRefOf(Index (TPPK, 0)), 2))
// Store (TCML, Index(DeRefOf(Index (TPPK, 0)), 3))
// Return (TPPK)
// }
// }
// HACK!
Device (TREE)
{
Name (_HID, "QCOM02BB") // _HID: Hardware ID
Alias (\_SB.PSUB, _SUB)
Name (_UID, Zero) // _UID: Unique ID
Method (MCGT, 0, NotSerialized)
{
Name (TPKG, Package (One)
{
Package (0x02)
{
Zero,
Zero
}
})
DerefOf (TPKG [Zero]) [Zero] = TCMA /* \_SB_.TCMA */
DerefOf (TPKG [Zero]) [One] = TCML /* \_SB_.TCML */
Return (TPKG) /* \_SB_.TREE.MCGT.TPKG */
}
}

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//
// This file contains ASL Bridge Device definitions
//
//
// ASL Bridge Device
//
Device (ABD)
{
Name (_DEP, Package(0x1)
{
\_SB_.PEP0
})
Name (_HID, "QCOM0242")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
OperationRegion(ROP1, GenericSerialBus, 0x00000000, 0x100)
Name(AVBL, Zero)
Method(_REG, 0x2, NotSerialized)
{
If(Lequal(Arg0, 0x9))
{
Store(Arg1, AVBL)
}
}
}

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Name (PSUB, "RENEGA0E")

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//
// ADSP RPC Driver
//
Device (ARPC)
{
Name (_DEP, Package(0x3)
{
\_SB_.MMU0,
\_SB_.GLNK,
\_SB_.SCM0
})
Name (_HID, "QCOM0297")
Alias(\_SB.PSUB, _SUB)
}
// ARPD AUDIO Daemon Driver
Device (ARPD)
{
Name (_DEP, Package(0x2)
{
\_SB_.ADSP,
\_SB_.ARPC
})
Name (_HID, "QCOM02F3")
Alias(\_SB.PSUB, _SUB)
}

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// This file contains the Bus Access Modules (BAM)
// ACPI device definitions and pipe configurations
//
//
// Device Map:
// 0x2401 - BAM
//
// List of Devices
// BAM1 - CRYPTO1
// BAM5 - SLIMBUS1
// BAM6 - SLIMBUS
// BAM7 - TSIF
// BAMD - USB3.0 secondary
// BAME - QDSS
// BAMF - USB3.0 primary
Device (BAM1)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// CRYPTO0 register address space
Memory32Fixed (ReadWrite, 0x1DC4000, 0x00024000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {304}
})
Return (RBUF)
}
}
Device (BAM5)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 5)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// AUD_SLIMBUS register address space
Memory32Fixed (ReadWrite, 0x17184000, 0x00032000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {196}
})
Return (RBUF)
}
}
Device (BAM6)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 6)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// QCA_SLIMBUS register address space
Memory32Fixed (ReadWrite, 0x17204000, 0x00026000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {324}
})
Return (RBUF)
}
}
Device (BAM7)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 7)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// TSIF register address space
Memory32Fixed (ReadWrite, 0x08884000, 0x00023000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {154}
})
Return (RBUF)
}
}
Device (BAMD)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 13)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// USB30 sec register address space
Memory32Fixed (ReadWrite, 0xA904000, 0x00017000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {169}
})
Return (RBUF)
}
}
Device (BAME)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 14)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// QDSS register address space
Memory32Fixed (ReadWrite, 0x6064000, 0x00015000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {199}
})
Return (RBUF)
}
}
Device (BAMF)
{
Name (_HID, "QCOM0213")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 15)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// USB30 PRI register address space
Memory32Fixed (ReadWrite, 0x0A704000, 0x00017000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {164}
})
Return (RBUF)
}
}

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//
// Core-BSP MPROC Drivers (IPC Router & GLINK)
//
//
// IPC Router
//
Device (IPC0)
{
Name (_DEP, Package(0x1)
{
\_SB_.GLNK
})
Name (_HID, "QCOM021C")
Alias(\_SB.PSUB, _SUB)
}
//
// GLINK
//
// Order of incoming and outgoing interrupts depend on the number of interrupts mentioned in INTR method
Device (GLNK)
{
Name (_DEP, Package(0x1)
{
\_SB_.RPEN
})
Name (_HID, "QCOM02F9")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// Inbound SMP2P interrupt from Modem (SYS_apssQgicSPI(451)):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {483}
// Inbound SMP2P interrupt from ADSP (SYS_apssQgicSPI[158]):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {190}
// Inbound SMP2P interrupt from SSC (SYS_apssQgicSPI(172)):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {204}
// Inbound SMP2P interrupt from CDSP (SYS_apssQgicSPI(576)):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {608}
// Inbound SMEM XPORT interrupt from Modem (SYS_apssQgicSPI(449)):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {481}
// Inbound SMEM XPORT interrupt from ADSP (SYS_apssQgicSPI[156]):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {188}
// Inbound SMEM XPORT interrupt from SSC (SYS_apssQgicSPI(170)):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {202}
// Inbound SMEM XPORT interrupt from CDSP (SYS_apssQgicSPI(574)):
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {606}
})
Return (RBUF)
}
}

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//
// RevRmNet Driver
//
Device (RVRM)
{
Name (_HID, "QCOM02A5")
Method (_STA)
{
Return (0xB)
}
}
//
// Databus Driver
//
Device (DBUS)
{
Name (_HID, "QCOM02F0")
Alias(\_SB.PSUB, _SUB)
Method (CHLD)
{
Return (Package()
{
// This package has following params
// 1. HWID of the child
// 2. Databus Device Type (0 - Link Local)
// 3. Max instances supported for the child
// 4. Number of child devices that should be Statically Enumerated.
Package() {"DBUS\\QCOM02AA", 0, 9, 1}
})
}
Method (_STA)
{
Return (0xB)
}
}
//
// linklocal
//
// Device (LNK0)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 0)
//}
// Device (LNK1)
//{
// Name (_HID, "QCOM02AA")
// Name (_UID, 1)
// }
// Device (LNK2)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 2)
// }
// Device (LNK3)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 3)
// }
// Device (LNK4)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 4)
// }
// Device (LNK5)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 5)
// }
// Device (LNK6)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 6)
// }
// Device (LNK7)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 7)
// }
// Device (LNK8)
// {
// Name (_HID, "QCOM02AA")
// Name (_UID, 8)
// }
//
// Modembridge Driver
//
Device (MBRG)
{
Name (_HID, "QCOM020D")
}
//
// Remote AT Command Processor Driver
//
Device (RMAT)
{
Name (_HID, "QCOM0210")
}
//
// rmnetbridge
//
Device (RMNT)
{
Name (_HID, "QCOM020E")
}
//
// dplbridge
//
Device (DPLB)
{
Name (_HID, "QCOM02C2")
}

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// This file contains the GPS ACPI device definitions.
//
//
// Qualcomm GPS driver
//
Device (GPS)
{
Name (_DEP, Package(0x1)
{
\_SB_.GLNK
})
Name (_HID, "QCOM02B6")
Alias(\_SB.PSUB, _SUB)
Name (_CID, "ACPI\QCOM24B4")
Name (_UID, 0)
}

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// This file contains the Generic Software Interface(GSI)
// ACPI device definitions.
// GSI is the interface used by IPA driver to talk to IPA HW and is intended
// as a replacement for BAM.
//
//
// Device Map:
// GSI
//
// List of Devices
Device (GSI)
{
// Indicates dependency on PEP
Name (_DEP, Package () { \_SB_.PEP0 })
Name(_HID, "QCOM02E7")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// GSI_PHYSICAL_ADDRESS, GSI_MEM_SIZE
Memory32Fixed (ReadWrite, 0x1E00000, 0x30000)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {464}
})
Return (RBUF)
}
}

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//
// Device Map:
// IPA
//
// List of Devices
Device (IPA)
{
// Indicates dependency on PEP, RPE, SMEM, PIL, SMMU, GSI and GLINK
Name (_DEP, Package(0x6)
{
\_SB_.PEP0,
\_SB_.RPEN,
\_SB_.PILC,
\_SB_.MMU0,
\_SB_.GSI,
\_SB_.GLNK,
})
Name(_HID, "QCOM02B3")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Method (_CRS, 0x0, NotSerialized)
{
Return
(
ResourceTemplate ()
{
// IPA_PHYSICAL_ADDRESS, IPA_MEM_SIZE
Memory32Fixed (ReadWrite, 0x1E40000, 0x1FFFF)
// IPA Interrupt for uC communication
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {343}
}
)
}
}

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//===========================================================================
// <ipa_resources.asl>
// DESCRIPTION
// This file contans the resources needed by ipa driver.
//
//===========================================================================
//===========================================================================
// Implementation of function states for IPA driver.
// Present implementation has two function states F0 and F1.
//
// F0 = Full power mode.
// F1 = Low power mode.
//
// Resource being managed is /clk/ipa
//===========================================================================
Scope(\_SB.PEP0)
{
Method(IPMD){
Return(IPSC)
}
Name(IPSC,
Package()
{
Package()
{
"DEVICE",
"\\_SB.IPA",
Package()
{
"COMPONENT",
0x0,
Package()
{
"FSTATE",
0x0,
package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_IPA_CORE", // Master
"ICBID_SLAVE_IPA_CORE", // Slave
37400, // IB= KHz ( map 37500 KHz needs to mapped to IB value )
0, // AB
"HLOS_DRV", // Optional: DRV Id
},
},
},
Package()
{
"FSTATE",
0x1,
package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_IPA_CORE", // Master
"ICBID_SLAVE_IPA_CORE", // Slave
0, // IB
0, // AB
"HLOS_DRV", // Optional: DRV Id
},
},
},
},
},
})
}

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//===========================================================================
// <oem_resources.asl>
// DESCRIPTION
// This file contans the resources needed by oem drivers.
//
//===========================================================================
Scope(\_SB_.PEP0)
{
// OEM
Method(OPMD)
{
Return(OPCC)
}
Name(OPCC,
Package ()
{
})
}

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//PCIE asl
// Unused Memory range
OperationRegion(CP00, SystemMemory, 0x13000000, 0x24)
Field(CP00, DWordAcc, NoLock, Preserve){
MVIO, 32, //0x00 Address to cause Memory violation
MV01, 32, //0x04 Address to cause Memory violation
MV02, 32, //0x08 Address to cause Memory violation
MV03, 32, //0x0C Address to cause Memory violation
MV04, 32, //0x10 Address to cause Memory violation
MV11, 32, //0x14 Address to cause Memory violation
MV12, 32, //0x18 Address to cause Memory violation
MV13, 32, //0x1C Address to cause Memory violation
MV14, 32, //0x20 Address to cause Memory violation
}
// PCIE_0_PCIE20_PARF
OperationRegion(CP01, SystemMemory, 0x01C00000, 0x1004)
Field(CP01, DWordAcc, NoLock, Preserve){
PSC0, 32, //0x00 PCIE_0_PCIE20_PARF_SYS_CTRL
Offset(0x20),
PPC0, 32, //0x20 PCIE_0_PCIE20_PARF_PM_CTRL
PPS0, 32, //0x24 PCIE_0_PCIE20_PARF_PM_STTS
Offset(0x1b0),
PLT0, 32, //0x1b0 PCIE_0_PCIE20_PARF_LTSSM
Offset(0x358),
PSL0, 32, //0x358 PCIE20_PARF_SLV_ADDR_SPACE_SIZE
Offset(0x360),
WBL0, 32, //0x360 PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE
WBH0, 32, //0x364 PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE_HI
WLL0, 32, //0x368 PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT
WLH0, 32, //0x36C PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT_HI
RBL0, 32, //0x370 PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE
RBH0, 32, //0x374 PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE_HI
RLL0, 32, //0x378 PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT
RLH0, 32, //0x37C PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT_HI
PPEB, 32, //0x380 PCIE_0_PCIE20_PARF_ECAM_BASE
Offset(0x398),
WBL1, 32, //0x398 PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE_2
WBH1, 32, //0x39C PCIE20_PARF_BLOCK_SLV_AXI_WR_BASE_2_HI
WLL1, 32, //0x3A0 PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT_2
WLH1, 32, //0x3A4 PCIE20_PARF_BLOCK_SLV_AXI_WR_LIMIT_2_HI
RBL1, 32, //0x3A8 PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE_2
RBH1, 32, //0x3AC PCIE20_PARF_BLOCK_SLV_AXI_RD_BASE_2_HI
RLL1, 32, //0x3B0 PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT_2
RLH1, 32, //0x3B4 PCIE20_PARF_BLOCK_SLV_AXI_RD_LIMIT_2_HI
Offset(0x1000),
PDT0, 32, //0x1000 PCIE_0_PCIE20_PARF_DEVICE_TYPE
}
// PCIE_0_QSERDES_COM_QSERDES_COM_PCIE_USB3_QMP_PLL
OperationRegion(CP02, SystemMemory, 0x01C06000, 0x188)
Field(CP02, DWordAcc, NoLock, Preserve){
Offset (0x00C),
QCB1, 32, //0x00C QSERDES_COM_BG_TIMER
QSEC, 32, //0x010 QSERDES_COM_SSC_EN_CENTER
QAP1, 32, //0x014 QSERDES_COM_SSC_ADJ_PER1
QAP2, 32, //0x018 QSERDES_COM_SSC_ADJ_PER2
QSP1, 32, //0x01C QSERDES_COM_SSC_PER1
QSP2, 32, //0x020 QSERDES_COM_SSC_PER2
QSS1, 32, //0x024 QSERDES_COM_SSC_STEP_SIZE1
QSS2, 32, //0x028 QSERDES_COM_SSC_STEP_SIZE2
Offset (0x034),
QECE, 32, //0x034 QSERDES_COM_BIAS_EN_CLKBUFLR_EN
QCE1, 32, //0x038 QSERDES_COM_CLK_ENABLE1
QSCC, 32, //0x03C QSERDES_COM_SYS_CLK_CTRL
QSBE, 32, //0x40 QSERDES_COM_SYSCLK_BUF_ENABLE
Offset (0x048),
QCPI, 32, //0x048 QSERDES_COM_PLL_IVCO
Offset (0x05C),
QCED, 32, //0x05C QSERDES_COM_CLK_EP_DIV
QCP0, 32, //0x060 QSERDES_COM_CP_CTRL_MODE0
Offset (0x068),
QPR0, 32, //0x068 QSERDES_COM_PLL_RCTRL_MODE0
Offset (0x070),
QPC0, 32, //0x070 QSERDES_COM_PLL_CCTRL_MODE0
Offset (0x080),
QSES, 32, //0x080 QSERDES_COM_SYSCLK_EN_SEL
Offset (0x088),
QCRC, 32, //0x088 QSERDES_COM_RESETSM_CNTRL
Offset (0x090),
QCLC, 32, //0x090 QSERDES_COM_LOCK_CMP_EN
Offset (0x098),
QC1M, 32, //0x098 QSERDES_COM_LOCK_CMP1_MODE0
QC2M, 32, //0x09C QSERDES_COM_LOCK_CMP2_MODE0
QC3M, 32, //0x0A0 QSERDES_COM_LOCK_CMP3_MODE0
Offset (0x0B0),
QSM0, 32, //0x0B0 QSERDES_COM_DEC_START_MODE0
Offset (0x0B8),
QS1M, 32, //0x0B8 QSERDES_COM_DIV_FRAC_START1_MODE0
QS2M, 32, //0x0BC QSERDES_COM_DIV_FRAC_START2_MODE0
QS3M, 32, //0x0C0 QSERDES_COM_DIV_FRAC_START3_MODE0
Offset (0x0D8),
QIG0, 32, //0x0D8 QSERDES_COM_INTEGLOOP_GAIN0_MODE0
QIG1, 32, //0x0DC QSERDES_COM_INTEGLOOP_GAIN1_MODE0
Offset (0x0F0),
QCVT, 32, //0x0F0 QSERDES_COM_VCO_TUNE_MAP
QVT1, 32, //0x0F4 QSERDES_COM_VCO_TUNE1_MODE0
QVT2, 32, //0x0F8 QSERDES_COM_VCO_TUNE2_MODE0
Offset (0x11C),
QTT1, 32, //0x11C QSERDES_COM_VCO_TUNE_TIMER1
QTT2, 32, //0x120 QSERDES_COM_VCO_TUNE_TIMER2
Offset (0x138),
QCCS, 32, //0x138 QSERDES_COM_CLK_SELECT
QCHS, 32, //0x13C QSERDES_COM_HSCLK_SEL
Offset (0x148),
QCD0, 32, //0x148 QSERDES_COM_CORECLK_DIV_MODE0
Offset (0x154),
QCCN, 32, //0x154 QSERDES_COM_CORE_CLK_EN
Offset (0x15C),
QCCC, 32, //0x15C QSERDES_COM_CMN_CONFIG
Offset (0x164),
QMCS, 32, //0x164 QSERDES_COM_SVS_MODE_CLK_SEL
Offset (0x184),
QCCM, 32, //0x184 QSERDES_COM_CMN_MODE
}
// PCIE_0_QSERDES_TX_QSERDES_TX_PCIE_USB3_QMP_TX
OperationRegion(CP03, SystemMemory, 0x01C06200, 0xA8)
Field(CP03, DWordAcc, NoLock, Preserve){
Offset (0x044),
QTOT, 32, //0x044 QSERDES_TX_RES_CODE_LANE_OFFSET_TX
Offset (0x060),
QTDE, 32, //0x060 QSERDES_TX_HIGHZ_DRVR_EN
Offset (0x08C),
QTM1, 32, //0x08C QSERDES_TX_LANE_MODE_1
Offset (0x0A4),
QTL2, 32, //0x0A4 QSERDES_TX_RCV_DETECT_LVL_2
}
// PCIE_0_QSERDES_RX_QSERDES_RX_PCIE_USB3_QMP_RX
OperationRegion(CP04, SystemMemory, 0x01C06400, 0x16C)
Field(CP04, DWordAcc, NoLock, Preserve){
Offset (0x00C),
QRSH, 32, //0x00C QSERDES_RX_UCDR_SO_GAIN_HALF
Offset (0x014),
QRSG, 32, //0x014 QSERDES_RX_UCDR_SO_GAIN
Offset (0x034),
QRUS, 32, //0x034 QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE
Offset (0x03C),
QRFL, 32, //0x03C QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW
Offset (0x044),
QRPC, 32, //0x044 QSERDES_RX_UCDR_PI_CONTROLS
Offset (0x0D4),
QRC2, 32, //0x0D4 QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2
QRC3, 32, //0x0D8 QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3
QRC4, 32, //0x0DC QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4
Offset (0x0F8),
QRA1, 32, //0x0F8 QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1
QRA2, 32, //0x0FC QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2
Offset (0x100),
QRSE, 32, //0x100 QSERDES_RX_SIGDET_ENABLES
QRSC, 32, //0x104 QSERDES_RX_SIGDET_CNTRL
Offset (0x10C),
QRDC, 32, //0x10C QSERDES_RX_SIGDET_DEGLITCH_CNTRL
Offset (0x11C),
QRIM, 32, //0x11C QSERDES_RX_RX_INTERFACE_MODE
Offset (0x164),
QRM0, 32, //0x164 QSERDES_RX_RX_MODE_00
QRM1, 32, //0x168 QSERDES_RX_RX_MODE_01
}
// PCIE_0_PCIE_USB3_PCS_MISC_PCIE_USB3_PCS_MISC_PCIE_USB3_PCS_MISC
OperationRegion(CP05, SystemMemory, 0x01C06600, 0x70)
Field(CP05, DWordAcc, NoLock, Preserve){
Offset (0x02C),
PMDC, 32, //0x02C PCIE_PCS_MISC_OSC_DTCT_CONFIG2
Offset (0x044),
PAC1, 32, //0x044 PCIE_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1
Offset (0x054),
PMC2, 32, //0x054 PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG2
PMC3, 32, //0x058 PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG3
PMC4, 32, //0x05C PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG4
PMC5, 32, //0x060 PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG5
}
// PCIE_0_PCIE_USB3_PCS_PCIE_USB3_PCS_PCIE_USB3_PCS
OperationRegion(CP06, SystemMemory, 0x01C06800, 0x210)
Field(CP06, DWordAcc, NoLock, Preserve){
PPSR, 32, //0x000 PCIE_PCS_SW_RESET
PPDC, 32, //0x004 PCIE_PCS_POWER_DOWN_CONTROL
PCST, 32, //0x008 PCIE_PCS_START_CONTROL
Offset (0x054),
PERD, 32, //0x054 PCIE_PCS_ENDPOINT_REFCLK_DRIVE
Offset (0x06C),
PSC4, 32, //0x06C PCIE_PCS_POWER_STATE_CONFIG4
Offset (0x0A0),
PDTA, 32, //0x0A0 PCIE_PCS_PWRUP_RESET_DLY_TIME_AUXCLK
PLTA, 32, //0x0A4 PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK
PLCD, 32, //0x0A8 PCIE_PCS_PLL_LOCK_CHK_DLY_TIME
Offset (0x0C4),
PFC1, 32, //0x0C4 PCIE_PCS_FLL_CNTRL1
PFC2, 32, //0x0C8 PCIE_PCS_FLL_CNTRL2
PFVL, 32, //0x0CC PCIE_PCS_FLL_CNT_VAL_L
PFVH, 32, //0x0D0 PCIE_PCS_FLL_CNT_VAL_H_TOL
PFMC, 32, //0x0D4 PCIE_PCS_FLL_MAN_CODE
Offset (0x174),
PPPS, 32, //0x174 PCIE_PCS_PCS_STATUS
Offset (0x1A8),
PSDM, 32, //0x1A8 PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB
PODA, 32, //0x1AC PCIE_PCS_OSC_DTCT_ACTIONS
PPSC, 32, //0x1B0 PCIE_PCS_SIGDET_CNTRL
Offset (0x1D8),
PRSL, 32, //0x1D8 PCIE_PCS_RX_SIGDET_LVL
PDAL, 32, //0x1DC PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB
PDAM, 32, //0x1E0 PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB
Offset (0x20C),
PRC1, 32, //0x20C PCIE_PCS_REFGEN_REQ_CONFIG1
}
// PCIE_0_PCIE20_DBI
OperationRegion(CP07, SystemMemory, 0x60000000, 0x1000)
Field(CP07, DWordAcc, NoLock, Preserve){
Offset(0x4),
SCR0, 32, //0x04 STATUS_COMMAND_REG
CRI0, 32, //0x08 TYPE1_CLASS_CODE_REV_ID_REG
Offset(0x10),
R0B0, 32, //0x10 PCIE_0_BAR0_REG
R0B1, 32, //0x14 PCIE_0_BAR1_REG
BNR0, 32, //0x18 PCIE_0_SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG
Offset(0x7C),
LCA0, 32, //0x7C PCIE_0_LINK_CAPABILITIES_REG
LCS0, 32, //0x80 PCIE_0_LINK_CONTROL_LINK_STATUS_REG
Offset(0x88),
SLC0, 32, //0x88 SLOT_CAS
Offset(0xa0),
LC20, 32, //0xa0 PCIE_0_LINK_CONTROL2_LINK_STATUS2_REG
Offset(0x8bc),
CSW0, 32, // 0x8bc CS Write Access register
Offset(0x900),
IAV0, 32, //0x900 PCIE_0_IATU_VIEWPORT_REG
CR10, 32, //0x904 PCIE_0_PL_IATU_REGION_CTRL_REG_1_OUTBOUND_0
CR20, 32, //0x908 PCIE_0_PL_IATU_REGION_CTRL_REG_2_OUTBOUND_0
ILB0, 32, //0x90C PCIE_0_PL_IATU_LWR_BASE_ADDR_REG_OUTBOUND_0
IUB0, 32, //0x910 PCIE_0_PL_IATU_UPPER_BASE_ADDR_REG_OUTBOUND_0
ILR0, 32, //0x914 PCIE_0_PL_IATU_LIMIT_ADDR_REG_OUTBOUND_0
ILT0, 32, //0x918 PCIE_0_PL_IATU_LWR_TARGET_ADDR_REG_OUTBOUND_0
IUT0, 32, //0x91C PCIE_0_PL_IATU_UPPER_TARGET_ADDR_REG_OUTBOUND_0
Offset(0xF24),
ESC0, 32, //0xF24 PCIE_0_PCIE20_ELBI_SYS_CTRL
EST0, 32, //0xF28 PCIE_0_PCIE20_ELBI_SYS_STTS
Offset(0xFC4),
ECS0, 32, //0xFC4 PCIE_0_PCIE20_ELBI_CS2_ENABLE
}
// Setup PHY
Method(PPU0, 0x0, Serialized) {
Name(TOUT, Zero)
Store (0x04, PDT0) // PCIE20_PARF_DEVICE_TYPE
Store (0x01, PPDC) // PCIE_PCS_POWER_DOWN_CONTROL
Store (0x14, QECE) // QSERDES_COM_BIAS_EN_CLKBUFLR_EN
Store (0x30, QCCS) // QSERDES_COM_CLK_SELECT
Store (0x07, QCPI) // QSERDES_COM_PLL_IVCO
Store (0x06, QCCC) // QSERDES_COM_CMN_CONFIG
Store (0x01, QCLC) // QSERDES_COM_LOCK_CMP_EN
Store (0x20, QCRC) // QSERDES_COM_RESETSM_CNTRL
Store (0x00, QCVT) // QSERDES_COM_VCO_TUNE_MAP
Store (0x01, QVT2) // QSERDES_COM_VCO_TUNE2_MODE0
Store (0xC9, QVT1) // QSERDES_COM_VCO_TUNE1_MODE0
Store (0xFF, QTT1) // QSERDES_COM_VCO_TUNE_TIMER1
Store (0x3F, QTT2) // QSERDES_COM_VCO_TUNE_TIMER2
Store (0x01, QMCS) // QSERDES_COM_SVS_MODE_CLK_SEL
Store (0x00, QCCN) // QSERDES_COM_CORE_CLK_EN
Store (0x0A, QCD0) // QSERDES_COM_CORECLK_DIV_MODE0
Store (0x19, QCED) // QSERDES_COM_CLK_EP_DIV
Store (0x90, QCE1) // QSERDES_COM_CLK_ENABLE1
Store (0x82, QSM0) // QSERDES_COM_DEC_START_MODE0
Store (0x02, QS3M) // QSERDES_COM_DIV_FRAC_START3_MODE0
Store (0xEA, QS2M) // QSERDES_COM_DIV_FRAC_START2_MODE0
Store (0xAB, QS1M) // QSERDES_COM_DIV_FRAC_START1_MODE0
Store (0x00, QC3M) // QSERDES_COM_LOCK_CMP3_MODE0
Store (0x0D, QC2M) // QSERDES_COM_LOCK_CMP2_MODE0
Store (0x04, QC1M) // QSERDES_COM_LOCK_CMP1_MODE0
Store (0x00, QCHS) // QSERDES_COM_HSCLK_SEL
Store (0x06, QCP0) // QSERDES_COM_CP_CTRL_MODE0
Store (0x16, QPR0) // QSERDES_COM_PLL_RCTRL_MODE0
Store (0x36, QPC0) // QSERDES_COM_PLL_CCTRL_MODE0
Store (0x01, QCCM) // QSERDES_COM_CMN_MODE
Store (0x02, QSCC) // QSERDES_COM_SYS_CLK_CTRL
Store (0x06, QSBE) // QSERDES_COM_SYSCLK_BUF_ENABLE
Store (0x04, QSES) // QSERDES_COM_SYSCLK_EN_SEL
Store (0x00, QIG1) // QSERDES_COM_INTEGLOOP_GAIN1_MODE0
Store (0x3F, QIG0) // QSERDES_COM_INTEGLOOP_GAIN0_MODE0
Store (0x09, QCB1) // QSERDES_COM_BG_TIMER
Store (0x01, QSEC) // QSERDES_COM_SSC_EN_CENTER
Store (0x40, QSP1) // QSERDES_COM_SSC_PER1
Store (0x01, QSP2) // QSERDES_COM_SSC_PER2
Store (0x02, QAP1) // QSERDES_COM_SSC_ADJ_PER1
Store (0x00, QAP2) // QSERDES_COM_SSC_ADJ_PER2
Store (0x7E, QSS1) // QSERDES_COM_SSC_STEP_SIZE1
Store (0x15, QSS2) // QSERDES_COM_SSC_STEP_SIZE2
Store (0x02, QTOT) // QSERDES_TX_RES_CODE_LANE_OFFSET_TX
Store (0x12, QTL2) // QSERDES_TX_RCV_DETECT_LVL_2
Store (0x10, QTDE) // QSERDES_TX_HIGHZ_DRVR_EN
Store (0x06, QTM1) // QSERDES_TX_LANE_MODE_1
Store (0x03, QRSC) // QSERDES_RX_SIGDET_CNTRL
Store (0x10, QRSE) // QSERDES_RX_SIGDET_ENABLES
Store (0x14, QRDC) // QSERDES_RX_SIGDET_DEGLITCH_CNTRL
Store (0x0E, QRC2) // QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2
Store (0x04, QRC3) // QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3
Store (0x1A, QRC4) // QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4
Store (0x4B, QRUS) // QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE
Store (0x04, QRSG) // QSERDES_RX_UCDR_SO_GAIN
Store (0x04, QRSH) // QSERDES_RX_UCDR_SO_GAIN_HALF
Store (0x71, QRA1) // QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1
Store (0x59, QRM0) // QSERDES_RX_RX_MODE_00
Store (0x59, QRM1) // QSERDES_RX_RX_MODE_01
Store (0x80, QRA2) // QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2
Store (0x40, QRIM) // QSERDES_RX_RX_INTERFACE_MODE
Store (0x71, QRPC) // QSERDES_RX_UCDR_PI_CONTROLS
Store (0x40, QRFL) // QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW
Store (0x04, PERD) // PCIE_PCS_ENDPOINT_REFCLK_DRIVE
Store (0x52, PMDC) // PCIE_PCS_MISC_OSC_DTCT_CONFIG2
Store (0x10, PMC2) // PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG2
Store (0x1A, PMC4) // PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG4
Store (0x06, PMC5) // PCIE_PCS_MISC_OSC_DTCT_MODE2_CONFIG5
Store (0x83, PFC2) // PCIE_PCS_FLL_CNTRL2
Store (0x09, PFVL) // PCIE_PCS_FLL_CNT_VAL_L
Store (0xA2, PFVH) // PCIE_PCS_FLL_CNT_VAL_H_TOL
Store (0x40, PFMC) // PCIE_PCS_FLL_MAN_CODE
Store (0x02, PFC1) // PCIE_PCS_FLL_CNTRL1
Store (0x00, PODA) // PCIE_PCS_OSC_DTCT_ACTIONS
Store (0x01, PDTA) // PCIE_PCS_PWRUP_RESET_DLY_TIME_AUXCLK
Store (0x00, PDAM) // PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB
Store (0x20, PDAL) // PCIE_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB
Store (0x00, PSDM) // PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB
Store (0x01, PLTA) // PCIE_PCS_LP_WAKEUP_DLY_TIME_AUXCLK
Store (0x73, PLCD) // PCIE_PCS_PLL_LOCK_CHK_DLY_TIME
Store (0xBB, PRSL) // PCIE_PCS_RX_SIGDET_LVL
Store (0x03, PPSC) // PCIE_PCS_SIGDET_CNTRL
Store (0x0D, PRC1) // PCIE_PCS_REFGEN_REQ_CONFIG1
Store (0x00, PSC4) // PCIE_PCS_POWER_STATE_CONFIG4
Store (0x00, PAC1) // PCIE_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1
// Version 2 and Higher Changes
If (LGreaterEqual (\_SB.SIDV,0x00020000))
{
//V1 and V2 PHY settings are same for PCI0
}
Store (0x03, PPDC) // PCIE_PCS_POWER_DOWN_CONTROL
Store (0x00, PPSR) // PCIE_PCS_SW_RESET
Store (0x03, PCST) // PCIE_PCS_START_CONTROL
Store (PPPS, Local0) // PCIE_PCS_PCS_STATUS
// loop until HWIO_PCIE_PCS_PCS_STATUS_PHYSTATUS_BMSK is '0'
While(And (Local0 , 0x40))
{
Sleep(1)
Increment(TOUT)
If (LEqual(TOUT, 0xF))
{
Break
}
Store (PPPS, Local0)
}
If(LEqual(TOUT, 0xF))
{
//Timeout occurred after 15 ms, so return an error value
Return(One)
}
Else
{
// PHY Init success
Return(Zero)
}
}
// Setup Link
Method(LTS0, 0x0, Serialized) {
Name(TOUT, Zero)
Store(LC20, Local0) ////PCIE_0_LINK_CONTROL2_LINK_STATUS2_REG
OR(Local0, 0x40, Local0) //set 3.5dB transmitter de-emphassis
Store(Local0, LC20)
Store (0x100, PLT0)// PCIE_0_PCIE20_PARF_PCIE20_PARF_LTSSM = 0x100
Store (EST0, Local0)// PCIE20_ELBI_SYS_STTS
While(LNotEqual(And(Local0 , 0x400), 0x400))// check for HWIO_PCIE20_ELBI_SYS_STTS_XMLH_LINK_UP_BMSK
{
Sleep(1)
Increment(TOUT)
If (LEqual(TOUT, 0x96))
{
Break
}
Store (EST0, Local0)
}
If(LEqual(TOUT, 0x96))
{
//Timeout occurred after 150 ms, so return an error value
Return(One)
}
Else
{
// LTSSM success
Return(Zero)
}
}
// Setup iATU
Method(IAT0, 0x0, Serialized) {
Store (0x01, IAV0)// IATU_VIEWPORT_REG
Store (0x60100000, ILB0)// PL_IATU_LWR_BASE_ADDR_REG_OUTBOUND_0
Store (0x00, IUB0)// PL_IATU_UPPER_BASE_ADDR_REG_OUTBOUND_0
Store (0x601FFFFF, ILR0)// PL_IATU_LIMIT_ADDR_REG_OUTBOUND_0
Store (0x01000000, ILT0 )// PL_IATU_LWR_TARGET_ADDR_REG_OUTBOUND_0
Store (0x00, IUT0)// PL_IATU_UPPER_TARGET_ADDR_REG_OUTBOUND_0
Store (0x04, CR10)// PL_IATU_REGION_CTRL_REG_1_OUTBOUND_0
Store (0x80000000, CR20)// PL_IATU_REGION_CTRL_REG_2_OUTBOUND_0
Store (0x010100, BNR0)// SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG
}
// Rootport Ecam-Blocker Method
// Arg0 - Block Base Address
// Arg1 - Block Limit Address
Method(REB0, 0x2, Serialized) {
Store (PSC0, Local0)
// Disable ECAM Blocker Region-0 at 26th bit
AND (Local0, 0xFBFFFFFF, Local0)
Store (Local0, PSC0)
// Configure Region Base and Limit
Store (Arg0, WBL0)
Store (0x00, WBH0)
Store (Arg1, WLL0)
Store (0x00, WLH0)
Store (Arg0, RBL0)
Store (0x00, RBH0)
Store (Arg1, RLL0)
Store (0x00, RLH0)
Store (PSC0, Local0)
// Enable ECAM Blocker Region-0 at 26th bit
OR (Local0, 0x04000000, Local0)
Store (Local0, PSC0)
}
// Endpoint Ecam-Blocker Method
// Arg0 - Block Base Address
// Arg1 - Block Limit Address
Method(EEB0, 0x2, Serialized) {
Store (PSC0, Local0)
// Disable ECAM Blocker Region-2 at 30th bit
AND (Local0, 0xBFFFFFFF, Local0)
Store (Local0, PSC0)
// Configure Region Base and Limit
Store (Arg0, WBL1)
Store (0x00, WBH1)
Store (Arg1, WLL1)
Store (0x00, WLH1)
Store (Arg0, RBL1)
Store (0x00, RBH1)
Store (Arg1, RLL1)
Store (0x00, RLH1)
Store (PSC0, Local0)
// Enable ECAM Blocker Region-2 at 30th bit
OR (Local0, 0x40000000, Local0)
Store (Local0, PSC0)
}
// Configure the limit for PCIe0 RP ECAM blocker
Name(E0LT, 0x600FFFFF)
// Setup Misc Configuration
Method(MSC0, 0x0, Serialized) {
// Memory Enable Compliance
Store (SCR0, Local0)
OR (Local0, 0x2, Local0)
Store (Local0, SCR0)
// Writing Slave address space size as 16MB
Store (0x01000000, PSL0)// PCIE20_PARF_SLV_ADDR_SPACE_SIZE
// Clear REQ_NOT_ENTER_L1 Field
Store(PPC0, Local0)
AND (Local0, 0xFFFFFFDF, Local0)
Store (Local0, PPC0)
// Enable DBI_RO_WR_EN to access CS1 region
Store (0x01, CSW0)
// Writing Link capability for enabling L1 and disabling L0s
Store(LCA0, Local0)
// Enable Optionality Compliance
OR(Local0, 0x00400000, Local0)
// Disable L0s
AND(Local0, 0xFFFFFBFF, Local0)
// Enable L1
OR(Local0, 0x00000800, Local0)
Store(Local0 , LCA0)
// Writing Bridge Class code
Store (CRI0, Local0)
AND (Local0, 0xFFFF, Local0)
OR (Local0, 0x06040000, Local0)
Store (Local0, CRI0)
// Assert CS2
Store (0x1, ECS0)
// Disable BAR0 and BAR1
Store (0x0, R0B0)
Store (0x0, R0B1)
// De-Assert CS2
Store (0x0, ECS0)
// Disable DBI_RO_WR_EN to access CS1 region
Store (0x00, CSW0)
// Store ECAM Base
Store (0x60000000, PPEB)
// Rootport Ecam-Blocker Method
REB0 (0x60001000, \_SB.E0LT)
// Endpoint Ecam-Blocker Method
EEB0 (0x60101000, 0x601FFFFF)
}
Name(G0D3, Zero)
PowerResource(P0ON, 0x5, 0) {
Name (_DEP, Package(0x1) {
\_SB.GIO0
})
Method(_STA){Return(0)}
Method(_ON) {
If(G0D3)
{
Store(0x1, GP0B)
Sleep(1)
Store(0x0, GP0B)
If(LEqual(\_SB.GIO0.GABL, 0x1))
{
Store (0x01, \_SB.PCI0.MOD1)
Sleep(5)
Store (0x00, \_SB.PCI0.MOD2)
}
Store (0x00, G0D3)
// Setup PHY
if ( \_SB.PPU0() )
{
// Method not returned 0x00, So handle the error
Store("PHY Init failed for Port 0", Debug)
// Store(0x0, MV01)
// This infinite loop would cause a bug check in Windows
While (One)
{
}
}
Sleep(5)
If(LEqual(\_SB.GIO0.GABL, 0x1))
{
Store (0x1, \_SB.PCI0.MOD2)
}
// Setup the Link
If( \_SB.LTS0() )
{
// Link training Failed!, block any potential access to Endpoint
// by extending the ECAM blocker region to hide the Endpoint
// config space
Store(0x601FFFFF, \_SB.E0LT)
}
Else
{
Store(0x600FFFFF, \_SB.E0LT)
}
// Setup iATU
\_SB.IAT0()
// Misc Configuration
\_SB.MSC0()
}
}
Method(_OFF) {
If(LEqual(G0D3, 0x0))
{
BreakPoint
Name(PTO0, Zero)
Store(1,G0D3)
Store(PSC0 , Local0)
OR(Local0, 0x10, Local0)
Store(Local0, PSC0)
Store(ESC0, Local0)
OR(Local0, 0x10, Local0)
Store(Local0 , ESC0)
Store (PPS0, Local0)
While(LNotEqual(And(Local0 , 0x20, Local0), 0x20))
{
Sleep(10)
Add(PTO0, 0x1, PTO0)
If(LEqual(PTO0, 0xA))
{
Break
}
Store (PPS0, Local0)
}
If(LEqual(\_SB.GIO0.GABL, 0x1))
{
Store (0x0, \_SB.PCI0.MOD2)
}
// Power Down Sequence for Port PHY
Store(0x0, PPDC)// PCIE_PCS_POWER_DOWN_CONTROL
Store(0x0, PCST)// PCIE_PCS_START_CONTROL
}
}
}
PowerResource(P0OF, 0x5, 0) {
Name (_DEP, Package(0x1) {
\_SB.GIO0
})
Method(_STA){Return(0)}
Method(_ON) {
}
Method(_OFF) {
}
Method(_RST, 0x0, NotSerialized) {
Store(0x1, GP0B)
Sleep(1)
Store(0x0, GP0B)
If(LEqual(\_SB.GIO0.GABL, 0x1))
{
Store (0x00, \_SB.PCI0.MOD1)
Sleep(1)
Store (0x01, \_SB.PCI0.MOD1)
Sleep(5)
Store (0x00, \_SB.PCI0.MOD2)
}
Store (0x00, G0D3)
// Setup PHY
if ( \_SB.PPU0() )
{
// Method not returned 0x00, So handle the error
Store("PHY Init failed for Port 0", Debug)
// Store(0x0, MV03)
// This infinite loop would cause a bug check in Windows
While (One)
{
}
}
Sleep(5)
If(LEqual(\_SB.GIO0.GABL, 0x1))
{
Store (0x1, \_SB.PCI0.MOD2)
}
// Setup the Link
If( \_SB.LTS0() )
{
// Link training Failed!, block any potential access to Endpoint
// by extending the ECAM blocker region to hide the Endpoint
// config space
Store(0x601FFFFF, \_SB.E0LT)
}
Else
{
Store(0x600FFFFF, \_SB.E0LT)
}
// Setup iATU
\_SB.IAT0()
// Misc Configuration
\_SB.MSC0()
}
}
Device (PCI0) {
Name (_DEP, Package(0x1) {
\_SB.PEP0
})
Name(_HID,EISAID("PNP0A08"))
Alias(\_SB.PSUB, _SUB)
Name(_CID,EISAID("PNP0A03"))
Name(_UID, 0x0)
Name(_SEG, 0x0)
Name(_BBN, 0x0)
Name(_PRT, Package(){
Package(){0x0FFFF, 0, 0, 181}, // Slot 1, INTA
Package(){0x0FFFF, 1, 0, 182}, // Slot 1, INTB
Package(){0x0FFFF, 2, 0, 183}, // Slot 1, INTC
Package(){0x0FFFF, 3, 0, 184} // Slot 1, INTD
})
// On SDM850 CCA is NOT supported by default for GEN2 port
Method (_CCA, 0)
{
Return (Zero)
}
// Wlan_11ad ACPI Enumeration, I don't think it's useful
// Include("wlan_11ad.asl")
Method(_PSC) {
Return(Zero)
}
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// [PCIE_0_PCIE20_DBI + 2MB(ECAM_SIZE)] to [DBI_SIZE - 2MB(ECAM_SIZE) - 64KB IO Space]
Memory32Fixed (ReadWrite, 0x60200000, 0x00DF0000)
WordBusNumber (ResourceProducer,
MinFixed, // IsMinFixed
MaxFixed, // IsMaxFixed
, // Decode: PosDecode
0, // AddressGranularity
0, // AddressMinimum
1, // AddressMaximum
0, // AddressTranslation
2) // RangeLength
})
Return (RBUF)
}
Name(SUPP, 0)
Name(CTRL, 0)
Method(_DSW, 0x3, NotSerialized) {
}
Method(_OSC, 4) {
// Check for proper UUID
If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
// Create DWord-adressable fields from the Capabilities Buffer
CreateDWordField(Arg3,0,CDW1)
CreateDWordField(Arg3,4,CDW2)
CreateDWordField(Arg3,8,CDW3)
// Save Capabilities DWord2 & 3
Store(CDW2,SUPP)
Store(CDW3,CTRL)
//No native hot plug support
//ASPM supported
//Clock PM supported
//MSI/MSI-X
If(LNotEqual(And(SUPP, 0x16), 0x16))
{
And(CTRL,0x1E) // Give control of everything to the OS
}
And(CTRL,0x15,CTRL)
If(LNotEqual(Arg1,One))
{ // Unknown revision
Or(CDW1,0x08,CDW1)
}
If(LNotEqual(CDW3,CTRL))
{ // Capabilities bits were masked
Or(CDW1,0x10,CDW1)
} // Update DWORD3 in the buffer
Store(CTRL,CDW3)
Return(Arg3)
}
Else {
Or(CDW1,4,CDW1) // Unrecognized UUID
Return(Arg3)
}
} // End _OSC
Method(_DSM, 0x4, NotSerialized) {
If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")))
{
// DSM Function
switch(ToInteger(Arg2))
{
//
// Function 0: Return supported functions, based on revision
//
case(0)
{
// revision 0: functions 1-9 are supported.
return (Buffer() {0xFF, 0x03})
}
//
// Function 1: For emulated ActiveBoth controllers, returns
// a package of controller-relative pin numbers.
// Each corresponding pin will have an initial
// polarity of ActiveHigh.
//
case(1)
{
Return (Package(2) {
Package(1){
1}, // Success
Package(3){
0,0x1,0x1}// Link Width supports x1??, PCI express card slot and WAKE# signal
})
}
case(2)
{
Return (Package(1) {
Package(4){
1,3,0,7} //Random have to check
})
}
case(3)
{
Return (Package(1) {
0}) //Random have to check , not implemented yet
}
case(4) // Not implemented yet
{
Return (Package(2) {
Package(1){0},
Package(4){
1,3,0,7} //Random have to check
})
}
case(5) // PCI Boot Configuration
{
Return (Package(1) {
1
})
}
case(6) // Latency Scale and Value
{
Return (Package(4) {
Package(1){0}, // Maximum Snoop Latency Scale
Package(1){0}, // Maximum Snoop Latency Value
Package(1){0}, // Maximum No-Snoop Latency Scale
Package(1){0} // Maximum No-Snoop Latency Value
})
}
case(7) // PCI Express Slot Parsing
{
Return (Package(1) {
1
})
}
case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume
{
Return (Package(1) {
1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow
})
}
case(9) // DSM for Specifying Device Readiness Durations
{
Return (Package(5) {
0xFFFFFFFF, // FW Reset Time
0xFFFFFFFF, // FW DL_Up Time
0xFFFFFFFF, // FW FLR Reset Time
0x00000000, // FW D3hot to D0 Time
0xFFFFFFFF // FW VF Enable Time
})
}
default
{
// Functions 9+: not supported
}
}
}
}
Name(_S0W, 4)
Name (GWLE, ResourceTemplate () //An existing GPIO Connection (to be used later)
{
GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {39}
})
Name (GWLP, ResourceTemplate () //An existing GPIO Connection (to be used later)
{
GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {35}
})
Scope(\_SB.GIO0) {
OperationRegion(WLEN, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long
OperationRegion(WLPR, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long
}
Field(\_SB.GIO0.WLEN, ByteAcc, NoLock, Preserve)
{
Connection (\_SB.PCI0.GWLE), // Following fields will be accessed atomically
MOD1, 1 // WIFI_EN
}
Field(\_SB.GIO0.WLPR, ByteAcc, NoLock, Preserve)
{
Connection (\_SB.PCI0.GWLP), // Following fields will be accessed atomically
MOD2, 1 // PERST
}
Name(_PR0, Package(){
\_SB.P0ON
})
Name(_PR3, Package(){
\_SB.P0ON
})
// PCIe Root Port 1
Device(RP1) {
Name(_ADR, 0x0)
Name(_PR0, Package(){
\_SB.P0OF
})
Name(_PR3, Package(){
\_SB.P0OF
})
Name(_PRR, Package(){
\_SB.P0OF
})
Name(_S0W, 4)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
GpioInt(Edge, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GIO0", 0 , ResourceConsumer, , ) {37}
})
Return (RBUF)
}
Name (_DSD, Package () {
ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"),
Package () {
Package (2) {"HotPlugSupportInD3", 1},
}
})
Method(_DSM, 0x4, NotSerialized) {
If(LEqual(Arg0,ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")))
{
// DSM Function
switch(ToInteger(Arg2))
{
case(0)
{
// revision 0: functions 1-7 are not supported.
return (Buffer() {0x01, 0x03})
}
case(8) // DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume
{
Return (Package(1) {
1 // Allow OS to avoid duplicating post power-on delay on Sx resume flow
})
}
case(9) // DSM for Specifying Device Readiness Durations
{
Return (Package(5) {
0xFFFFFFFF, // FW Reset Time
0xFFFFFFFF, // FW DL_Up Time
0xFFFFFFFF, // FW FLR Reset Time
0x00000000, // FW D3hot to D0 Time
0xFFFFFFFF // FW VF Enable Time
})
}
default
{
// Functions 1-7: not supported
}
}
}
}
}
} // End PCI0
Include("../common/pcie1.asl")

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//===========================================================================
// <pcie_resources.asl>
// DESCRIPTION
// This file contans the resources needed by pcie subsystem.
//
//===========================================================================
Scope(\_SB_.PEP0)
{
// PCIe Intra-Soc ports
Method(PEMD)
{
Return (PEMC)
}
Name(PEMC,
package()
{
Package()
{
"DEVICE",
"\\_SB.PCI0",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"FSTATE",
0x1, // f1 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
// PCIE Analog
package()
{
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L28 @1.0v
{
"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
1200000, // Voltage 1.2V : microvolts ( V )
1, // Enable = Enable
1, // Power Mode = NPM
0, // Head Room
},
},
// PCIE Core
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_LDO1_A",
1, // Voltage Regulator Type, 1 = LDO
880000, // Voltage (uV)
1, // Enable = Enable
1, // Power Mode = NPM
0, // Headroom
},
},
//Turning on PCIe core
Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 1}},
// ICB votes through PSTATE
package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 75000000, 0}},
package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 400000000, 200000000}},
package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 8, 19200000, 3}},
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
package() {"CLOCK", package() {"gcc_pcie_0_pipe_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_0_aux_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_0_slv_axi_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_0_slv_q2a_axi_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_0_mstr_axi_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_0_cfg_ahb_clk", 2}},
// common clocks
package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}},
// ICB votes
package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_0_CFG", 0, 0}},
package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_0", "ICBID_SLAVE_EBI1", 0, 0}},
// Turn off PCIe core
Package() { "FOOTSWITCH", Package() { "pcie_0_gdsc", 2}},
// PCIE Analog
package()
{
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L28 @1.0v
{
"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
0, // Voltage 1.2V : microvolts ( V )
0, // Enable = Disable
0, // Power Mode = NPM
0, // Head Room
},
},
// PCIE Core
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_LDO1_A",
1, // Voltage Regulator Type, 1 = LDO
0, // Voltage (uV)
0, // Enable = Disable
0, // Power Mode = NPM
0, // Headroom
},
},
},
},
Package()
{
"DEVICE",
"\\_SB.PCI0.RP1",
Package()
{
"COMPONENT",
0x0, // Component 0
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"FSTATE",
0x1, // f1 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
},
},
Package()
{
"DEVICE",
"\\_SB.PCI1",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"FSTATE",
0x1, // f1 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
// PCIE Analog
package()
{
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L28 @1.0v
{
"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
1200000, // Voltage 1.2V : microvolts ( V )
1, // Enable = Enable
1, // Power Mode = NPM
0, // Head Room
},
},
// PCIE Core
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_LDO1_A",
1, // Voltage Regulator Type, 1 = LDO
880000, // Voltage (uV)
1, // Enable = Enable
1, // Power Mode = NPM
0, // Headroom
},
},
//Turning on PCIe core
Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 1}},
// ICB votes
package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 75000000, 0}},
package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 400000000, 200000000}},
/*
package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
package()
{
"PPP_RESOURCE_ID_CXO_BUFFERS_LNBBCLK1_A", // Resource ID
6, // Voltage Regulator type = CXO Buffer
1, // Force enable from s/w
0, // Disable pin control
},
},
*/
package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 1}},
package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 8, 19200000, 3}},
package() {"CLOCK", package() {"gcc_pcie_phy_refgen_clk", 8, 100000000, 3}},
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
package() {"CLOCK", package() {"gcc_pcie_1_pipe_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_phy_refgen_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_1_aux_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_1_slv_axi_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_1_slv_q2a_axi_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_1_mstr_axi_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_1_cfg_ahb_clk", 2}},
// common clocks
package() {"CLOCK", package() {"gcc_aggre_noc_pcie_tbu_clk", 2}},
package() {"CLOCK", package() {"gcc_pcie_phy_aux_clk", 2}},
// ICB votes
package() {"BUSARB", Package() { 3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_PCIE_1_CFG", 0, 0}},
package() {"BUSARB", Package() { 3, "ICBID_MASTER_PCIE_1", "ICBID_SLAVE_EBI1", 0, 0}},
// Turn off PCIe core
Package() { "FOOTSWITCH", Package() { "pcie_1_gdsc", 2}},
/*
package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
package()
{
"PPP_RESOURCE_ID_CXO_BUFFERS_LNBBCLK1_A", // Resource ID
6, // Voltage Regulator type = CXO Buffer
0, // Force enable from s/w
0, // Disable pin control
},
},
*/
// PCIE Analog
package()
{
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L28 @1.0v
{
"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
0, // Voltage 1.2V : microvolts ( V )
0, // Enable = Disable
0, // Power Mode = NPM
0, // Head Room
},
},
// PCIE Core
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_LDO1_A",
1, // Voltage Regulator Type, 1 = LDO
0, // Voltage (uV)
0, // Enable = Disable
0, // Power Mode = NPM
0, // Headroom
},
},
},
},
Package()
{
"DEVICE",
"\\_SB.PCI1.RP1",
Package()
{
"COMPONENT",
0x0, // Component 0
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"FSTATE",
0x1, // f1 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
},
},
})
}

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//
// The PEP Device & Driver Related Configuration
//
Device (PEP0)
{
Name (_HID, "QCOM0237")
Name (_CID, "PNP0D80")
Include("../common/thz.asl") // Driver for Dynamically Changing Thresholds of Thermal Zones
Method(_CRS)
{
// List interrupt resources in the order they are used in PEP_Driver.c
Return
(
ResourceTemplate ()
{
// TSENS threshold interrupts
// Controller 0: Low / high
Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {538}
// Controller 0: Critical
Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {540}
// Controller 1: Low / high
Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {539}
// Controller 1: Critical
Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {541}
// apss amc finish irq
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {37}
// apss epcb timeout irq
//Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {47}
// mdss amc finish irq
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {161}
// mdss epcb timeout irq
//Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {160}
// Inbound interrupt from AOP to Apps PEP Glink:
//SYS_apssQgicSPI[389] = 421
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {421}
//rpm_to_kpss_ipc_irq0 = SYSApcsQgicSpi169 = 201 (MPM)
//Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {201}
//rpm_to_kpss_ipc_irq0 = SYSApcsQgicSpi171 = 203 (wakeup)
//Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {203}
//o_pwr_dcvsh_interrupt: LMH debug interrupt for power cluster
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {64}
//o_perf_dcvsh_interrupt: LMH debug interrupt for perf cluster
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {65}
//ddrss_apps_interrupt[1]: BIMC BWMON
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {613}
}
)
}
// need 20 char and 1 D state info
Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve)
{
/* Connection Object - 0x007C is the unique identifier */
Connection(I2CSerialBus( 0x0001,,0x0,, "\\_SB.ABD",,,,)),
AccessAs(BufferAcc, AttribRawBytes(21)),
FLD0, 168
}
//Get port to connect to
Method(GEPT)
{
Name(BUFF, Buffer(4){})
CreateByteField(BUFF, 0x00, STAT)
CreateWordField(BUFF, 0x02, DATA)
Store(0x1, DATA) //in this example we will connect to ABDO
Return(DATA)
}
Name(ROST, 0x0)
// Number of CPUs to Park
Method(NPUR, 0x1, NotSerialized)
{
Store(Arg0, Index(\_SB_.AGR0._PUR, 1))
Notify(\_SB_.AGR0, 0x80)
}
// ACPI method to return intr descriptor
Method(INTR, 0x0, NotSerialized) {
Name(RBUF, Package()
{
// Version
0x00000002,
// Number of hosts
0x00000001,
// number of memory regions
0x00000003,
// number of IPC registers
0x00000001,
// Rpm: APCS_IPC(0)
// Host = SMEM_RPM
0x00000006,
// Physical address
0x17911008,
// Value
0x00000001,
// Reserved
0x00000000,
// Shared memory
// Start address
0x86000000,
// Size
0x00200000,
// Reserved
0x00000000,
// Reserved
0x00000000,
// MSG RAM
// Start address
0x0C300000,
// Size
0x00001000,
// Reserved
0x00000000,
// Reserved
0x00000000,
// IMEM or TZ_WONCE
// Start address
0x01fd4000,
// Size
0x00000008,
// Reserved
0x00000000,
// Reserved
0x00000000,
// IPC register 1
// Physical addr
0x1799000C,
// Reserved
0x00000000,
// Reserved
0x00000000,
// Reserved
0x00000000,
})
Return (RBUF)
}
Method(CRTC)
{
return (CTRX)
}
Name(CTRX,
Package()
{
// Methods (names are reversed) that are critical to
// system boot
"NSTC", // critical thermal sensors
"HLCB", // BCL sensor HID
"MMVD", // Discrete Vreg Mapping Package
"DSGP", //System Default Configuration, SDFR
"CCGP", // CPU Configuration
"MTPS", //Read the speaker calibration related parameters
"CPGP", // CPU cap for DCVS Package
"DMPP", // PEP resources (usually dummy devices required for power mgmt)
"VRDL", // DRV ID List
"GBDL", // Debugger configuration -- must be below DSGP (reading SDFR)
"SRDL", // Default resources -- must be below DSGP (reading SDFR)
}
)
Method(STND)
{
return (STNX)
}
Name(STNX,
Package()
{
// Power resources for devices
// Names are reversed (so method OCMD becomes DMCO)
//
// Following format must be followed for name:
// DMxx -- Exists on QCOM SoC. Will use normal PoFX for power mgmt
// XMxx -- Exists off QCOM SoC and uses legacy power mgmt (_PS1, _PS2, etc)
//
// The files where these methods are declared must be included
// at the bottom of this file and must exists inside the scope: \_SB.PEP0
"DMPO", //oem dummy
"DMSB", // buses resources
"DMQP", // dfs Resources
"DMMS", // SMMU
"DMPA", //AUDIO
"DMPC", //CAMERA
"DMPB", //COREBSP
"DM0G", //GRAPHICS
"DM1G", //GRAPHICS
"DM2G", //GRAPHICS
"DM3G", //GRAPHICS
"DM4G", //GRAPHICS
"DM5G", //GRAPHICS
"DM6G", //GRAPHICS
"DM7G", //GRAPHICS
"DM8G", //GRAPHICS
"DM9G", //GRAPHICS
"DMPS", //SUBSYSTEMDRIVERS
// "DMRC", //CRYPTO
"DMPL", // PLATFORM
// "DMTB", //BAMTestClient
"DMDQ", //QDSS
// "DMMT", //SMMUTestClient
"DMPI", //IPA
"DMWE", //EXTERNAL WIRELESS CONNECTIVITY
"XMPC", //CAMERA
"XMPL", // PLATFORM
// "XMPN", //SENSORS
"DMEP", //PCIE-Resources
}
)
//
// Core topology
//
Method(CTPM){
Name( CTPN, package(){
"CORE_TOPOLOGY",
8 // Kyro cores
})
return(CTPN)
}
// CPU/Core Configurations Packages
Name(CCFG,
Package ()
{
// Post computex cpu names
Package ()
{
"\\_SB.SYSM.CLUS.CPU0",
0x10, // CPU0.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU1",
0x11, // CPU1.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU2",
0x12, // CPU2.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU3",
0x13, // CPU3.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU4",
0x14, // CPU4.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU5",
0x15, // CPU5.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU6",
0x16, // CPU6.
},
Package ()
{
"\\_SB.SYSM.CLUS.CPU7",
0x17, // CPU7.
},
})
// Method to return CPU configuration packages
// PEP Get CPU Configuration
Method(PGCC)
{
Return(CCFG)
}
// DRV ID Configurations Packages
Name(DRVC,
Package ()
{
// PEP Supported DRV List
Package ()
{
"HLOS_DRV",
0x2, // HLOS Subsystem DRV ID.
"/icb/arbiter", // HLOS ICB resource node
},
Package ()
{
"DISPLAY_DRV",
0x9, // Display Subsystem DRV ID.
"/icb/arbiter/display", //Display ICB resource node
},
})
// Method to return DRV Id list packages
// PEP Get DRV Id list
Method(LDRV)
{
Return(DRVC)
}
// CPU cap for DCVS Packages
Name(DCVS,0x0)
// Method to return CPU cap for DCVS Package
Method(PGDS)
{
Return(DCVS)
}
// PPP Supported Resources Package
Name (PPPP,
Package()
{
// Resource ID // Set Interface Type // Get Interface Type
//------------------------ ---------------------------------------------- ----------------------------------------------
Package () { "PPP_RESOURCE_ID_SMPS1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS4_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS5_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS6_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS7_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS9_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS1_C", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS2_C", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_SMPS3_C", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO4_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO5_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO6_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO7_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO8_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO9_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO10_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO11_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO12_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO13_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO14_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO15_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO16_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO17_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO18_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO19_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO20_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO21_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO22_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO23_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO24_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO25_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO26_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO27_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LDO28_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LVS1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_LVS2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_RFCLK3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK1_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK2_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
Package () { "PPP_RESOURCE_ID_BUCK_BOOST1_B", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_RPMH", "PM_RESOURCE_SERVICE_INTERFACE_TYPE_PMIC_KMDF" },
})
// Method to return PPP Package
Method(PPPM)
{
Return (PPPP)
}
// Method to return System Default config packages
Name (PRRP,
Package()
{
// Resource type range Initial supported resource Last supported resource
//-------------------- -------------------------- -------------------------
"PPP_RESOURCE_RANGE_INFO_SMPS_A", "PPP_RESOURCE_ID_SMPS1_A", "PPP_RESOURCE_ID_SMPS13_A",
"PPP_RESOURCE_RANGE_INFO_SMPS_C", "PPP_RESOURCE_ID_SMPS1_C", "PPP_RESOURCE_ID_SMPS4_C",
"PPP_RESOURCE_RANGE_INFO_LDO_A", "PPP_RESOURCE_ID_LDO1_A", "PPP_RESOURCE_ID_LDO28_A",
"PPP_RESOURCE_RANGE_INFO_LVS_A", "PPP_RESOURCE_ID_LVS1_A", "PPP_RESOURCE_ID_LVS2_A",
"PPP_RESOURCE_RANGE_INFO_CXO_BUFFERS_A", "PPP_RESOURCE_ID_CXO_BUFFERS_BBCLK2_A", "PPP_RESOURCE_ID_CXO_BUFFERS_DIVCLK3_A",
"PPP_RESOURCE_RANGE_INFO_BUCK_BOOST_B", "PPP_RESOURCE_ID_BUCK_BOOST1_B", "PPP_RESOURCE_ID_BUCK_BOOST1_B",
})
// Method to return Pep Ppp Resource Range Package
Method(PPRR)
{
Return (PRRP)
}
// Method to return System Default config packages
// PEP Get System Default package
Method(PGSD)
{
Return(SDFR)
}
// Full PEP Device Package
Name(FPDP,0x0)
// Method to return Full PEP Managed Device List Package
Method(FPMD)
{
Return(FPDP)
}
//
// PEP Processor Performance configuration
// CPU cap for DCVS Packages
Name(PPPC,0x0)
// Method to return CPU cap for DCVS Package
Method(PGPC)
{
Return(PPPC)
}
// Methods to read USB DP & DM interrupts polarity
// The return names should match with buffers
// declared and defined in usb.asl file.
// This method allows PEP to read Polarity of
// eud_p0_dmse_int_mx & eud_p0_dpse_int_mx
// interrupts which belong to Primary USB Port (P0)
Method(DPRF) {
// Return DPRF
Return(\_SB.DPP0)
}
// This method allows PEP to read Polarity of
// eud_p1_dmse_int_mx & eud_p1_dpse_int_mx
// interrupts which belong to Secondary USB Port (P1)
Method(DMRF) {
// Return DMRF
Return(\_SB.DPP1)
}
}
// Data required by PEP
Include("../common/pep_libPdc.asl")
Include("../common/pep_libPCU.asl")
Include("../common/pep_vddresources.asl")
Include("../common/pep_lmh.asl")
Include("../common/pep_dvreg.asl")
Include("../common/pep_dbgSettings.asl")
// Device specific
Include("pep_defaults.asl")
Include("../common/pep_idle.asl")
Include("../common/pep_cprh.asl")
Include("../common/pep_dcvscfg.asl")
// Device specific, pep_tsens.asl is needed for PEP DeviceAdd
Include("pep_tsens.asl")
// Resources by area
Include("../common/audio_resources.asl")
Include("../common/graphics_resources.asl")
Include("../common/HoyaSmmu_resources.asl")
// Include("msft_resources.asl")
Include("../common/oem_resources.asl")
Include("../common/subsys_resources.asl")
Include("../common/pep_resources.asl")
Include("../common/corebsp_resources.asl")
Include("../common/ipa_resources.asl")
// Include("crypto_resources.asl")
Include("../common/wcnss_resources.asl")
// Include("cust_wcnss_resources.asl")
Include("../common/qdss_resources.asl")
Include("../common/pcie_resources.asl")

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Scope(\_SB.PEP0)
{
// Method to return CPR data
Method(CPRZ)
{
Return(CPRH)
}
//-----------------------------------------------------------------------------------------
// CPRh Napali V1
// ------------
//
//-----------------------------------------------------------------------------------------
// CPR data
Name(CPRH,
Package(){
"CPRH_SW_SETTING", // CPR SW Setting
0,
Package(){
"CPRH_CHIP_INFO",
321, // chip ID
1, // chip version
//-----------------------------------------------------------------------------------------
// APC Controller SW Setting
// -------------------------
//
//-----------------------------------------------------------------------------------------
Package(){
"CPRH_SW_CONTROLLER_SETTING",
0, //instance_num (doc: CPR SW)
"APC0", //rail_name (doc: voltage plan)
0x17DC0000, //cpr_register_addr (doc: SWI)
0x4000, //cpr_register_size (doc: SWI)
0, //count_mode (doc: voltage plan)
20, //count_repeat (doc: voltage plan)
15, //idle_clocks (doc: voltage plan)
12, //step_quot_max (doc: voltage plan)
11, //step_quot_min (doc: voltage plan)
1, //reset_step_quot_loop_en (doc: voltage plan) - TBD
8, //number_of_sensors (doc: HPG)
0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3
0, //sensor_mask (doc: voltage plan)
0, //sensor_bypass (doc: voltage plan)
0x17700, //auto_cont_interval (doc: voltage plan) //5ms
400, //base_voltage_mV (doc: CPR SW)
4, //voltage_multiplier (doc: CPR HPG)
4, //target_multiplier (doc: CPR HPG)
5, //mode_switch_timer (doc: voltage plan)
0, //initial_mode (doc: CPR HPG)
1, //temp_sensor_id_start (doc: CPR HPG)
5, //temp_sensor_id_end (doc: CPR HPG)
1, //error_step_limit_dn (doc: voltage plan)
1, //error_step_limit_up (doc: voltage plan)
1, //thread_aggregation_enable (doc: CPR HPG)
1, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period
0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG)
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand; (doc: voltage plan)
4, //MarginMaxNumCores; (doc: CPUSS HPG)
1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG)
4, //MarginPmicStepSize; (doc: PMIC HPG)
1, //MarginClosedLoopEn; (doc: CPR HPG)
0, //MarginCoreAdjEn; (doc: CPR HPG)
0, //MarginTempAdjEn; (doc: CPR HPG)
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17840800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "L3", 2, 2, 0, 0, },
//---------------------------------------------------------------------------------------------------------------------
// Thread 1 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 1, "Silver", 2, 2, 0, 0, },
},
Package(){
"CPRH_SW_CONTROLLER_SETTING",
1, //instance_num
"APC1", //rail_name
0x17DB0000, //cpr_register_addr
0x4000, //cpr_register_size
0, //count_mode
20, //count_repeat
15, //idle_clocks
14, //step_quot_max
9, //step_quot_min
1, //reset_step_quot_loop_en //TBD
14, //number_of_sensors
0, //sensor_thread_mask //Assigning to thread0
0, //sensor_mask
0, //sensor_bypass
0x17700, //auto_cont_interval
400, //base_voltage_mV
4, //voltage_multiplier
4, //target_multiplier
5, //mode_switch_timer
0, //initial_mode
6, //temp_sensor_id_start
10, //temp_sensor_id_end
1, //error_step_limit_dn
1, //error_step_limit_up
0, //thread_aggregation_enable
0, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage
0x4b00, //MarginTimerLowerVoltage
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand;
4, //MarginMaxNumCores;
1, //MarginLowerVoltageWaitSelect;
4, //MarginPmicStepSize;
1, //MarginClosedLoopEn;
0, //MarginCoreAdjEn;
0, //MarginTempAdjEn;
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17830800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, },
},
},
Package(){
"CPRH_CHIP_INFO",
321, // chip ID
2, // chip version
//-----------------------------------------------------------------------------------------
// APC Controller SW Setting
// -------------------------
//
//-----------------------------------------------------------------------------------------
Package(){
"CPRH_SW_CONTROLLER_SETTING",
0, //instance_num (doc: CPR SW)
"APC0", //rail_name (doc: voltage plan)
0x17DC0000, //cpr_register_addr (doc: SWI)
0x4000, //cpr_register_size (doc: SWI)
0, //count_mode (doc: voltage plan)
20, //count_repeat (doc: voltage plan)
15, //idle_clocks (doc: voltage plan)
12, //step_quot_max (doc: voltage plan)
11, //step_quot_min (doc: voltage plan)
1, //reset_step_quot_loop_en (doc: voltage plan) - TBD
8, //number_of_sensors (doc: HPG)
0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3
0, //sensor_mask (doc: voltage plan)
0, //sensor_bypass (doc: voltage plan)
0x17700, //auto_cont_interval (doc: voltage plan) //5ms
400, //base_voltage_mV (doc: CPR SW)
4, //voltage_multiplier (doc: CPR HPG)
4, //target_multiplier (doc: CPR HPG)
5, //mode_switch_timer (doc: voltage plan)
0, //initial_mode (doc: CPR HPG)
1, //temp_sensor_id_start (doc: CPR HPG)
5, //temp_sensor_id_end (doc: CPR HPG)
1, //error_step_limit_dn (doc: voltage plan)
1, //error_step_limit_up (doc: voltage plan)
1, //thread_aggregation_enable (doc: CPR HPG)
1, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period
0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG)
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand; (doc: voltage plan)
4, //MarginMaxNumCores; (doc: CPUSS HPG)
1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG)
4, //MarginPmicStepSize; (doc: PMIC HPG)
1, //MarginClosedLoopEn; (doc: CPR HPG)
0, //MarginCoreAdjEn; (doc: CPR HPG)
0, //MarginTempAdjEn; (doc: CPR HPG)
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17840800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "L3", 2, 2, 0, 0, },
//---------------------------------------------------------------------------------------------------------------------
// Thread 1 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 1, "Silver", 2, 2, 0, 0, },
},
Package(){
"CPRH_SW_CONTROLLER_SETTING",
1, //instance_num
"APC1", //rail_name
0x17DB0000, //cpr_register_addr
0x4000, //cpr_register_size
0, //count_mode
20, //count_repeat
15, //idle_clocks
14, //step_quot_max
9, //step_quot_min
1, //reset_step_quot_loop_en //TBD
14, //number_of_sensors
0, //sensor_thread_mask //Assigning to thread0
0, //sensor_mask
0, //sensor_bypass
0x17700, //auto_cont_interval
400, //base_voltage_mV
4, //voltage_multiplier
4, //target_multiplier
5, //mode_switch_timer
0, //initial_mode
6, //temp_sensor_id_start
10, //temp_sensor_id_end
1, //error_step_limit_dn
1, //error_step_limit_up
0, //thread_aggregation_enable
0, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage
0x4b00, //MarginTimerLowerVoltage
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand;
4, //MarginMaxNumCores;
1, //MarginLowerVoltageWaitSelect;
4, //MarginPmicStepSize;
1, //MarginClosedLoopEn;
0, //MarginCoreAdjEn;
0, //MarginTempAdjEn;
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17830800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, },
},
},
Package(){
"CPRH_CHIP_INFO",
341, // chip ID
1, // chip version
//-----------------------------------------------------------------------------------------
// APC Controller SW Setting
// -------------------------
//
//-----------------------------------------------------------------------------------------
Package(){
"CPRH_SW_CONTROLLER_SETTING",
0, //instance_num (doc: CPR SW)
"APC0", //rail_name (doc: voltage plan)
0x17DC0000, //cpr_register_addr (doc: SWI)
0x4000, //cpr_register_size (doc: SWI)
0, //count_mode (doc: voltage plan)
20, //count_repeat (doc: voltage plan)
15, //idle_clocks (doc: voltage plan)
12, //step_quot_max (doc: voltage plan)
11, //step_quot_min (doc: voltage plan)
1, //reset_step_quot_loop_en (doc: voltage plan) - TBD
8, //number_of_sensors (doc: HPG)
0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3
0, //sensor_mask (doc: voltage plan)
0, //sensor_bypass (doc: voltage plan)
0x17700, //auto_cont_interval (doc: voltage plan) //5ms
400, //base_voltage_mV (doc: CPR SW)
4, //voltage_multiplier (doc: CPR HPG)
4, //target_multiplier (doc: CPR HPG)
5, //mode_switch_timer (doc: voltage plan)
0, //initial_mode (doc: CPR HPG)
1, //temp_sensor_id_start (doc: CPR HPG)
5, //temp_sensor_id_end (doc: CPR HPG)
1, //error_step_limit_dn (doc: voltage plan)
1, //error_step_limit_up (doc: voltage plan)
1, //thread_aggregation_enable (doc: CPR HPG)
1, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period
0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG)
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand; (doc: voltage plan)
4, //MarginMaxNumCores; (doc: CPUSS HPG)
1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG)
4, //MarginPmicStepSize; (doc: PMIC HPG)
1, //MarginClosedLoopEn; (doc: CPR HPG)
0, //MarginCoreAdjEn; (doc: CPR HPG)
0, //MarginTempAdjEn; (doc: CPR HPG)
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17840800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "Silver", 2, 2, 0, 0, },
//---------------------------------------------------------------------------------------------------------------------
// Thread 1 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 1, "L3", 2, 2, 0, 0, },
},
Package(){
"CPRH_SW_CONTROLLER_SETTING",
1, //instance_num
"APC1", //rail_name
0x17DB0000, //cpr_register_addr
0x4000, //cpr_register_size
0, //count_mode
20, //count_repeat
15, //idle_clocks
14, //step_quot_max
9, //step_quot_min
1, //reset_step_quot_loop_en //TBD
14, //number_of_sensors
0, //sensor_thread_mask //Assigning to thread0
0, //sensor_mask
0, //sensor_bypass
0x17700, //auto_cont_interval
400, //base_voltage_mV
4, //voltage_multiplier
4, //target_multiplier
5, //mode_switch_timer
0, //initial_mode
6, //temp_sensor_id_start
10, //temp_sensor_id_end
1, //error_step_limit_dn
1, //error_step_limit_up
0, //thread_aggregation_enable
0, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage
0x4b00, //MarginTimerLowerVoltage
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand;
4, //MarginMaxNumCores;
1, //MarginLowerVoltageWaitSelect;
4, //MarginPmicStepSize;
1, //MarginClosedLoopEn;
0, //MarginCoreAdjEn;
0, //MarginTempAdjEn;
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17830800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, },
},
},
Package(){
"CPRH_CHIP_INFO",
341, // chip ID
2, // chip version
//-----------------------------------------------------------------------------------------
// APC Controller SW Setting
// -------------------------
//
//-----------------------------------------------------------------------------------------
Package(){
"CPRH_SW_CONTROLLER_SETTING",
0, //instance_num (doc: CPR SW)
"APC0", //rail_name (doc: voltage plan)
0x17DC0000, //cpr_register_addr (doc: SWI)
0x4000, //cpr_register_size (doc: SWI)
0, //count_mode (doc: voltage plan)
20, //count_repeat (doc: voltage plan)
15, //idle_clocks (doc: voltage plan)
12, //step_quot_max (doc: voltage plan)
11, //step_quot_min (doc: voltage plan)
1, //reset_step_quot_loop_en (doc: voltage plan) - TBD
8, //number_of_sensors (doc: HPG)
0xf0, //sensor_thread_mask (doc: HPG) L3 using sensor #0,1,2,3
0, //sensor_mask (doc: voltage plan)
0, //sensor_bypass (doc: voltage plan)
0x17700, //auto_cont_interval (doc: voltage plan) //5ms
400, //base_voltage_mV (doc: CPR SW)
4, //voltage_multiplier (doc: CPR HPG)
4, //target_multiplier (doc: CPR HPG)
5, //mode_switch_timer (doc: voltage plan)
0, //initial_mode (doc: CPR HPG)
1, //temp_sensor_id_start (doc: CPR HPG)
5, //temp_sensor_id_end (doc: CPR HPG)
1, //error_step_limit_dn (doc: voltage plan)
1, //error_step_limit_up (doc: voltage plan)
1, //thread_aggregation_enable (doc: CPR HPG)
1, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage (doc: CPR HPG) - TBD - PMIC delay for one step / CPR clock period
0x4b00, //MarginTimerLowerVoltage (doc: CPR HPG)
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand; (doc: voltage plan)
4, //MarginMaxNumCores; (doc: CPUSS HPG)
1, //MarginLowerVoltageWaitSelect; (doc: CPR HPG)
4, //MarginPmicStepSize; (doc: PMIC HPG)
1, //MarginClosedLoopEn; (doc: CPR HPG)
0, //MarginCoreAdjEn; (doc: CPR HPG)
0, //MarginTempAdjEn; (doc: CPR HPG)
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17840800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting //TBD - Voltage plan does not have entries for L3 for settings below
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "Silver", 2, 2, 0, 0, },
//---------------------------------------------------------------------------------------------------------------------
// Thread 1 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 1, "L3", 2, 2, 0, 0, },
},
Package(){
"CPRH_SW_CONTROLLER_SETTING",
1, //instance_num
"APC1", //rail_name
0x17DB0000, //cpr_register_addr
0x4000, //cpr_register_size
0, //count_mode
20, //count_repeat
15, //idle_clocks
14, //step_quot_max
9, //step_quot_min
1, //reset_step_quot_loop_en //TBD
14, //number_of_sensors
0, //sensor_thread_mask //Assigning to thread0
0, //sensor_mask
0, //sensor_bypass
0x17700, //auto_cont_interval
400, //base_voltage_mV
4, //voltage_multiplier
4, //target_multiplier
5, //mode_switch_timer
0, //initial_mode
6, //temp_sensor_id_start
10, //temp_sensor_id_end
1, //error_step_limit_dn
1, //error_step_limit_up
0, //thread_aggregation_enable
0, //thread_has_always_vote (doc: CPR HPG)
23, //1.2us/19.2MHz MarginTimerSettleVoltage
0x4b00, //MarginTimerLowerVoltage
//Below are temp adj related - Setting to zero for now.
0, //MarginInitialTempBand;
4, //MarginMaxNumCores;
1, //MarginLowerVoltageWaitSelect;
4, //MarginPmicStepSize;
1, //MarginClosedLoopEn;
0, //MarginCoreAdjEn;
0, //MarginTempAdjEn;
//---------------------------------------------------------------------------------------------------------------------
// Aging Setting
// ------------
"", //aging_rail_id (doc: power grid)
0, //aging_thread_index (doc: n/a)
0, //aging_measurement_voltage_mV (doc: voltage plan)
0, //aging_sensor_id (doc: voltage plan)
0, //age_ro_kv (/1000 = 1.62) (doc: voltage plan)
0, //derate_scaling_factor (doc: voltage plan)
0, //max_age_compensation (mV) (doc: voltage plan)
0, //bypass_sensor (doc: voltage plan)
//---------------------------------------------------------------------------------------------------------------------
// SAW4 Setting
// ------------
0x17830800, //saw_register_addr
0x400, //saw_register_size
1, //saw_enable
1, //saw_ctl_sel
0, //saw_tmr_clk_div
1, //saw_vlvl_width
1, //saw_vlvl_step_up
1, //saw_vlvl_step_dn
//---------------------------------------------------------------------------------------------------------------------
// Thread 0 SW Setting
// ------------------- thread# clk_domain_name up_threshold dn_threshold consecutive_up consecutive_dn
// ------- --------------- ------------ ------------ -------------- --------------
Package(){"CPRH_SW_THREAD_SETTING", 0, "Gold", 2, 2, 0, 2, },
},
},
})
}

434
DSDT/common/pep_dbgSettings.asl Normal file
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@ -0,0 +1,434 @@
/**
* This file contains debugger and debugger power resource information used by
* the PEP driver.
*/
Scope(\_SB.PEP0)
{
Method(LDBG){
return(NDBG)
}
Name( NDBG,
/**
* The debuggers package is used by PEP to detect when a debugger is connected,
* turn on the required power resources for a debugger and to turn off all
* debugger related resources when not in use (this logic is encompassed in PEP).
*
* The expected hiearchy of this package:
* DEBUGGERS
* TYPE
* String = SERIAL, USB2.0, USB3.0
* INSTANCES
* The instancepath of the drivers which the debugger impersonates
* DEBUG_ON
* The resources that need to be turned on for the debugger to work
* for the given controller type (SERIAL/USB2.0/USB3.0)
* DEBUG_OFF
* The resources to turn off when no debugger is connected for this
* debugger type and no HLOS driver is loaded for any one of the given
* HLOS types. The implementation for this feature is documented within
* PEP.
*
*/
package(){
"DEBUGGERS",
package()
{
"TYPE",
"SERIAL",
package()
{
"INSTANCES",
"\\_SB.UARD",
},
package()
{
"DEBUG_ON",
/**
* There is a limitation with KDCOM port, if RX engine is runnign when system
* enters deeper sleep mode, the UART can result in undefined behaviour, this may
* could lead to loss of Windbg connection.
**/
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}},// enable clock
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 9,8}},// mark suppressible
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 9,12}},// always ON
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 9,8 }}, // mark suppressible
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 9,12 }}, // always ON
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",3,7372800,4}}, //update frequency
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 9,8}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 9,12}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 10000000,1666,"HLOS_DRV", "SUPPRESSIBLE"}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 10000000,5000000,"HLOS_DRV", "SUPPRESSIBLE"}},
},
package()
{
"DEBUG_OFF",
}
},
// Secondary USB Port Debugger
package()
{
"TYPE",
"USB2.0",
package()
{
"INSTANCES",
"\\_SB.USB1",
//URS1 specific
//"\\_SB.URS1",
},
package()
{
"DEBUG_ON",
package()
{
// L12 - VDDA_QUSB_HS0_1P8
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L12 @1.8v
{
"PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
1800000, // Voltage 1.8V : microvolts ( V )
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
package()
{
// L24 - VDDA_QUSB_HS0_3P1
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L24 @ 3.075v
{
"PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
1, // Voltage Regulator type 1 = LDO
3075000, // Voltage = 3.075 V
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
package()
{
// L26 - VDDA_USB_SS_1P2 (QMP PHY)
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L2 @1.2v
{
"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
1200000, // Voltage 1.2V : microvolts ( V )
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
package()
{
// VDDA_USB_SS_CORE & VDDA_QUSB0_HS
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L1 @ 0.88v
{
"PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
880000, // Voltage (microvolts)
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
// Enable usb30_sec_gdsc power domain
package()
{
"FOOTSWITCH", // Footswitch
package()
{
"usb30_sec_gdsc", // USB 3.0 Core Power domain
1, //1==Enable
},
},
// Mark Suppressible for USB 3.0 Sleep Clock
package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 8,}},
// Mark Always On for USB 3.0 Sleep Clock
package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 9, 12,}},
// Enable USB 3.0 Sleep Clock
package() { "CLOCK", package() { "gcc_usb30_sec_sleep_clk", 1}},
// Mark Suppressible for USB PHY pipe Clock
package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 8,}},
// Mark Always ON for USB PHY pipe Clock
package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 9, 12,}},
// Enable PHY pipe Clock
package() { "CLOCK", package() { "gcc_usb3_sec_phy_pipe_clk", 1}},
// Mark Suppressible for gcc_aggre_usb3_sec_axi_clk
package() { "CLOCK", package() { "gcc_aggre_usb3_sec_axi_clk", 9, 8,}},
// Mark Always ON for gcc_aggre_usb3_sec_axi_clk
package() { "CLOCK", package() { "gcc_aggre_usb3_sec_axi_clk", 9, 12,}},
//aggre_usb3_sec_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
package() {"CLOCK", package() {"gcc_aggre_usb3_sec_axi_clk", 8, 120, 9}},
// Mark Suppressible for gcc_cfg_noc_usb3_sec_axi_clk
package() { "CLOCK", package() { "gcc_cfg_noc_usb3_sec_axi_clk", 9, 8,}},
// Mark Always ON for gcc_cfg_noc_usb3_sec_axi_clk
package() { "CLOCK", package() { "gcc_cfg_noc_usb3_sec_axi_clk", 9, 12,}},
// gcc_cfg_noc_usb3_sec_axi_clk should be configured to the frequency as master clock
// @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
package() {"CLOCK", package() {"gcc_cfg_noc_usb3_sec_axi_clk", 8, 120, 9}},
// Mark Suppressible for gcc_usb30_sec_master_clk
package() { "CLOCK", package() { "gcc_usb30_sec_master_clk", 9, 8,}},
// Mark Always ON for gcc_usb30_sec_master_clk
package() { "CLOCK", package() { "gcc_usb30_sec_master_clk", 9, 12,}},
// USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
package() {"CLOCK", package() {"gcc_usb30_sec_master_clk", 8, 120, 9}},
// Mark Suppressible for gcc_usb3_sec_phy_aux_clk
package() { "CLOCK", package() { "gcc_usb3_sec_phy_aux_clk", 9, 8,}},
// Mark Always ON for gcc_usb3_sec_phy_aux_clk
package() { "CLOCK", package() { "gcc_usb3_sec_phy_aux_clk", 9, 12,}},
// Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
package() {"CLOCK", package() {"gcc_usb3_sec_phy_aux_clk", 8, 1200, 7}},
// Mark Suppressible for gcc_usb_phy_cfg_ahb2phy_clk
package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 8,}},
// Mark Always ON for gcc_usb_phy_cfg_ahb2phy_clk
package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 12,}},
// Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
// Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
// Required for gcc_usb_phy_cfg_ahb2phy_clk
//BUS Arbiter Request (Type-3)
package()
{
"BUSARB",
package()
{
3, // Req Type
"ICBID_MASTER_APPSS_PROC", // Master
"ICBID_SLAVE_USB3_1", // Slave
400000000, // IB=400 MBps
0, // AB=0 MBps
"HLOS_DRV", // Optional: DRV Id
"SUPPRESSIBLE", // Optional: Set Type
}
},
//Vote for max freq: BUS Arbiter Request (Type-3)
// Instantaneous BW BytesPerSec = 671088640;
// Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_USB3_1", // Master
"ICBID_SLAVE_EBI1", // Slave
671088640, // IB=5Gbps
671088640, // AB=5Gbps
"HLOS_DRV", // Optional: DRV Id
"SUPPRESSIBLE", // Optional: Set Type
}
},
//Nominal==block vdd_min:
package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}},
},
package()
{
"DEBUG_OFF",
}
},
package()
{
"TYPE",
"USB3.0",
package()
{
"INSTANCES",
"\\_SB.URS0",
},
package()
{
"DEBUG_ON",
// LDO1, 26, 12, 24
package()
{
// L12 - VDDA_QUSB_HS0_1P8
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L12 @1.8v
{
"PPP_RESOURCE_ID_LDO12_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
1800000, // Voltage 1.8V : microvolts ( V )
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
package()
{
// L24 - VDDA_QUSB_HS0_3P1
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L24 @ 3.075v
{
"PPP_RESOURCE_ID_LDO24_A", // Voltage Regulator ID
1, // Voltage Regulator type 1 = LDO
3075000, // Voltage = 3.075 V
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
package()
{
// L26 - VDDA_USB_SS_1P2 (QMP PHY)
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L2 @1.2v
{
"PPP_RESOURCE_ID_LDO26_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
1200000, // Voltage 1.2V : microvolts ( V )
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
package()
{
// VDDA_USB_SS_CORE & VDDA_QUSB0_HS
"PMICVREGVOTE", // PMIC VREG resource
package() // Vote for L1 @ 0.88v
{
"PPP_RESOURCE_ID_LDO1_A", // Voltage Regulator ID
1, // Voltage Regulator type = LDO
880000, // Voltage (microvolts)
1, // SW Enable = Enable
7, // SW Power Mode = NPM
0, // Head Room
},
},
// Enable usb30_prim_gdsc power domain
package()
{
"FOOTSWITCH", // Footswitch
package()
{
"usb30_prim_gdsc", // USB 3.0 Core Power domain
1, //1==Enable
},
},
// Enable USB 3.0 Sleep Clock
package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 1}},
// Mark Suppressible for USB 3.0 Sleep Clock
package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 8,}},
// Mark Always On for USB 3.0 Sleep Clock
package() { "CLOCK", package() { "gcc_usb30_prim_sleep_clk", 9, 12,}},
// Enable PHY pipe Clock
package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 1}},
// Mark Suppressible for USB PHY pipe Clock
package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 8,}},
// Mark Always ON for USB PHY pipe Clock
package() { "CLOCK", package() { "gcc_usb3_prim_phy_pipe_clk", 9, 12,}},
// Mark Suppressible for gcc_aggre_usb3_prim_axi_clk
package() { "CLOCK", package() { "gcc_aggre_usb3_prim_axi_clk", 9, 8,}},
// Mark Always ON for gcc_aggre_usb3_prim_axi_clk
package() { "CLOCK", package() { "gcc_aggre_usb3_prim_axi_clk", 9, 12,}},
//aggre_usb3_prim_axi Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
package() {"CLOCK", package() {"gcc_aggre_usb3_prim_axi_clk", 8, 120, 9}},
// Mark Suppressible for gcc_cfg_noc_usb3_prim_axi_clk
package() { "CLOCK", package() { "gcc_cfg_noc_usb3_prim_axi_clk", 9, 8,}},
// Mark Always ON for gcc_cfg_noc_usb3_prim_axi_clk
package() { "CLOCK", package() { "gcc_cfg_noc_usb3_prim_axi_clk", 9, 12,}},
// gcc_cfg_noc_usb3_prim_axi_clk should be configured to the frequency as master clock
// @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
package() {"CLOCK", package() {"gcc_cfg_noc_usb3_prim_axi_clk", 8, 120, 9}},
// Mark Suppressible for gcc_usb30_prim_master_clk
package() { "CLOCK", package() { "gcc_usb30_prim_master_clk", 9, 8,}},
// Mark Always ON for gcc_usb30_prim_master_clk
package() { "CLOCK", package() { "gcc_usb30_prim_master_clk", 9, 12,}},
// USB 3.0 Master Clock @ 120 MHz 8 = Set & Enable; 120,9 -> Atleast 120 Mhz
package() {"CLOCK", package() {"gcc_usb30_prim_master_clk", 8, 120, 9}},
// Mark Suppressible for gcc_usb3_prim_phy_aux_clk
package() { "CLOCK", package() { "gcc_usb3_prim_phy_aux_clk", 9, 8,}},
// Mark Always ON for gcc_usb3_prim_phy_aux_clk
package() { "CLOCK", package() { "gcc_usb3_prim_phy_aux_clk", 9, 12,}},
// Phy Aux Clock @ 1.2 Mhz 8 = Set & Enable; 1.2, 7 -> Closest 1.2 Mhz
package() {"CLOCK", package() {"gcc_usb3_prim_phy_aux_clk", 8, 1200, 7}},
// Mark Suppressible for gcc_usb_phy_cfg_ahb2phy_clk
package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 8,}},
// Mark Always ON for gcc_usb_phy_cfg_ahb2phy_clk
package() { "CLOCK", package() { "gcc_usb_phy_cfg_ahb2phy_clk", 9, 12,}},
// Enable gcc_usb_phy_cfg_ahb2phy_clk, Frequency need not be set since its synced to CNOC
package() {"CLOCK", package() {"gcc_usb_phy_cfg_ahb2phy_clk", 1}},
// Vote for CNOC 100 MHz - 400 MB/s IB-only (AB = 0)
// Required for gcc_usb_phy_cfg_ahb2phy_clk
//BUS Arbiter Request (Type-3)
package()
{
"BUSARB",
package()
{
3, // Req Type
"ICBID_MASTER_APPSS_PROC", // Master
"ICBID_SLAVE_USB3_0", // Slave
400000000, // IB=400 MBps
0, // AB=0 MBps
"HLOS_DRV", // Optional: DRV Id
"SUPPRESSIBLE", // Optional: Set Type
}
},
//Vote for max freq: BUS Arbiter Request (Type-3)
// Instantaneous BW BytesPerSec = 671088640;
// Arbitrated BW BytesPerSec = 671088640 (5 x 1024 X 1024 x 1024)/8
package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_USB3_0", // Master
"ICBID_SLAVE_EBI1", // Slave
671088640, // IB=5Gbps
671088640, // AB=5Gbps
"HLOS_DRV", // Optional: DRV Id
"SUPPRESSIBLE", // Optional: Set Type
}
},
//Nominal==block vdd_min:
package() {"NPARESOURCE",Package() {1, "/arc/client/rail_cx", 256, "SUPPRESSIBLE"}},
},
package()
{
"DEBUG_OFF",
}
},
})
}

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Scope(\_SB.PEP0)
{
// CPU DCVS Configurations Packages
Name(NDCV,
Package ()
{
Package() //MSM v1
{
"CHIP_INFO",
321, // chip ID
1, // chip major version
0, // chip minor version
2, //Total number of CPU domain
Package() // Big Cluster configuration
{
"BIG", // Type of cluster
4, //Number of cores perf cluster.
"apcs_gold_sysleaf_clk",
Package(){300, 1037, 1574}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 9, 16}, //Cpu Efficient Performance Levels
},
Package() // Little Cluster configuration
{
"LITTLE", //Type of cluster
4, //Number of cores perf cluster.
"apcs_silver_sysleaf_clk",
Package(){300, 1210, 1594}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 11, 16}, //Cpu Efficient Performance Levels
},
Package() // L3_CACHE domain configuration
{
"L3_CACHE", //Type of cluster
"apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform
},
},
Package() //MSM v2
{
"CHIP_INFO",
321, // chip ID
2, // chip major version
0, // chip minor version
2, //Total number of CPU domain
Package() // Big Cluster configuration
{
"BIG", // Type of cluster
4, //Number of cores perf cluster.
"apcs_gold_sysleaf_clk",
Package(){826, 1363, 1460}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 7, 15}, //Cpu Efficient Performance Levels
},
Package() // Little Cluster configuration
{
"LITTLE", //Type of cluster
4, //Number of cores perf cluster.
"apcs_silver_sysleaf_clk",
Package(){300, 1229, 1325}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 11, 15}, //Cpu Efficient Performance Levels
},
Package() // L3_CACHE domain configuration
{
"L3_CACHE", //Type of cluster
"apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform
},
},
Package() //APQ v1
{
"CHIP_INFO",
341, // chip ID
1, // chip major version
0, // chip minor version
2, //Total number of CPU domain
Package() // Big Cluster configuration
{
"BIG", // Type of cluster
4, //Number of cores perf cluster.
"apcs_gold_sysleaf_clk",
Package(){300, 1037, 1574}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 9, 16}, //Cpu Efficient Performance Levels
},
Package() // Little Cluster configuration
{
"LITTLE", //Type of cluster
4, //Number of cores perf cluster.
"apcs_silver_sysleaf_clk",
Package(){300, 1210, 1594}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 11, 16}, //Cpu Efficient Performance Levels
},
Package() // L3_CACHE domain configuration
{
"L3_CACHE", //Type of cluster
"apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform
},
},
Package() //APQ v2
{
"CHIP_INFO",
341, // chip ID
2, // chip major version
0, // chip minor version
2, //Total number of CPU domain
Package() // Big Cluster configuration
{
"BIG", // Type of cluster
4, //Number of cores perf cluster.
"apcs_gold_sysleaf_clk",
Package(){826, 1363, 1460}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 7, 15}, //Cpu Efficient Performance Levels
},
Package() // Little Cluster configuration
{
"LITTLE", //Type of cluster
4, //Number of cores perf cluster.
"apcs_silver_sysleaf_clk",
Package(){300, 1229, 1325}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 11, 15}, //Cpu Efficient Performance Levels
},
Package() // L3_CACHE domain configuration
{
"L3_CACHE", //Type of cluster
"apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform
},
},
Package() //MSM v2
{
"CHIP_INFO",
348, // chip ID
2, // chip major version
0, // chip minor version
2, //Total number of CPU domain
Package() // Big Cluster configuration
{
"BIG", // Type of cluster
4, //Number of cores perf cluster.
"apcs_gold_sysleaf_clk",
Package(){826, 1363, 1460}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 7, 15}, //Cpu Efficient Performance Levels
},
Package() // Little Cluster configuration
{
"LITTLE", //Type of cluster
4, //Number of cores perf cluster.
"apcs_silver_sysleaf_clk",
Package(){300, 1229, 1325}, //Cpu Key Frequency
3, // Number of Efficient Performance Levels
Package(){0, 11, 15}, //Cpu Efficient Performance Levels
},
Package() // L3_CACHE domain configuration
{
"L3_CACHE", //Type of cluster
"apcs_l3_sysleaf_clk", //Clock ID. If this is NULL/0, that means no L3 domain supported on this platform
},
},
}) //End of NDCV method
// Method to return DCVS configuration packages
Method(LDCV)
{
return(NDCV)
}
}

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//===========================================================================
// <pep_dvreg.asl>
// DESCRIPTION
// This file contains the default discrete VREG mapping and method names
//
//===========================================================================
// NOTE: this file is included in the platform level pep.asl and can be replaced with platform
// specific discrete VREG definitions
Scope(\_SB.PEP0)
{
// Discrete Vreg Mapping Package
Name(DVMP,
Package()
{
// Virtual regulator to aggregate GPIO pin control of CHIP_PWD_L
// CHIP_PWD_L must be deasserted for BT to share a clock with AR6004
// BT and WLAN devices will take a vote on this virtual regulator to
// control the shared GPIO pin
Package()
{
"PPP_RESOURCE_ID_PMIC_GPIO_DV1", // Discrete Vreg ID
"PPP_RESOURCE_TYPE_DISCRETE_PMIC_GPIO", // Vreg type
Package()
{
"PM_DISCRETE_VREG_STATE_ON", // Mapping for VREG ON
package()
{
0, // pmic_number (PM8994) - must match pmic.asl
8,// gpio_id - GPIO #9
0, // Mode - GPIO configured as output - 0, 1 for input
0, // voltage_source - PM_GPIO_VIN0
1, // source - PM_GPIO_SOURCE_1 (drive logic HIGH)
0, // out_buffer_config - PM_GPIO_OUT_BUFFER_CONFIG_CMOS
1, // out_buffer_strength - PM_GPIO_OUT_BUFFER_LOW
0, // inversion <20> no invert
1, // External pin enable - PM_GPIO_PERPH_EN_ENABLE
5, // PM_GPIO_I_SOURCE_PULL_NO_PULL, ignored for Output mode.
},
},
Package()
{
"PM_DISCRETE_VREG_STATE_OFF", // Mapping for VREG OFF
package()
{
0, // pmic_number 0
8,// gpio_id - GPIO #9
0, // Mode - GPIO configured as output - 0, 1 for input
0, // voltage_source - PM_GPIO_VIN0
0, // source - PM_GPIO_SOURCE_0 (drive logic LOW)
0, // out_buffer_config - PM_GPIO_OUT_BUFFER_CONFIG_CMOS
1, // out_buffer_strength - PM_GPIO_OUT_BUFFER_LOW
0, // inversion <20> no invert
1, // External pin enable - PM_GPIO_PERPH_EN_ENABLE
5, // PM_GPIO_I_SOURCE_PULL_NO_PULL, ignored for Output mode.
},
},
},
//discrete vreg vote for MPP4
Package()
{
"PPP_RESOURCE_ID_PMIC_MPP_DV1", // Discrete Vreg ID
"PPP_RESOURCE_TYPE_DISCRETE_PMIC_MPP", // Vreg type
Package()
{
"PM_DISCRETE_VREG_STATE_ON", // Mapping for VREG ON
package()
{
0, // PMIC number
3, // MPP index (mpp #4)
0, // Direction, 0 - output
2, // VIO_2
1, // PM_MPP__DLOGIC__OUT_CTRL_HIGH
0, // PM_MPP__DLOGIC__DBUS_NONE
},
},
Package()
{
"PM_DISCRETE_VREG_STATE_OFF", // Mapping for VREG OFF
package()
{
0, // PMIC number
3, // MPP index (mpp #4)
0, // Direction, 0 - output
2, // VIO_2
0, // PM_MPP__DLOGIC__OUT_CTRL_LOW
0, // PM_MPP__DLOGIC__DBUS_NONE
},
},
},
})
// Method to return Discrete Vreg Mapping Package
Method(DVMM)
{
Return(DVMP)
}
}

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DSDT/common/pep_libPCU.asl Normal file
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Scope(\_SB.PEP0)
{
Method(LPCU){
return(NPCU)
}
Name( NPCU, package(){
"PCU_CONFIG",
9, // number of cores
1, // number of clusters
package(){
"PCU_CLUSTER_CONFIG",
9,
},
package(){
"PCU_PHYS_CONFIG",
0x17E00040, // Core 0
0x17E10040, // Core 1
0x17E20040, // Core 2
0x17E30040, // Core 3
0x17E40040, // Core 4
0x17E50040, // Core 5
0x17E60040, // Core 6
0x17E70040, // Core 7
0x17810104, // L3
}
})
}

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Scope(\_SB.PEP0)
{
Method(LPDC){
return(NPDC)
}
Name( NPDC, package(){
package(){
"INTERRUPT_CONFIG",
package(){
/// Data Format:
/// { INDEX , LOCAL_IRQ, IRQ_TYPE, TRIGGER_TYPE, [optional] FLAGS }
///
/// @param INDEX THIS IS ZERO BASED INDEX UNIQUE and INCREASING ORDER.
/// @param LOCAL_IRQ GPIO or QGIC IRQ number
/// @param IRQ_TYPE 0 for QGIC, 1 for GPIO
///
/// @param TRIGGER_TYPE 0-4; Set when MPM is init; will be overriden by HLOS values
/// 0 = LEVEL_LOW
/// 1 = RISING_EDGE
/// 2 = FALLING_EDGE
/// 3 = DUAL_EDGE
/// 4 = LEVEL HIGH
///
/// @param [opt] FLAGS 0-16 reference: file pdc_types.h
/// 0 = No Flags set (default)
/// 1 = Don't Program with HLOS given trigger type - instead use default PDC configuration
/// 2 = Program with Static trigger type
/// 4 = Forcefully disable pdc interrupt
/// 8 = Ignore OS sent Polarity configuration for PDC interrupt - instead use either default polarity or let it get updated internally
/// 16 = Ignore OS sent Mode configuration for PDC interrupt - instead use either default polarity or let it get updated internally
// Tsens Wake able interrupts
// // Mandatory wake-capable Tsens interrupts
package(){ 0, 538, 0, 1 }, // tsense0_upper_lower_intr
package(){ 1, 539, 0, 1 }, // tsense1_upper_lower_intr
package(){ 2, 540, 0, 1 }, // tsense0_critical_intr
package(){ 3, 541, 0, 1 }, // tsense1_critical_intr
// // Preferable wake-capable interrupts (in the event Tsens use them for debugging min/max shutdowns)
package(){ 4, 536, 0, 1 }, // tsense0_tsense_max_min_int
package(){ 5, 537, 0, 1 }, // tsense1_tsense_max_min_int
// USB wakeup interrupts
// to be used in Host mode ( WD ) for device detection and
// wake up from suspend in SS and HS modes on Xo shutdown + Cx collapse.
package(){ 6, 518, 0, 1 }, // qmp_usb3_lfps_rxterm_irq USB SS Primary
package(){ 7, 519, 0, 1 }, // qmp_usb3_lfps_rxterm_irq USB SS Secondary
package(){ 8, 520, 0, 1 , 8}, // eud_p0_dmse_int_mx
package(){ 9, 521, 0, 1 , 8}, // eud_p0_dpse_int_mx
package(){10, 522, 0, 1 , 8}, // eud_p1_dmse_int_mx
package(){11, 523, 0, 1 , 8}, // eud_p1_dpse_int_mx
// PMIC wakeup interrupt --
// (Power Key button)
package(){12, 513, 0, 4 }, // ee0_apps_hlos_spmi_periph_irq
}
},
})
}

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Scope(\_SB.PEP0)
{
Method(LLMH){
return(NLMH)
}
Name( NLMH, package(){
package(){
"PEP_LMH_CFG",
package(){
0, //SILVER_CLUSTER
0, // 0 = SIMPLE_STEP_ALGO, 1 = TOCKEN_BUCKET_ALGO
2995200, //Domain Max frequency for Silver cluster
3330, //ARM Threshold in 10s K
3675, //LOW Threshold in 10s K
3680, //HIGH Threshold in 10s K
},
package(){
1, //GOLD_CLUSTER
0, // 0 = SIMPLE_STEP_ALGO, 1 = TOCKEN_BUCKET_ALGO
2995200, //Domain Max frequency for Gold cluster
3330, //ARM Threshold in 10s K
3675, //LOW Threshold in 10s K
3680, //HIGH Threshold in 10s K
},
},
})
}

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//===========================================================================
// <pep_resources.asl>
// DESCRIPTION
// This file contans the resources needed by pep drivers.
//
//===========================================================================
Scope(\_SB_.PEP0)
{
// PEP
Method(PPMD)
{
Return(PPCC)
}
Name(PPCC,
Package ()
{
// PEP Proxy Driver
Package(){
"DEVICE",
"\\_SB.PRXY",
Package(){
"COMPONENT",
0,
// F-State placeholders
Package(){ "FSTATE", 0, },
},
},
// PEP Stats Driver
Package(){
"DEVICE",
"\\_SB.STAT",
Package(){
"COMPONENT",
0,
// F-State placeholders
Package(){ "FSTATE", 0, },
},
},
// Claim GPIO Device to enable wake up from XO etc
Package()
{
//GPIO
"DEVICE",
0x81, // TransferrableIOIrq
"\\_SB.GIO0",
Package()
{
"COMPONENT",
0,
// F-State placeholders
Package() {"FSTATE",0,},
},
Package()
{
"COMPONENT",
1,
// F-State placeholders
Package() {"FSTATE",0},
},
},
})
// System Default Resources Packages
Name(SDFR,
Package()
{
//System Resources
Package(){
"DEVICE",
"\\_SB.SDFR",
Package(){
"COMPONENT",
0,
Package(){
"FSTATE",
0,
// Place any resources required for nominal operation
// SDF will choose either Nominal or SVS at boot
},
Package(){
"FSTATE",
1,
// Place any resources required for SVS operation
// SDF will choose either Nominal or SVS at boot
},
Package(){
"FSTATE",
2,
// Common SDF resources; will be set when PEP finishes
// parsing standard ACPI resources
},
Package(){
"FSTATE",
3,
//Low Power Pad Settings
},
},
},
})
}

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//Cx & Mx supported vlvl
//RAIL_VOLTAGE_LEVEL_OFF = 0,
//RAIL_VOLTAGE_LEVEL_RETENTION = 16,
//RAIL_VOLTAGE_LEVEL_SVS_LOW = 64,
//RAIL_VOLTAGE_LEVEL_SVS = 128,
//RAIL_VOLTAGE_LEVEL_SVS_HIGH = 192,
//RAIL_VOLTAGE_LEVEL_NOMINAL = 256,
//RAIL_VOLTAGE_LEVEL_NOMINAL_HIGH = 320,
//RAIL_VOLTAGE_LEVEL_TURBO = 384,
//RAIL_VOLTAGE_LEVEL_TURBO_L1 = 384,
// XO supported vlvl
//XO_LEVEL_CRYSTAL_OFF = 0x0,
//XO_LEVEL_PMIC_BUFFER_OFF = 0x20,
//XO_LEVEL_SOC_BUFFER_OFF = 0x50,
//XO_LEVEL_ON = 0x80,
Scope(\_SB.PEP0)
{
Method(LVDD){
return(NVDD)
}
Name( NVDD, package(){
package(){
"/arc/client/rail_cx", // Resource name
"RAIL_VOLTAGE_LEVEL_NOMINAL", // Initial value
},
package(){
"/arc/client/display/rail_cx", // Resource name
"RAIL_VOLTAGE_LEVEL_OFF", // Initial value
},
package(){
"/arc/client/rail_mx", // Resource name
"RAIL_VOLTAGE_LEVEL_NOMINAL", // Initial value
},
package(){
"/arc/client/display/rail_mx", // Resource name
"RAIL_VOLTAGE_LEVEL_OFF", // Initial value
},
package(){
"/arc/client/rail_xo", // Resource name
"XO_LEVEL_ON", // Initial value
},
package(){
"/arc/client/display/rail_xo", // Resource name
"XO_LEVEL_CRYSTAL_OFF", // Initial value
},
})
}

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//
// This file contains common Power Management IC (PMIC) ACPI device definitions
//
//
//
//PMIC KMDF
//
Device (PMIC)
{
Name (_DEP, Package(0x1)
{
\_SB_.SPMI
})
Name (_HID, "QCOM0266")
Name (_CID, "PNP0CA3")
Method (PMCF) {
Name (CFG0,
Package()
{
// PMIC Info
3, // Number of PMICs, must match the number of info packages
Package()
{
0,
1,
},
Package()
{
2,
3,
},
Package()
{
4,
5,
},
})
Return (CFG0)
}
}
//
// PMIC GPIO PM8998
//
Device (PM01)
{
Name (_HID, "QCOM0269")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
Name (_DEP,
Package(0x1) {
\_SB_.PMIC
}
)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF,
ResourceTemplate() {
// QGIC Interrupt Resource
// Register for SPMI Interrupt 513
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , ,) {513}
}
)
Return (RBUF)
}
// _DSM method to mark PM01's ActiveBoth interrupts
Method(_DSM, 0x4, NotSerialized) {
// DSM UUID
switch(ToBuffer(Arg0))
{
// ACPI DSM UUID for GPIO
case(ToUUID("4F248F40-D5E2-499F-834C-27758EA1CD3F"))
{
// DSM Function
switch(ToInteger(Arg2))
{
// Function 0: Return supported functions, based on revision
case(0)
{
// revision 0: function 0 & 1 are supported.
return (Buffer() {0x3})
}
// Function 1: For emulated ActiveBoth controllers, returns
// a package of controller-relative pin numbers.
// Each corresponding pin will have an initial
// polarity of ActiveHigh.
case(1)
{
// Marks pins KPDPWR_ON, RESIN_ON to be ActiveHigh.
Return (Package() {0, 1})
}
default
{
// Functions 2+: not supported
}
}
}
default
{
// No other GUIDs supported
Return(Buffer(One) { 0x00 })
}
}
}
}
//
// PMIC Apps Driver
//
Device (PMAP)
{
Name (_HID, "QCOM0268")
Alias(\_SB.PSUB, _SUB)
Name(_DEP, Package(0x3) {
\_SB_.PMIC,
\_SB.ABD,
\_SB.SCM0
})
//PMAP is dependent on ABD for operation region access
// Get pseudo SPB controller port which is used to handle the ACPI operation region access
Method(GEPT)
{
Name(BUFF, Buffer(4){})
CreateByteField(BUFF, 0x00, STAT)
CreateWordField(BUFF, 0x02, DATA)
Store(0x2, DATA)
Return(DATA)
}
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
//Interrupts must be in this order to match PmicAppsDevice.c OnPrepareHardware
//LAB Vreg OK interrupt
GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {448} // 0xEF0 - PM_INT__LAB__VREG_OK
//WLED SC fault interrupt
//GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {418} // 0xEC2 - PM_INT__WLED_CTRL__SC_FAULT
//IBB SC fault interrupt
//GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {434} // 0xEE2 - PM_INT__IBB__SC_ERROR
//LAB SC fault interrupt
//GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01", , , ,) {449} // 0xEF1 - PM_INT__LAB__SC_ERROR
})
Return (RBUF)
}
}
//
// PMIC Apps Real Time Clock (RTC)
//
Device (PRTC)
{
Name(_HID, "ACPI000E")
Name (_DEP,
Package(0x1) {
\_SB_.PMAP
}
)
//Get the capabilities of the time and alarm device
Method(_GCP)
{
Return (0x04) //Bit 2 set indicating Get Set Supported
}
Field(\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve)
{
Connection(I2CSerialBus( 0x0002,,0x0,, "\\_SB.ABD",,,,)),
AccessAs(BufferAcc, AttribRawBytes(24)),
FLD0,192
}
Method(_GRT) // Get the Real time
{
Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16)
CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time
CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field
CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field
Store(FLD0, BUFF)
Return(TME1)
}
Method(_SRT, 1) // Set the Real time
{
Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16)
CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field
CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time
CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field
CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field
Store(0x0, ACT1)
Store(Arg0, TME1)
Store(0x0, ACW1)
Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port
// Return the status
If(LNotEqual(STAT,0x00)) {
Return(1) // Call to OpRegion failed
}
Return(0) //success
}
//
//Code to enable RTC AC/DC wake timers
//
// Method(_TIV) // Get the AC TIMER Field
// {
// Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16)
// CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time
// CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field
// CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field
// Store(FLD0, BUFF)
// Return(ACT1)
// }
// Method(_GWS) // Get the AC TIMER Wake Status
// {
// Name(BUFF, Buffer(26){}) // 18 bytes STAT(1), SIZE(1), Time(16)
// CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time
// CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field
// CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field
// Store(FLD0, BUFF)
// Return(ACW1)
// }
// Method(_STV, 2) // Set alarm timer value
// {
// If(LEqual(Arg0,0x00)) {
// Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16)
// CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field
// CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time
// CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field
// CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field
// Store(Arg1, ACT1)
// Store(0x0, TME1)
// Store(0x0, ACW1)
// Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port
// // Return the status
// If(LNotEqual(STAT,0x00)) {
// Return(1) // Call to OpRegion failed
// }
// Return(0) //success
// }
// Return(1)
// }
// Method(_CWS, 1) // Clear wake alarm status
// {
// Name(BUFF, Buffer(50){}) // 18 bytes STAT(1), SIZE(1), Time(16)
// CreateByteField(BUFF, 0x0, STAT) // Create the STAT Field
// CreateField(BUFF, 16, 128, TME1) // Create the TIME Field - For the time
// CreateField(BUFF, 144, 32, ACT1) // Create the AC TIMER Field
// CreateField(BUFF, 176, 32, ACW1) // Create the AC Wake Alarm Status Field
// Store(0x0, ACT1)
// Store(0x0, TME1)
// Store(Arg0, ACW1)
// Store(Store(BUFF, FLD0),BUFF) // Write the transaction to the Psuedo I2C Port
// // Return the status
// If(LNotEqual(STAT,0x00)) {
// Return(1) // Call to OpRegion failed
// }
// Return(0) //success
// }
}

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//
// Qualcomm DIAG Bridge
//
Device (QCDB)
{
Name (_HID, "QCOM0298")
Alias(\_SB.PSUB, _SUB)
}

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//===========================================================================
// <qdss_resources.asl>
// DESCRIPTION
// This file contans the power management resources needed by qdss driver.
//
//===========================================================================
//===========================================================================
// Description & Possible use cases for Qdss's p-state implementation
// Qdss employs pstate-sets to robustly configure clock and tlmm registers
// pstate-set 0 has pstates for clock frequencies
// pstate-set 1 has pstates for managing tlmm registers for tpiu operation
//========================================================
// Sinks p-states allowed
//--------------------------------------------------------
// non-TPIU P{0,0}
// P{0,1}
// P{0,2}
// P{0,3}
// TPIU P{0,0} AND (P{1,1} OR P{1,3})
// P{0,1} AND (P{1,0} OR P{1,2})
// P{0,2} AND (P{1,0} OR P{1,2})
// P{0,3} AND (P{1,0} OR P{1,2})
//
// Description of pstate-sets and corresponding p-states :
// pstate-set-0 is the set with allowed qdss clock frequencies
// under set-0 each p-state holds the following meaning:
// pstate-0 CLOCK OFF (0 Hz)
// pstate-1 SVS CLOCK FREQUENCY (depends on the voltage; ranges 150 to 300 MHz)
// pstate-2 HIGH CLOCK FREQUENCY (300 MHz)
// pstate-3 LOW CLOCK FREQUENCY (150 MHz)
//
// under set-1 each p-state hold the following meaning:
// pstate-0 sets SET-B TLMM registers to make TPIU operational
// pstate-1 clears SET-B TLMM registers to make TPIU operational
// pstate-2 sets SD TLMM registers to make TPIU operational
// pstate-3 clears SD TLMM registers to make TPIU operational
//===========================================================================
Scope(\_SB.PEP0)
{
Method(QDMD){
Return(QDSC)
}
Name(QDSC,
Package()
{
Package()
{
"DEVICE",
"\\_SB.QDSS",
Package()
{
"COMPONENT",
0x0,
Package()
{
"FSTATE",
0x0,
},
Package()
{
"FSTATE",
0x1,
Package() {"PSTATE_ADJUST", Package() {0, 0},},
},
Package()
{
"PSTATE_SET",
0x0,
// p-state for turning off the clock
Package()
{
"PSTATE",
0x0,
package() {"NPARESOURCE", package() {1, "/clk/qdss", 0},},
},
// p-state for setting the clock to SVS mode (depends on the voltage)
Package()
{
"PSTATE",
0x1,
package() {"NPARESOURCE", package() {1, "/clk/qdss", 1},},
},
// p-state for high speed clock
Package()
{
"PSTATE",
0x2,
package() {"NPARESOURCE", package() {1, "/clk/qdss", 2},},
},
// p-state for low speed mode
Package()
{
"PSTATE",
0x3,
package() {"NPARESOURCE", package() {1, "/clk/qdss", 3},},
},
},
Package()
{
"PSTATE_SET",
0x1,
// p-state for enabling SET-B TPIU TLMM
// TODO: clean-up TPIU code and deprecate this functionality. TPIU is no longer used
package()
{
"PSTATE",
0x0,
},
// p-state for disabling SET-B TPIU TLMM
package()
{
"PSTATE",
0x1,
},
// p-state for enabling TPIU SD
package()
{
"PSTATE",
0x2,
},
// p-state for disabling TPIU SD
package()
{
"PSTATE",
0x3,
},
},
// pstate-set for enabling the HWEVT Mux clocks TO DO: requires hw event xml
// for subsystems that are under Qdss address map
// *the convention followed in the code is for a mux enable state is
// immediately followed by disable state.*
// e.g. as in 0 is to enable mmss clock and 0+1 is to disable mmss clock
// TODO: confirm with clkrgm team for "/clk/qdss" npa node support.
Package()
{
"PSTATE_SET",
0x2,
// p-state for setting the /clk/qdss
package()
{
"PSTATE",
0x0,
package() {"NPARESOURCE", package() {1, "/clk/qdss", 1},},
},
// p-state for shutting of the qdss clock
package()
{
"PSTATE",
0x1,
package() {"NPARESOURCE", package() {1, "/clk/qdss", 0},},
},
},
// logger integrator GPIO
Package()
{
"PSTATE_SET",
0x3,
// p-state for setting the /clk/qdss
package()
{
"PSTATE",
0x0,
package() {"TLMMPORT", package() {0x33000, 0x07FF, 0x01C8},}, // TLMM_GPIO_CFG51, qdss_cti_trig0_out_mira, See http://ipcatalog.qualcomm.com/chipio/tlmm/chip/53/map/170 TLMM base address: TLMM_NORTH, see http://ipcatalog.qualcomm.com/swi/module/1279315#TLMM_GPIO_CFG51
},
},
},
},
})
}

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// This file contains the QUPv3 ACPI device definitions.
// GPI is the interface used by buses drivers for different peripherals.
//
//
// Device Map:
// QGPI
//
// List of Devices
Device (QGP0)
{
// Indicates dependency on PEP
//Name (_DEP, Package () { \_SB_.PEP0 })
Name (_HID, "QCOM02F4")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized)
{
Name (RBUF, ResourceTemplate ()
{
// QUPV3_0 address space
Memory32Fixed (ReadWrite, 0x00804000, 0x50000)
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {276} // GPII-ID 0x0
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {277} // GPII-ID 0x1
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {278} // GPII-ID 0x2
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {279} // GPII-ID 0x3
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {280} // GPII-ID 0x4
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {281} // GPII-ID 0x5
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {282} // GPII-ID 0x6
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {283} // GPII-ID 0x7
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {284} // GPII-ID 0x8
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {285} // GPII-ID 0x9
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {286} // GPII-ID 0xA
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {287} // GPII-ID 0xB
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {288} // GPII-ID 0xC
})
Return (RBUF)
}
Method (GPII, 0x0, Serialized)
{
Return( Package()
{
//Package ()
//{
// 0x00, // QUPV3 Instance
// 0x00, // GPII ID
// 0x114 // Interrupt
//},
//Package ()
//{
// 0x00,
// 0x01,
// 0x115
//},
//Package ()
//{
// 0x00,
// 0x02,
// 0x116
//},
//Package ()
//{
// 0x00,
// 0x03,
// 0x117
//},
//Package ()
//{
// 0x00,
// 0x04,
// 0x118
//},
Package ()
{
0x00,
0x05,
0x119
}
//Package ()
//{
// 0x00,
// 0x06,
// 0x11A
//},
//Package ()
//{
// 0x00,
// 0x07,
// 0x11B
//},
//Package ()
//{
// 0x00,
// 0x08,
// 0x11C
//},
//Package ()
//{
// 0x00,
// 0x09,
// 0x11D
//},
//Package ()
//{
// 0x00,
// 0x0A,
// 0x11E
//},
//Package ()
//{
// 0x00,
// 0x0B,
// 0x11F
//},
//Package ()
//{
// 0x00,
// 0x0C,
// 0x120
//}
})
}
}
Device (QGP1)
{
// Indicates dependency on PEP
//Name (_DEP, Package () { \_SB_.PEP0 })
Name (_HID, "QCOM02F4")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
Name (_CCA, 0)
Method (_CRS, 0x0, Serialized)
{
Name (RBUF, ResourceTemplate ()
{
// QUPV3_1 address space
Memory32Fixed (ReadWrite, 0x00A04000, 0x50000)
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {311} // GPII-ID : 0x0
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {312} // GPII-ID : 0x1
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {313} // GPII-ID : 0x2
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {314} // GPII-ID : 0x3
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {315} // GPII-ID : 0x4
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {316} // GPII-ID : 0x5
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {325} // GPII-ID : 0x6
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {326} // GPII-ID : 0x7
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {327} // GPII-ID : 0x8
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {328} // GPII-ID : 0x9
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {329} // GPII-ID : 0xA
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {330} // GPII-ID : 0xB
//Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {331} // GPII-ID : 0xC
})
Return (RBUF)
}
Method (GPII, 0x0, Serialized)
{
Return( Package()
{
//Package ()
//{
// 0x01,
// 0x00,
// 0x137
//},
Package ()
{
0x01,
0x01,
0x138
},
//Package ()
//{
// 0x01,
// 0x02,
// 0x139
//},
Package ()
{
0x01,
0x03,
0x13A
}
//Package ()
//{
// 0x01,
// 0x04,
// 0x13B
//},
//Package ()
//{
// 0x01,
// 0x05,
// 0x13C
//},
//Package ()
//{
// 0x01,
// 0x06,
// 0x145
//},
//Package ()
//{
// 0x01,
// 0x07,
// 0x146
//},
//Package ()
//{
// 0x01,
// 0x08,
// 0x147
//},
//Package ()
//{
// 0x01,
// 0x09,
// 0x148
//},
//Package ()
//{
// 0x01,
// 0x0A,
// 0x149
//},
//Package ()
//{
// 0x01,
// 0x0B,
// 0x14A
//},
//Package ()
//{
// 0x01,
// 0x0C,
// 0x14B
//}
})
}
}

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Device (QWPP)
{
Name (_DEP, Package () { \_SB_.PEP0 })
Name (_HID, "QCOM02E4")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Method(_STA, 0)
{
return (0xB) // Loaded, but hidden
}
Method (_CRS, 0x0, NotSerialized)
{
Return
(
ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x1100000, 0x1EE000) // The CABO address space
Memory32Fixed (ReadWrite, 0x1380000, 0x320000) // MEMNOC address space
}
)
}
}

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//
// RemoteFS
//
Device (RFS0)
{
Name (_DEP, Package(0x2)
{
\_SB_.IPC0,
\_SB_.UFS0
})
Name (_HID, "QCOM0235")
Alias(\_SB.PSUB, _SUB)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// RemoteFS Shared Memory
Memory32Fixed (ReadWrite, 0x88888888, 0x99999999, RMTS)
// RFSA MPSS Shared Memory
Memory32Fixed (ReadWrite, 0x11111111, 0x22222222, RFSM)
// RFSA ADSP Shared Memory
Memory32Fixed (ReadWrite, 0x33333333, 0x44444444, RFSA)
})
CreateDWordField (RBUF, RMTS._BAS, RMTA)
CreateDWordField (RBUF, RMTS._LEN, RMTL)
CreateDWordField (RBUF, RFSM._BAS, RFMA)
CreateDWordField (RBUF, RFSM._LEN, RFML)
CreateDWordField (RBUF, RFSA._BAS, RFAA)
CreateDWordField (RBUF, RFSA._LEN, RFAL)
Store(\_SB_.RMTB, RMTA)
Store(\_SB_.RMTX, RMTL)
Store(\_SB_.RFMB, RFMA)
Store(\_SB_.RFMS, RFML)
Store(\_SB_.RFAB, RFAA)
Store(\_SB_.RFAS, RFAL)
Return (RBUF)
}
Method (_STA)
{
Return(0xB)
}
}

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//
// SARMGR Device
//
Device (SARM)
{
Name (_HID, "QCOM0301")
Alias(\_SB.PSUB, _SUB)
//Method(_HRV) { Return(_BID) }
}

40
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//
// Storage - SD card
//
Device (SDC2)
{
Name (_DEP, Package(0x2) {
\_SB_.PEP0,
\_SB_.GIO0
})
Name (_HID, "QCOM2466")
Alias(\_SB.PSUB, _SUB)
Name (_CID, "ACPI\QCOM2466")
Name (_UID, 1)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// SDCC2 register address space
Memory32Fixed (ReadWrite, 0x8804000, 0x00001000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {236}
// Card detect GPIO
GpioInt(Edge, ActiveBoth, SharedAndWake, PullUp, 30000, "\\_SB.GIO0", ,) {192}
Gpioio(Shared, PullUp, 0, 0, , "\\_SB.GIO0", ,) {126}
})
Return (RBUF)
}
Method(_DIS)
{
// Place holder to allow disable
}
Method (_STA)
{
Return(0xF)
}
}

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//
// SLIMbus controller
//
Device (SLM1)
{
Name (_ADR, 0)
Name (_CCA, 0)
Alias(\_SB.PSUB, _SUB)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// SLIMbus register address space
Memory32Fixed (ReadWrite, 0x171C0000, 0x0002c000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {195}
})
Return (RBUF)
}
Method (CHLD)
{
Return (Package()
{
"SLM1\\QCOM023F",
})
}
Include("audio_bus.asl")
}
Device (SLM2)
{
Name (_ADR, 1)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// SLIMbus register address space
Memory32Fixed (ReadWrite, 0x17240000, 0x0002c000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {323}
})
Return (RBUF)
}
}

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//
//SPMI driver.
//
Device(SPMI)
{
Name(_HID, "QCOM0216")
Alias(\_SB.PSUB, _SUB)
Name (_CID, "PNP0CA2")
Name(_UID, One)
Name(_CCA, 0)
Method(_CRS, 0x0, NotSerialized)
{
Name(RBUF, ResourceTemplate ()
{
Memory32Fixed(ReadWrite, 0x0C400000, 0x02800000)
})
Return(RBUF)
}
Include("../common/spmi_conf.asl")
}

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//
//SPMI driver configuration.
//
Method(CONF)
{
Name(XBUF,
Buffer () {
0x00, // uThisOwnerNumber
0x01, // polling mode
0x01, // reserved channel enable
0x01, 0xFF, // reserved channel number (upper byte, lower byte)
0x00, // dynamic channel mode enable
0x02, 0x00, // number of channels (upper byte, lower byte)
0x0A, // number of port priorities
0x07, // number of PVC ports
0x04, // number of PVC port PPIDs
0x07, // number of masters
0x01, 0xFF, // number of mapping table entries (upper byte, lower byte)
0x10, // number of PIC accumulated status registers
0x01, 0x00, // number of Program RAM REGS (upper byte, lower byte)
0x01, // number of SPMI bus controllers
0x0C, 0x40, 0x00, 0x00, // physical address 0 (byte3, byte2, byte1, byte0)
0x02, 0x80, 0x00, 0x00 // physical size 0 (byte3, byte2, byte1, byte0)
}
)
Return(XBUF)
}

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//===========================================================================
// <subsys_resources.asl>
// DESCRIPTION
// This file contans the resources needed by subsystem drivers.
//
//===========================================================================
Scope(\_SB_.PEP0)
{
// Subsystem Drivers
Method(SPMD)
{
Return(SPCC)
}
Name(SPCC,
Package ()
{
Package()
{
"DEVICE",
"\\_SB.AMSS",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"PSTATE",
0x0, // P0 state
// turning on MSS specific clocks which were earlier not power managed
// gcc_mss_gpll0_div_clk_src enabled using register in subsys amss code
// Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE
// Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST
// -----------------------------------------------------------------------------------------------------
// CLOCK Clock Name Action Freq (Hz) MatchType
// -----------------------------------------------------------------------------------------------------
Package() { "CLOCK", Package() { "gcc_boot_rom_ahb_clk", 1,}},
Package() { "CLOCK", Package() { "gcc_mss_cfg_ahb_clk", 1,}},
Package() { "CLOCK", Package() { "gcc_mss_q6_memnoc_axi_clk", 1,}},
Package() { "CLOCK", Package() { "gcc_mss_snoc_axi_clk", 1,}},
Package() { "CLOCK", Package() { "gcc_mss_mfab_axis_clk", 1,}},
Package() { "CLOCK", Package() { "gcc_prng_ahb_clk", 1,}},
Package() { "CLOCK", Package() { "gcc_mss_axis2_clk", 1,}},
// MSS HPG says that step 1 is to turn on the power rails
// to nominal settings. The HPG calls out the following:
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_SMPS2_C", // Voltage Regulator ID - PPP_RESOURCE_ID_SMPS2_C S2CPM8005 See http://ipcatalog.qualcomm.com/pmic/grids/73
2, // Voltage Regulator Type - 2 - SMPS
752000, // Voltage - 0.752 V
1, // Software Enable - 1 - Enable
7, // Software Power Mode - 0 - Normal
0, // Head Room - 0
},
},
Package()
{
"NPARESOURCE",
Package()
{
1, //Required Resource - 1 or Non Required Resource - 0
"/arc/client/rail_cx",
384, //vlvl Vote - RAIL_VOLTAGE_LEVEL_TUR
},
},
Package()
{
"NPARESOURCE",
Package()
{
1, //Required Resource - 1 or Non Required Resource - 0
"/arc/client/rail_mx",
384, //vlvl Vote - RAIL_VOLTAGE_LEVEL_TUR
},
},
Package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_IPA_CORE", // Master
"ICBID_SLAVE_IPA_CORE", // Slave
37400, // IB= KHz ( map 37500 KHz needs to mapped to IB value )
0, // AB
"HLOS_DRV", // Optional: DRV Id
},
},
},
Package()
{
"PSTATE",
1,
// removing apps vote for MSS specific votable clocks
// gcc_mss_gpll0_div_clk_src disable using register in subsys amss code before we go to P1 state
// Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE
// Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST
// -----------------------------------------------------------------------------------------------------
// CLOCK Clock Name Action Freq (Hz) MatchType
// -----------------------------------------------------------------------------------------------------
//Package() { "CLOCK", Package() { "gcc_boot_rom_ahb_clk", 2,}},
Package() { "CLOCK", Package() { "gcc_prng_ahb_clk", 2,}},
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_SMPS2_C", // Voltage Regulator ID - PPP_RESOURCE_ID_SMPS2_C
2, // Voltage Regulator Type - 2 - SMPS
0, // Voltage - NA
0, // Software Disable - 0 - Disable
0, // Software Power Mode - 0 - NA
0, // Head Room - 0
},
},
Package()
{
"NPARESOURCE",
Package()
{
1, //Required Resource - 1 or Non Required Resource - 0
"/arc/client/rail_cx",
0, //vlvl Vote
},
},
Package()
{
"NPARESOURCE",
Package()
{
1, //Required Resource - 1 or Non Required Resource - 0
"/arc/client/rail_mx",
0, //vlvl Vote
},
},
Package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_IPA_CORE", // Master
"ICBID_SLAVE_IPA_CORE", // Slave
0, // IB= KHz ( map 37500 KHz needs to mapped to IB value )
0, // AB
"HLOS_DRV", // Optional: DRV Id
},
},
},
Package()
{
"PSTATE",
2,
// removing apps vote for MSS specific votable clocks
// gcc_mss_gpll0_div_clk_src disable using register in subsys amss code before we go to P1 state
// Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE
// Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST
// -----------------------------------------------------------------------------------------------------
// CLOCK Clock Name Action Freq (Hz) MatchType
// -----------------------------------------------------------------------------------------------------
Package() { "CLOCK", Package() { "gcc_boot_rom_ahb_clk", 2,}},
Package() { "CLOCK", Package() { "gcc_prng_ahb_clk", 2,}},
Package()
{
"PMICVREGVOTE",
Package()
{
"PPP_RESOURCE_ID_SMPS2_C", // Voltage Regulator ID - PPP_RESOURCE_ID_SMPS2_C
2, // Voltage Regulator Type - 2 - SMPS
0, // Voltage - NA
0, // Software Disable - 0 - Disable
0, // Software Power Mode - 0 - NA
0, // Head Room - 0
},
},
},
},
Package()
{
"DSTATE",
0x0, // D0 state
},
Package()
{
"DSTATE",
0x3, // D3 state
}
},
/////////////////////////////////////////////////////////////////////////////////////
// ADSP device
Package()
{
"DEVICE",
"\\_SB.ADSP",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"PSTATE",
0x0, // P0 state
},
Package(){
"PSTATE",
1, // P1 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
},
Package()
{
"DSTATE",
0x3, // D3 state
},
},
/////////////////////////////////////////////////////////////////////////////////////
// SCSS (sensors subsystem bus) device
Package()
{
"DEVICE",
"\\_SB.SCSS",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"PSTATE",
0x0,
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LDO27_A", // VREG ID
1, // Voltage Regulator type - LDO,
752000, // Voltage is in micro volts - (0.752V = Nominal L27A, PM845. See http://ipcatalog.qualcomm.com/pmic/grids/chip/53/grid/98)
1, // force enable from software - enable
7, // power mode - Normal Power Mode (See go/pepuserguide for translation from mode to value)
0, // head room voltage
},
},
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LDO4_A", // VREG ID
1, // Voltage Regulator type - LDO
800000, // Voltage is in micro volts - (0.8V = Nominal, L4A PM845. See http://ipcatalog.qualcomm.com/pmic/grids/chip/53/grid/98)
1, // force enable from software - enable
7, // power mode - Normal Power Mode (See go/pepuserguide for translation from mode to value)
0, // head room voltage
},
},
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LVS2_A",
4, // TYPE of VREG - LVS
1800000, // 1.8V LVS2APM845 See http://ipcatalog.qualcomm.com/pmic/grids/73
1, // Force enable from s/w
},
},
Package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_APPSS_PROC", // Master
"ICBID_SLAVE_CLK_CTL", // Slave
1, // IB
1, // AB
},
},
},
Package()
{
"PSTATE",
0x1,
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LDO27_A", // VREG ID
1, // Voltage Regulator type - LDO
576000, // Voltage is in micro volts - (0.576V = MinSVS L27A, PM845. See http://ipcatalog.qualcomm.com/hsr/213#)
1, // force enable from software
5, // power mode - Low Power Mode (See go/pepuserguide for translation from mode to value)
0, // head room voltage
},
},
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LDO4_A", // VREG ID
1, // Voltage Regulator type - LDO
800000, // Voltage is in micro volts - (0.8V = Nominal (Lowest supported) L4A, PM845. See http://ipcatalog.qualcomm.com/hsr/213#)
1, // force enable from software
5, // power mode - Low Power Mode (See go/pepuserguide for translation from mode to value)
0, // head room voltage
},
},
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LVS2_A",
4, // TYPE of VREG - LVS
0, // 0.0V
0, // Force enable from s/w
},
},
Package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_APPSS_PROC", // Master
"ICBID_SLAVE_CLK_CTL", // Slave
0, // IB
0, // AB
},
},
},
Package(){
"PSTATE",
2,
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LDO27_A", // VREG ID
1, // Voltage Regulator type - LDO
0, // Voltage is in micro volts - NA
0, // force enable from software - disable
0, // power mode - NA
0, // head room voltage
},
},
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LDO4_A", // VREG ID
1, // Voltage Regulator type - LDO
0, // Voltage is in micro volts - NA
0, // force enable from software - disable
0, // power mode - NA
0, // head room voltage
},
},
Package()
{
"PMICVREGVOTE", // PMICVREGVOTE resource
Package()
{
"PPP_RESOURCE_ID_LVS2_A",
4, // TYPE of VREG - LVS
0, // 0.0V
0, // Force enable from s/w
},
},
Package()
{
"BUSARB",
Package()
{
3, // Req Type
"ICBID_MASTER_APPSS_PROC", // Master
"ICBID_SLAVE_CLK_CTL", // Slave
0, // IB
0, // AB
},
},
},
},
Package()
{
"DSTATE",
0x0, // D0 state
},
Package()
{
"DSTATE",
0x3, // D3 state
},
},
/////////////////////////////////////////////////////////////////////////////////////
// CDSP device
Package()
{
"DEVICE",
"\\_SB.CDSP",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"PSTATE",
0x0, // P0 state
},
Package(){
"PSTATE",
1,
},
},
Package()
{
"DSTATE",
0x0, // D0 state
},
Package()
{
"DSTATE",
0x3, // D3 state
},
},
/////////////////////////////////////////////////////////////////////////////////////
})
}

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//
// System Cache Driver
//
Device (LLC)
{
Name (_DEP, Package(0x1)
{
\_SB_.PEP0
})
Name (_HID, "QCOM02F8")
Alias(\_SB.PSUB, _SUB)
Method (_CRS, 0x0, NotSerialized)
{
Return (ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x01300000, 0x28000)
})
}
}

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//
// The Driver for Dynamically Changing Thresholds
// of Thermal Zones
//
Method(THTZ, 0x4, NotSerialized)
{
// Switch based on thermal zone number
Switch(toInteger(Arg0))
{
Case(1)
{
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ1.TPSV)
Notify(\_SB.TZ1, 0x81)
}
Return(\_SB.TZ1._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ1.TTSP)
Notify(\_SB.TZ1, 0x81)
}
Return(\_SB.TZ1._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ1.TTC1)
Notify(\_SB.TZ1, 0x81)
}
Return(\_SB.TZ1._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ1.TTC2)
Notify(\_SB.TZ1, 0x81)
}
Return(\_SB.TZ1._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(3)
{
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ3.TPSV)
Notify(\_SB.TZ3, 0x81)
}
Return(\_SB.TZ3._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ3.TTSP)
Notify(\_SB.TZ3, 0x81)
}
Return(\_SB.TZ3._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ3.TTC1)
Notify(\_SB.TZ3, 0x81)
}
Return(\_SB.TZ3._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ3.TTC2)
Notify(\_SB.TZ3, 0x81)
}
Return(\_SB.TZ3._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(20)
{
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ20.TPSV)
Notify(\_SB.TZ20, 0x81)
}
Return(\_SB.TZ20._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ20.TTSP)
Notify(\_SB.TZ20, 0x81)
}
Return(\_SB.TZ20._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ20.TTC1)
Notify(\_SB.TZ20, 0x81)
}
Return(\_SB.TZ20._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ20.TTC2)
Notify(\_SB.TZ20, 0x81)
}
Return(\_SB.TZ20._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(21)
{
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ21.TPSV)
Notify(\_SB.TZ21, 0x81)
}
Return(\_SB.TZ21._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ21.TTSP)
Notify(\_SB.TZ21, 0x81)
}
Return(\_SB.TZ21._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ21.TTC1)
Notify(\_SB.TZ21, 0x81)
}
Return(\_SB.TZ21._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ21.TTC2)
Notify(\_SB.TZ21, 0x81)
}
Return(\_SB.TZ21._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(33) {
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ33.TPSV)
Notify(\_SB.TZ33, 0x81)
}
Return(\_SB.TZ33._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ33.TTSP)
Notify(\_SB.TZ33, 0x81)
}
Return(\_SB.TZ33._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ33.TTC1)
Notify(\_SB.TZ33, 0x81)
}
Return(\_SB.TZ33._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ33.TTC2)
Notify(\_SB.TZ33, 0x81)
}
Return(\_SB.TZ33._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(36) {
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ36.TPSV)
Notify(\_SB.TZ36, 0x81)
}
Return(\_SB.TZ36._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ36.TTSP)
Notify(\_SB.TZ36, 0x81)
}
Return(\_SB.TZ36._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ36.TTC1)
Notify(\_SB.TZ36, 0x81)
}
Return(\_SB.TZ36._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ36.TTC2)
Notify(\_SB.TZ36, 0x81)
}
Return(\_SB.TZ36._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(37) {
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ37.TPSV)
Notify(\_SB.TZ37, 0x81)
}
Return(\_SB.TZ37._PSV)
}
Case(1)
{
If(Arg2)
{
Store(Arg1, \_SB.TZ37.TCRT)
Notify(\_SB.TZ37, 0x81)
}
Return(\_SB.TZ37._CRT)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ37.TTSP)
Notify(\_SB.TZ37, 0x81)
}
Return(\_SB.TZ37._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ37.TTC1)
Notify(\_SB.TZ37, 0x81)
}
Return(\_SB.TZ37._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ37.TTC2)
Notify(\_SB.TZ37, 0x81)
}
Return(\_SB.TZ37._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(38) {
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ38.TPSV)
Notify(\_SB.TZ38, 0x81)
}
Return(\_SB.TZ38._PSV)
}
Default
{
Return(0xFFFF)
}
}
}
Case(40) {
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ40.TPSV)
Notify(\_SB.TZ40, 0x81)
}
Return(\_SB.TZ40._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ40.TTSP)
Notify(\_SB.TZ40, 0x81)
}
Return(\_SB.TZ40._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ40.TTC1)
Notify(\_SB.TZ40, 0x81)
}
Return(\_SB.TZ40._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ40.TTC2)
Notify(\_SB.TZ40, 0x81)
}
Return(\_SB.TZ40._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(44) {
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ44.TPSV)
Notify(\_SB.TZ44, 0x81)
}
Return(\_SB.TZ44._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ44.TTSP)
Notify(\_SB.TZ44, 0x81)
}
Return(\_SB.TZ44._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ44.TTC1)
Notify(\_SB.TZ44, 0x81)
}
Return(\_SB.TZ44._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ44.TTC2)
Notify(\_SB.TZ44, 0x81)
}
Return(\_SB.TZ44._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(98)
{
Switch(toInteger(Arg3))
{
Case(0) {
If(Arg2)
{
Store(Arg1, \_SB.TZ98.TPSV)
Notify(\_SB.TZ98, 0x81)
}
Return(\_SB.TZ98._PSV)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ98.TTSP)
Notify(\_SB.TZ98, 0x81)
}
Return(\_SB.TZ98._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ98.TTC1)
Notify(\_SB.TZ98, 0x81)
}
Return(\_SB.TZ98._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ98.TTC2)
Notify(\_SB.TZ98, 0x81)
}
Return(\_SB.TZ98._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Case(99)
{
Switch(toInteger(Arg3))
{
Case(1) {
If(Arg2)
{
Store(Arg1, \_SB.TZ99.TCRT)
Notify(\_SB.TZ99, 0x81)
}
Return(\_SB.TZ99._CRT)
}
Case(2) {
If(Arg2)
{
Store(Arg1, \_SB.TZ99.TTSP)
Notify(\_SB.TZ99, 0x81)
}
Return(\_SB.TZ99._TSP)
}
Case(3) {
If(Arg2)
{
Store(Arg1, \_SB.TZ99.TTC1)
Notify(\_SB.TZ99, 0x81)
}
Return(\_SB.TZ99._TC1)
}
Case(4) {
If(Arg2)
{
Store(Arg1, \_SB.TZ99.TTC2)
Notify(\_SB.TZ99, 0x81)
}
Return(\_SB.TZ99._TC2)
}
Default
{
Return(0xFFFF)
}
}
}
Default {
Return(0xFFFF)
}
}
}

40
DSDT/common/ufs.asl Normal file
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// UFS Controller
Device (UFS0)
{
Name (_DEP, Package(0x1)
{
\_SB.PEP0,
})
Name (_HID, "QCOM24A5")
Alias(\_SB.PSUB, _SUB)
Name (_CID, "ACPI\QCOM24A5")
Name (_UID, 0)
Name (_CCA, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// UFS register address space
Memory32Fixed (ReadWrite, 0x1D84000, 0x14000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {297}
})
Return (RBUF)
}
// UFS Device
Device (DEV0)
{
// Memory Type
Method (_ADR)
{
Return (8)
}
// Non-removable
Method (_RMV)
{
Return (0)
}
}
}

49
DSDT/common/wcnss_bt.asl Normal file
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//
// WCN3990 Bluetooth
//
Device(BTH0)
{
Name(_HID, "QCOM02B5")
Alias(\_SB.PSUB, _SUB)
Name(_DEP, Package(0x3)
{
\_SB_.PEP0,
\_SB_.PMIC,
\_SB_.UAR7 // depends on UART ACPI definition
})
Name(_PRW, Package(0x2)
{
Zero,
Zero
})
Name(_S4W, 0x2)
Name(_S0W, 0x2)
Method(_CRS, 0x0, NotSerialized)
{
Name(PBUF, ResourceTemplate()
{
UARTSerialBus(
115200, // ConnectionSpeed
DataBitsEight, // BitsPerByte (defaults to DataBitsEight)
StopBitsOne, // StopBits (defaults to StopBitsOne)
0xC0, // LinesInUse
LittleEndian, // IsBigEndian (defaults to LittleEndian)
ParityTypeNone, // Parity (defaults to ParityTypeNone)
FlowControlHardware, // FlowControl (defaults to FlowControlNone)
0x20, // ReceiveBufferSize
0x20, // TransmitBufferSize
"\\_SB.UAR7", // depends on UART ACPI definition
0, // ResourceSourceIndex (defaults to 0)
ResourceConsumer, // ResourceUsage (defaults to ResourceConsumer)
, // DescriptorName
)
// GpioIo(Exclusive, PullDown, 0, 0, , "\\_SB.PM01", , , , ) {146} // 0x690 - PM_INT__PM1_GPIO19__GPIO_IN_STS
})
Return(PBUF)
}
Method(_STA, 0x0, NotSerialized)
{
Return(0xF)
}
}//End BTH0

384
DSDT/common/wcnss_resources.asl Normal file
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// PEP resources for WCNSS
Scope(\_SB_.PEP0)
{
//Wireless Connectivity Devices
Method(EWMD)
{
Return(WBRC)
}
Name(WBRC,
Package()
{
// PEP settings for Wlan iHelium
Package()
{
"DEVICE",
"\\_SB.AMSS.QWLN",
Package()
{
"COMPONENT",
0x0, // Component 0
Package()
{
"FSTATE",
0x0, // F0 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS7_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
1028000, // Voltage = 1.028 V
1, // Software Enable = Enable
6, // Software Power Mode = Auto
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO5_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
800000, // Voltage = 0.8 V
1, // Software Enable = Enable
7, // Software Power Mode = NPM
0, // Head Room
},
},
},
Package()
{
"DSTATE",
0x2, // D2 state
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO5_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS7_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
},
Package()
{
"DSTATE",
0x3, // D3 state
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO5_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS7_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
},
package()
{
"ABANDON_DSTATE",
2 // Abandon D state defined as D2
},
},
// END AMSS.QWLN
// PEP settings for Ltecoex device
Package()
{
"DEVICE",
"\\_SB.COEX",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
Package()
{
"PSTATE",
0x0, // P0 state
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS7_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
1028000, // Voltage = 1.028 V
1, // Software Enable = Enable
6, // Software Power Mode = Auto
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO5_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
800000, // Voltage = 0.8 V
1, // Software Enable = Enable
7, // Software Power Mode = NPM
0, // Head Room
},
},
},
Package()
{
"PSTATE",
0x1, // P1 state
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO5_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS7_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
},
},
},
// END _SB.COEX
// PEP settings for Bluetooth SOC
Package()
{
"DEVICE",
"\\_SB.BTH0",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS3_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
1352000, // Voltage = 1.352 V
1, // Software Enable = Enable
6, // Software Power Mode = Auto
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS5_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
2040000, // Voltage = 2.04 V
1, // Software Enable = Enable
6, // Software Power Mode = Auto
0, // Head Room
},
},
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO7_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
1800000, // Voltage = 1.8 V
1, // Software Enable = Enable
5, // Software Power Mode = LPM
0, // Head Room
},
},
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO17_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
1304000, // Voltage = 1.304 V
1, // Software Enable = Enable
5, // Software Power Mode = LPM
0, // Head Room
},
},
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO25_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
3104000, // Voltage = 3.104 V
1, // Software Enable = Enable
5, // Software Power Mode = LPM
0, // Head Room
},
},
},
Package()
{
"DSTATE",
0x3, // D3 state
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO7_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO17_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
Package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_LDO25_A", // Resource ID
1, // Voltage Regulator type 1 = LDO
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS3_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
package()
{
"PMICVREGVOTE",
package()
{
"PPP_RESOURCE_ID_SMPS5_A", // Resource ID
2, // Voltage Regulator type 2 = SMPS
0, // Voltage = 0 V
0, // Software Enable = Disable
5, // Software Power Mode = LPM
0, // Head Room
},
},
},
},
// END BTH0
// PEP settings for FM SOC
// END FM
}) // END WBRC
}

356
DSDT/common/win_mproc.asl Normal file
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//
// MPROC Drivers (PIL Driver and Subsystem Drivers)
//
//
// RPE Subsystem Notifier (RPEN)
//
Device (RPEN)
{
Name (_HID, "QCOM026D")
Alias(\_SB.PSUB, _SUB)
}
//
// Peripheral Image Loader (PIL) Driver
//
Device (PILC)
{
Name (_HID, "QCOM023B")
Method(PILX)
{
return (PILP)
}
Name(PILP,
Package()
{
// Methods needed for PIL bootup proceedure
// Drive will parse this list and call each
// method accordingly
"OPCA", // ACPO - ACPI Override for MBA load address
}
)
Method (ACPO)
{
Name(PKGG, Package()
{
Package ()
{
// Represents MBA subsystem
0x00000000, // Address
0x00000000, // Length
ToUUID ("BA58766D-ABF2-4402-88D7-90AB243F6C77")
}
})
// Copy ACPI globals for Address for this subsystem into above package for use in driver
Store (RMTB, Index(DeRefOf(Index (PKGG, 0)), 0))
Store (RMTX, Index(DeRefOf(Index (PKGG, 0)), 1))
Return (PKGG)
}
}
//
// RPE Crash Dump Injector (CDI) Driver
//
Device (CDI)
{
Name (_DEP, Package(0x2)
{
\_SB_.PILC,
\_SB_.RPEN
})
Name (_HID, "QCOM026C")
Alias(\_SB.PSUB, _SUB)
Method(_STA, 0)
{
return (0xf)
}
}
//
// SCSS device : loads sensors subsystem (SCSS) image
//
Device (SCSS)
{
Name (_DEP, Package(0x6)
{
\_SB_.PEP0,
\_SB_.PILC,
\_SB_.GLNK,
\_SB_.IPC0,
\_SB_.RPEN,
\_SB_.SSDD,
})
Name (_HID, "QCOM02BE")
Alias(\_SB.PSUB, _SUB)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// Inbound interrupt from SCSS dog bite
// See http://ipcatalog.qualcomm.com/irqs/chip/53/map/438
// q6ss_irq_out_apps_ipc[5 = SYS_apssQgicSPI[377] = 409
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {409}
})
Return (RBUF)
}
}
//
// ADSP Driver: load ADSP image
//
Device (ADSP)
{
Name (_DEP, Package(0x7)
{
\_SB_.PEP0,
\_SB_.PILC,
\_SB_.GLNK,
\_SB_.IPC0,
\_SB_.RPEN,
\_SB_.SSDD,
\_SB_.PDSR,
})
Name (_HID, "QCOM023D")
Alias(\_SB.PSUB, _SUB)
//
// WDIR - Watch Dog Interrupt Registers
//
Method (WDIR)
{
// See http://ipcatalog.qualcomm.com/swi/module/1280630
Return( Package ()
{
0x02, // Interrupt number - 2nd bit in Seventh register
0x17A0011C, // APSS_GICD_ISENABLERn (n represents Seventh register), register used to enable WDOG bite interrupt. 0x17A00000 + 0x00000100 (0x17A00100) + 0x4 * (n), n=7
0x17A0019C, // APSS_GICD_ICENABLERn (n represents Seventh register), register used to disable WDOG bite interrupt. 0x17A00000 + 0x00000180 (0x17A00180) + 0x4 * (n), n=7
0x17A0021C // APSS_GICD_ISPENDRn (n represents Seventh register), register used to clear pending WDOG bite interrupt. 0x17A00000 + 0x00000200 (0x17A00200) + 0x4 * (n), n=7
})
}
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// Inbound interrupt from LPASS dog bite
// See http://ipcatalog.qualcomm.com/irqs/chip/53/map/438
// u_lpass_lpass_irq_out_apcs[6] = SYS_apcsQgicSPI[162] = 194
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {194}
})
Return (RBUF)
}
Include("../common/slimbus.asl")
}
//
// AMSS Driver: Used for loading the modem binaries
//
Device (AMSS)
{
Name(_CCA, 0)
Name (_DEP, Package(0x9)
{
\_SB_.PEP0,
//\_SB_.PMIC,
\_SB_.IPA,
\_SB_.GLNK,
\_SB_.IPC0,
\_SB_.PILC,
\_SB_.RFS0,
\_SB_.RPEN,
\_SB_.SSDD,
\_SB_.PDSR,
})
Name (_HID, "QCOM023E")
Name (WLEN, 0x1) // Holds the enable/disable flag for WLAN
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// Inbound interrupt from Q6SW dog bite: refer http://ipcatalog.qualcomm.com/irqs/chip/53/map/438
// q6ss_wdog_exp_irq = SYS_apssQgicSPI[266] = 298
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {298}
})
Return (RBUF)
}
//
// WDIR - Watch Dog Interrupt Registers
//
Method (WDIR)
{
Return( Package ()
{
// See http://ipcatalog.qualcomm.com/swi/module/1280630
0x00, // Interrupt number - 0th bit in Fifteenth register
0x17A0013C, // APSS_GICD_ISENABLERn (n represents Fifteenth register), register used to enable WDOG bite interrupt.
0x17A001BC, // APSS_GICD_ICENABLERn (n represents Fifteenth register), register used to disable WDOG bite interrupt.
0x17A002BC // APSS_GICD_ICPENDRn (n represents Fifteenth register), register used to clear pending WDOG bite interrupt.
})
}
Method(_STA, 0)
{
return (0xf)
}
Include("wcnss_wlan.asl")
}
// QMI Service manager
//
Device (QSM)
{
Name (_HID, "QCOM02B9")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x4)
{
\_SB_.GLNK,
\_SB_.IPC0,
\_SB_.PILC,
\_SB_.RPEN
})
//
// DHMS client memory config
//
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// UEFI memory bank for DHMS clients
// Note: must match order of flagged for carveout packages below. See http://ipcatalog.qualcomm.com/memmap/chip/53/map/353#block=755839
Memory32Fixed(ReadWrite, 0x98f00000, 0x00600000)
})
Return (RBUF)
}
Method(_STA, 0)
{
return (0xf)
}
}
//
// Subsys Dependency Device
// Subsys devices that use QCCI should have an dependency on this
//
Device (SSDD)
{
Name (_HID, "QCOM02D1")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x2)
{
\_SB_.GLNK,
\_SB_.TFTP
})
}
//
// PDSR device
//
Device (PDSR)
{
Name (_HID, "QCOM02CE")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x3)
{
\_SB_.PEP0,
\_SB_.GLNK,
\_SB_.IPC0,
})
}
//
// CDSP Driver: load CDSP image
//
Device (CDSP)
{
Name (_DEP, Package(0x7)
{
\_SB_.PEP0,
\_SB_.PILC,
\_SB_.GLNK,
\_SB_.IPC0,
\_SB_.RPEN,
\_SB_.SSDD,
\_SB_.PDSR,
})
Name (_HID, "QCOM02F7")
Alias(\_SB.PSUB, _SUB)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// TURING QDSP6 WDOG Bite to APCS
// See http://ipcatalog.qualcomm.com/irqs/chip/53/map/480
// q6ss_wdog_exp_irq = SYS_apssQgicSPI[578] = 610
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {610}
})
Return (RBUF)
}
}
//
// TFTP Device
//
Device (TFTP)
{
Name (_HID, "QCOM02F6")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1)
{
\_SB_.IPC0,
})
}
// QcShutdownSvc Device
Device (SSVC)
{
Name (_DEP, Package(0x2)
{
\_SB_.IPC0, // IPC Router used by QMI, in turn depends on GLINK
\_SB_.QDIG // Qualcomm DIAG service
})
Name (_HID, "QCOM0302")
Alias(\_SB.PSUB, _SUB)
Name (_CID, "ACPI\QCOM0302")
Name (_UID, 0)
}
// Warning: Include these files after device scopes have been defined
// Include("cust_win_mproc.asl") // Customer specific data
// Include("plat_win_mproc.asl") // Platform specific data

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//
// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support.
//
DefinitionBlock("", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3)
{
Scope(\_SB_) {
Include("../common/addSub.asl")
Include("dsdt_common.asl")
Include("cust_dsdt.asl")
Include("usb.asl")
// Thermal Zone devices depend on PEP (included in dsdt_common). Please be CAREFUL on location
Include("cust_thermal_zones.asl")
//
// Hardware Notifications
//
Include("cust_hwn.asl")
//
// Touch
//
Include("cust_touch.asl")
//
// Buttons
//
Include("cust_arraybutton.asl")
//
// Data components
//
Include("../common/data.asl")
//
//Qualcomm Diagnostic Consumer Interface
//
Device (QDCI)
{
Name (_DEP, Package(0x1)
{
\_SB_.GLNK
})
Name (_HID, "QCOM0224")
Alias(\_SB.PSUB, _SUB)
}
//
// Bluetooth
//
Include("../common/wcnss_bt.asl")
//
// ADC driver
//
Include("adc.asl")
//Include("Bringup_Disable.asl")
}
}

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/*============================================================================
FILE: adc.asl
OVERVIEW: This file contains the board-specific configuration info for
ADC1 - qcadc analog-to-digital converter (ADC): ACPI device
definitions, common settings, etc.
DEPENDENCIES: None
============================================================================*/
/*----------------------------------------------------------------------------
* QCADC
* -------------------------------------------------------------------------*/
Device(ADC1)
{
/*----------------------------------------------------------------------------
* Dependencies
* -------------------------------------------------------------------------*/
Name(_DEP, Package(0x2)
{
\_SB_.SPMI,
\_SB_.PMIC
})
/*----------------------------------------------------------------------------
* HID
* -------------------------------------------------------------------------*/
Name(_HID, "QCOM0221")
Alias(\_SB.PSUB, _SUB)
Name(_UID, 0)
/*----------------------------------------------------------------------------
* ADC Resources
* -------------------------------------------------------------------------*/
Method(_CRS)
{
/*
* Interrupts
*/
Name (INTB, ResourceTemplate()
{
// VAdc - EOC
// ID = {slave id}{perph id}{int} = {0}{0011 0001}{000} = 0x188
GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {32} // 0x188 - PM_INT__VADC_HC1_USR__EOC
// VAdc TM - All interrupts
// ID = {slave id}{perph id}{int} = {0}{0011 0100}{000} = 0x1A0
GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {40} // 0x1A0 - PM_INT__VADC_HC7_BTM__THR
// FgAdc - All interrupts
// ID = {slave id}{perph id}{int} = {10}{0100 0101}{000} = 0x1228
GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullUp, 0, "\\_SB.PM01", , , , RawDataBuffer(){0x2}) {360} // 0x1228 - PM_INT__FG_ADC__BT_ID
})
/*
* SPMI peripherals
*/
Name(NAM, Buffer() {"\\_SB.SPMI"})
// VAdc
Name(VUSR, Buffer()
{
0x8E, // SPB Descriptor
0x13, 0x00, // Length including NAM above
0x01, // +0x00 SPB Descriptor Revision
0x00, // +0x01 Resource Source Index
0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
0x02, // +0x03 Consumer + controller initiated
0x00, 0x31, // +0x04 Type specific flags . Slave id, Upper8 bit address
0x01, // +0x06 Type specific revision
0x00, 0x00 // +0x07 type specific data length
// +0x09 - 0xd bytes for NULL-terminated NAM
// Length = 0x13
})
// VAdc TM
Name(VBTM, Buffer()
{
0x8E, // SPB Descriptor
0x13, 0x00, // Length including NAM above
0x01, // +0x00 SPB Descriptor Revision
0x00, // +0x01 Resource Source Index
0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
0x02, // +0x03 Consumer + controller initiated
0x00, 0x34, // +0x04 Type specific flags . Slave id, Upper8 bit address
0x01, // +0x06 Type specific revision
0x00, 0x00 // +0x07 type specific data length
// +0x09 - 0xd bytes for NULL-terminated NAM
// Length = 0x13
})
// FgAdc
Name(FGRR, Buffer()
{
0x8E, // SPB Descriptor
0x13, 0x00, // Length including NAM above
0x01, // +0x00 SPB Descriptor Revision
0x00, // +0x01 Resource Source Index
0xC1, // +0x02 Bus type - vendor defined values are in the range 0xc0-0xff
0x02, // +0x03 Consumer + controller initiated
0x02, 0x45, // +0x04 Type specific flags . Slave id, Upper8 bit address
0x01, // +0x06 Type specific revision
0x00, 0x00 // +0x07 type specific data length
// +0x09 - 0xd bytes for NULL-terminated NAM
// Length = 0x13
})
// Name(END, Buffer() {0x79, 0x00})
// {VUSR, NAM, VBTM, NAM, FGRR, NAM, INTB}
// {Local1, Local2, Local3, INTB}
// {Local4, Local5}
// {Local0}
Concatenate(VUSR, NAM, Local1)
Concatenate(VBTM, NAM, Local2)
Concatenate(FGRR, NAM, Local3)
Concatenate(Local1, Local2, Local4)
Concatenate(Local3, INTB, Local5)
Concatenate(Local4, Local5, Local0)
Return(Local0)
}
/*----------------------------------------------------------------------------
* Device configuration
* -------------------------------------------------------------------------*/
/*
* General ADC properties
*
* bHasVAdc:
* Whether or not TM is supported.
* 0 - Not supported
* 1 - Supported
*
* bHasTM:
* Whether or not TM is supported.
* 0 - Not supported
* 1 - Supported
*
* bHasFgAdc:
* Whether or not FGADC is supported.
* 0 - Not supported
* 1 - Supported
*
*/
Method (ADDV)
{
Return (Package()
{
/* .bHasVAdc = */ 1,
/* .bHasTM = */ 1,
/* .bHasFgAdc = */ 1,
})
}
/*----------------------------------------------------------------------------
* Voltage ADC (VADC) Configuration
* -------------------------------------------------------------------------*/
/*
* General VADC properties
*
* bUsesInterrupts:
* End-of-conversion interrupt mode.
* 0 - Polling mode
* 1 - Interrupt mode
*
* uFullScale_code:
* Full-scale ADC code.
*
* uFullScale_uV:
* Full-scale ADC voltage in uV.
*
* uReadTimeout_us:
* Timeout for reading ADC channels in us.
*
* uLDOSettlingTime_us:
* LDO settling time in us.
*
* ucMasterID:
* Master ID to send the interrupt to.
*
* ucPmicDevice:
* PMIC which has the VAdc.
*
* usMinDigRev:
* Minimum digital version <major> <minor>
*
* usMinAnaRev:
* Minimum analog version <major> <minor>
*
* ucPerphType:
* ADC peripheral type.
*
*/
Method (GENP)
{
Return (Package()
{
/* .bUsesInterrupts = */ 0,
/* .uFullScale_code = */ 0x4000,
/* .uFullScale_uV = */ 1875000,
/* .uReadTimeout_us = */ 500000,
/* .uLDOSettlingTime_us = */ 17,
/* .ucMasterID = */ 0,
/* .ucPmicDevice = */ 0,
/* .usMinDigRev = */ 0x300,
/* .usMinAnaRev = */ 0x100,
/* .ucPerphType = */ 0x8,
})
}
/*===========================================================================
FUNCTION PTCF
DESCRIPTION Scales the ADC result from millivolts to 0.001 degrees
Celsius using the PMIC thermistor conversion equation.
DEPENDENCIES None
PARAMETERS Arg0 [in] ADC result data (uMicroVolts)
RETURN VALUE Scaled result in mDegC
SIDE EFFECTS None
===========================================================================*/
Method (PTCF, 1)
{
/*
* Divide by two to convert from microvolt reading to micro-Kelvin.
*
* Subtract 273160 to convert the temperature from Kelvin to
* 0.001 degrees Celsius.
*/
ShiftRight (Arg0, 1, Local0)
Subtract (Local0, 273160, Local0)
Return (Local0)
}
/*===========================================================================
FUNCTION PTCI
DESCRIPTION Inverse of PTCF - scaled PMIC temperature to microvolts.
DEPENDENCIES None
PARAMETERS Arg0 [in] temperature in mDegC
RETURN VALUE ADC result data (uMicroVolts)
SIDE EFFECTS None
===========================================================================*/
Method (PTCI, 1)
{
Add (Arg0, 273160, Local0)
ShiftLeft (Local0, 1, Local0)
Return (Local0)
}
/*
* VADC channel to GPIO mapping
*
*/
Method (VGIO)
{
Return (Package()
{
Package()
{
/* .GPIO = */ 8,
/* .aucChannels = */ Buffer(){0x12, 0x32, 0x52, 0x72},
},
Package()
{
/* .GPIO = */ 9,
/* .aucChannels = */ Buffer(){0x13, 0x33, 0x53, 0x73},
},
Package()
{
/* .GPIO = */ 10,
/* .aucChannels = */ Buffer(){0x14, 0x34, 0x54, 0x74},
},
Package()
{
/* .GPIO = */ 11,
/* .aucChannels = */ Buffer(){0x15, 0x35, 0x55, 0x75},
},
Package()
{
/* .GPIO = */ 12,
/* .aucChannels = */ Buffer(){0x16, 0x36, 0x56, 0x76},
},
Package()
{
/* .GPIO = */ 21,
/* .aucChannels = */ Buffer(){0x17, 0x37, 0x57, 0x77, 0x97},
},
Package()
{
/* .GPIO = */ 22,
/* .aucChannels = */ Buffer(){0x18, 0x38, 0x58, 0x78, 0x98},
},
Package()
{
/* .GPIO = */ 23,
/* .aucChannels = */ Buffer(){0x19, 0x39, 0x59, 0x79, 0x99},
},
})
}
/*----------------------------------------------------------------------------
* Voltage ADC Threshold Monitor (VADCTM) Configuration
* -------------------------------------------------------------------------*/
/*
* General VADCTM properties
*
* eAverageMode:
* Obtains N ADC readings and averages them together.
* 0 - VADCTM_AVERAGE_1_SAMPLE
* 1 - VADCTM_AVERAGE_2_SAMPLES
* 2 - VADCTM_AVERAGE_4_SAMPLES
* 3 - VADCTM_AVERAGE_8_SAMPLES
* 4 - VADCTM_AVERAGE_16_SAMPLES
*
* eDecimationRatio:
* The decimation ratio.
* 0 - VADCTM_DECIMATION_RATIO_256
* 1 - VADCTM_DECIMATION_RATIO_512
* 2 - VADCTM_DECIMATION_RATIO_1024
*
* uFullScale_code:
* Full-scale ADC code.
*
* uFullScale_uV:
* Full-scale ADC voltage in uV.
*
* ucMasterID:
* Master ID to send the interrupt to.
*
* ucPmicDevice:
* PMIC which has the VAdc.
*
* usMinDigRev:
* Minimum digital version <major> <minor>
*
* usMinAnaRev:
* Minimum analog version <major> <minor>
*
* ucPerphType:
* ADC peripheral type.
*
*/
Method (VTGN)
{
Return (Package()
{
/* .eAverageMode = */ 2,
/* .eDecimationRatio = */ 2,
/* .uFullScale_code = */ 0x4000,
/* .uFullScale_uV = */ 1875000,
/* .ucMasterID = */ 0,
/* .ucPmicDevice = */ 0,
/* .usMinDigRev = */ 0x300,
/* .usMinAnaRev = */ 0x100,
/* .ucPerphType = */ 0x8,
})
}
/*----------------------------------------------------------------------------
* Fuel Gauge ADC (FGADC) Configuration
* -------------------------------------------------------------------------*/
/*
* General FGADC properties
*
* skinTempThreshRange:
* Range for skin temperature thresholds
*
* chgTempThreshRange:
* Range for charger temperature thresholds
*
* uFullScale_code:
* Full scale ADC value in code.
*
* uFullScale_uV:
* Full scale ADC value in microvolts.
*
* uMicroVoltsPerMilliAmps:
* Microvolts per milliamp scaling factor.
*
* uCodePerKelvin:
* Code per Kelvin scaling factor.
*
* uBattIdClipThresh:
* Max code for a BATT ID channel.
*
* uMaxWaitTimeus:
* Maximum time to wait for a reading to complete in microseconds.
*
* uSlaveId:
* PMIC slave ID.
*
* ucPmicDevice:
* PMIC which has the VAdc.
*
* ucPerphType:
* ADC peripheral type.
*
*/
Method (GENF)
{
Return (Package()
{
/* .skinTempThreshRange.nMin = */ 0xFFFFFFE2, // -30
/* .skinTempThreshRange.nMax = */ 97,
/* .chgTempThreshRange.nMin = */ 0xFFFFFFCE, // -50
/* .chgTempThreshRange.nMax = */ 160,
/* .uFullScale_code = */ 0x3ff,
/* .uFullScale_uV = */ 2500000,
/* .uMicroVoltsPerMilliAmps = */ 500,
/* .uCodePerKelvin = */ 4,
/* .uBattIdClipThresh = */ 820,
/* .uMaxWaitTimeUs = */ 5000000,
/* .uSlaveId = */ 2,
/* .ucPmicDevice = */ 1,
/* .ucPerphType = */ 0xD,
})
}
/*
* FGADC Channel Configuration Table
*
* The following table is the list of channels the FGADC can read. Below is
* a description of each field:
*
* sName:
* Appropriate string name for the channel from AdcInputs.h.
*
* eChannel:
* Which channel.
* 0 - FGADC_CHAN_SKIN_TEMP
* 1 - FGADC_CHAN_BATT_ID
* 2 - FGADC_CHAN_BATT_ID_FRESH
* 3 - FGADC_CHAN_BATT_ID_5
* 4 - FGADC_CHAN_BATT_ID_15
* 5 - FGADC_CHAN_BATT_ID_150
* 6 - FGADC_CHAN_BATT_THERM
* 7 - FGADC_CHAN_AUX_THERM
* 8 - FGADC_CHAN_USB_IN_V
* 9 - FGADC_CHAN_USB_IN_I
* 10 - FGADC_CHAN_DC_IN_V
* 11 - FGADC_CHAN_DC_IN_I
* 12 - FGADC_CHAN_DIE_TEMP
* 13 - FGADC_CHAN_CHARGER_TEMP
* 14 - FGADC_CHAN_GPIO
*
* eEnable:
* Whether or not to enable the channel.
* 0 - FGADC_DISABLE
* 1 - FGADC_ENABLE
*
* ucTriggers:
* Mask of triggers. Use 0x0 for default trigger configuration.
*
* scalingFactor.num:
* Numerator of the channel scaling
*
* scalingFactor.den:
* Denominator of the channel scaling
*
* eScaling:
* The scaling method to use.
* 0 - FGADC_SCALE_TO_MILLIVOLTS
* 1 - FGADC_SCALE_BATT_ID_TO_OHMS
* 2 - FGADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
* 3 - FGADC_SCALE_THERMISTOR
* 4 - FGADC_SCALE_CURRENT_TO_MILLIAMPS
*
* uInterpolationTableName:
* The name of the lookup table in ACPI that will be interpolated to obtain
* a physical value. Note that the physical value (which has default units
* of millivolts unless custom scaling function is used) is passed as the
* input. This value corresponds to the first column of the table. The
* scaled output appears in the physical adc result.
* 0 - No interpolation table
* WXYZ - Where 'WXYZ' is the interpolation table name
*
*/
Method (FCHN)
{
Return (Package()
{
/* BATT_ID_OHMS (BATT_ID pin) */
Package()
{
/* .sName = */ "BATT_ID_OHMS",
/* .eChannel = */ 1,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 1,
/* .uInterpolationTableName = */ 0,
},
/* BATT_ID_OHMS_FRESH (BATT_ID pin) */
Package()
{
/* .sName = */ "BATT_ID_OHMS_FRESH",
/* .eChannel = */ 2,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 1,
/* .uInterpolationTableName = */ 0,
},
/* BATT_THERM (BATT_THERM pin) */
Package()
{
/* .sName = */ "BATT_THERM",
/* .eChannel = */ 6,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 3,
/* .uInterpolationTableName = */ 0,
},
/* AUX_THERM (AUX_THERM pin) */
Package()
{
/* .sName = */ "AUX_THERM",
/* .eChannel = */ 7,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 3,
/* .uInterpolationTableName = */ 0,
},
/* SKIN_THERM (AUX_THERM pin) */
Package()
{
/* .sName = */ "SKIN_THERM",
/* .eChannel = */ 0,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 3,
/* .uInterpolationTableName = */ 0,
},
/* PMIC_TEMP2 (internal sensor) */
Package()
{
/* .sName = */ "PMIC_TEMP2",
/* .eChannel = */ 12,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 3,
/* .scalingFactor.den = */ 2,
/* .eScaling = */ 2,
/* .uInterpolationTableName = */ FGDT,
},
/* CHG_TEMP (internal sensor) */
Package()
{
/* .sName = */ "CHG_TEMP",
/* .eChannel = */ 13,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 3,
/* .scalingFactor.den = */ 2,
/* .eScaling = */ 2,
/* .uInterpolationTableName = */ FGCT,
},
/* USB_IN (USB_IN pin) */
Package()
{
/* .sName = */ "USB_IN",
/* .eChannel = */ 8,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 8,
/* .eScaling = */ 0,
/* .uInterpolationTableName = */ 0,
},
/* USB_IN_I (USB_IN pin) */
Package()
{
/* .sName = */ "USB_IN_I",
/* .eChannel = */ 9,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 4,
/* .uInterpolationTableName = */ 0,
},
/* DC_IN (DC_IN pin) */
Package()
{
/* .sName = */ "DC_IN",
/* .eChannel = */ 10,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 8,
/* .eScaling = */ 0,
/* .uInterpolationTableName = */ 0,
},
/* DC_IN_I (DC_IN pin) */
Package()
{
/* .sName = */ "DC_IN_I",
/* .eChannel = */ 11,
/* .eEnable = */ 1,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScaling = */ 4,
/* .uInterpolationTableName = */ 0,
},
/* FG_GPIO */
Package()
{
/* .sName = */ "FG_GPIO",
/* .eChannel = */ 14,
/* .eEnable = */ 0,
/* .ucTriggers = */ 0x0,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 2,
/* .eScaling = */ 0,
/* .uInterpolationTableName = */ 0,
},
})
}
/*
* Die temperature sensor scaling table
*
* The first column in the table is sensor voltage in millivolts and the
* second column is the temperature in milli degrees C.
*
* Scaling equation:
*
* milliDegC = (uV - 600000) / 2 + 25000
*
*/
Method (FGDT)
{
Return (Package()
{
Package(){ 450, 0xFFFF3CB0}, // -50000
Package(){ 870, 160000}
})
}
/*
* NOTE: CHG_TEMP on PMI8998 uses fab-dependent scaling in the driver.
* This is the default scaling if no fab-dependent scaling is found.
* It corresponds to GF.
*/
/*
* Charger temperature sensor scaling table
*
* The first column in the table is sensor voltage in millivolts and the
* second column is the temperature in milli degrees C.
*
* Scaling equation:
*
* milliDegC = (1303168 - uV) / 3.784 + 25000
*
*/
Method (FGCT)
{
Return (Package()
{
Package(){ 1587, 0xFFFF3CB0}, // -50000
Package(){ 792, 160000}
})
}
}
Include("cust_adc.asl")

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// This file contains the Audio Drivers
// ACPI device definitions, configuration and look-up tables.
//
// Currently there's nothing here

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// This file contains the Audio Drivers
// ACPI device definitions, configuration and look-up tables.
//
//
//ADCM
//
Device (ADCM)
{
// HID values are present in Qualcomm.HID.props under <WDKRoot>MSBuild\Qualcomm
// Parent of ADCM shall defined this ( Refer mproc.asl or slimbus.asl)
// AMSS in bear family and Slimbus in Badger family makes below entry
// Name (_HID, "QCOM023F")
Alias(\_SB.PSUB, _SUB)
// Address object for acpi device enumerated device (ADCM) on parent device bus
// Used to identify multiple child if present
Name (_ADR, 0)
// Adding dependency for LPASS SMMU (Defined in HoneyBadgerSmmu_Resources.asl)
//Added new dependency for 845+
Name (_DEP, Package()
{
\_SB_.MMU0,
\_SB_.IMM0,
})
// Child Method lists immediate child of ADCM - That is AUDD (Codec Driver)
Method (CHLD)
{
Return (Package()
{
// Syntax: Name of Parent Device (ADCM)\\HID value (HID_XXX) of AUDD driver
// HID values are present in Qualcomm.HID.props under <WDKRoot>MSBuild\Qualcomm
"ADCM\\QCOM0240"
})
}
// AUDD Driver Configurations
Device (AUDD)
{
// Address object for acpi device enumerated device (AUDD) on parent device bus
// Used to identify multiple child if present
Name (_ADR, 0)
Alias(\_SB.PSUB, _SUB)
// Adding dependency for SPI BUS
Name (_DEP, Package()
{
\_SB_.SPI9,
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
GpioIo(Exclusive, PullNone, 0, 1600, , "\\_SB.GIO0", ,) {64} //RESET
GpioInt(Edge, ActiveHigh, Exclusive, PullDown, 0, "\\_SB.GIO0", ,) {256} // GPIO number for interrupt changed for wakeup capability
// on target it is GPIO 54
GpioIo(Shared, PullUp, 0, 200, IoRestrictionOutputOnly, "\\_SB.GIO0", ,) {49} //USB_AUDIO_EN1
// SPI
SPISerialBus(
0, // DeviceSelection: chip-select, GPIO, or other line selection
, // DeviceSelectionPolarity: defaults to PolarityLow (optional)
, // WireMode: defaults to FourWireMode (optional)
8, // DataBitLength
, // SlaveMode: defaults to ControllerInitiated (optional)
24000000, // ConnectionSpeed: in Hz (24MHz, wcd supports SPI clock up tp 26MHz)
ClockPolarityLow, // ClockPolarity
ClockPhaseFirst, // ClockPhase
"\\_SB.SPI9", // ResourceSource: SPI bus controller name
, // ResourceSourceIndex: defaults to 0 (optional)
, // ResourceUsage: defaults to ResourceConsumer (optional)
, // DescriptorName: creates name for offset of resource descriptor
RawDataBuffer(){
0x00, // Reserved; must be 0
0x00, // spi_mode
0x00, // inter_word_delay_cycles
0x00, // loopback_mode
0x00, // cs_toggle
0x00, // endianness
0x00, // cs_clk_delay_cycles
}) // VendorData
})
Return (RBUF)
}
Method (CHLD)
{
// HID values are present in Qualcomm.HID.props under <WDKRoot>MSBuild\Qualcomm
Name(CH, Package()
{
// Syntax: Name of Parent Device (AUDD)\\HID value (HID_XXX) of MBHC driver
// QCOM0277 = QCOM2468
"AUDD\\QCOM0277",
// Syntax: Name of Parent Device (AUDD)\\HID value (HID_XXX) of QCRT driver
//QCOM0262 = QCOM2451
"AUDD\\QCOM0262",
})
Return(CH)
}
//
//MBHC
//
Device (MBHC)
{
// Address object for acpi device enumerated device (MBHC) on parent device bus
// Used to identify multiple child if present
Name (_ADR, 0)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate () {
//GpioIo(Shared, Pullup, 0, 200, IoRestrictionOutputOnly, "\\_SB.GIO0", ,) {51} //HSJ_US_EURO_SEL/EN2
})
Return (RBUF)
}
} // MBHC Device Configurations end
// Miniport Device Configurations
Device (QCRT)
{
// Address object for acpi device enumerated device (QCRT) on parent device bus
// Used to identify multiple child if present
// Since, QCRT is second child of AUDD, we have assigned slot-1
Name (_ADR, 1)
}// Miniport Device Configurations end
} // AUDD Driver Configurations end
} // end Device (ADCM)

38
DSDT/polaris/backlightcfg.asl Normal file
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@ -0,0 +1,38 @@
///
// BLCP Method - Backlight control packet method, returns a
// command buffer for a specific backlight level
//
// Input Parameters
// Backlight level - Integer from 0% to 100%
//
// Output Parameters
//
// Packet format:
// +--32bits--+-----variable (8bit alignment)--+
// | Header | Packet payload |
// +----------+--------------------------------+
//
// For DSI Command packets, payload data must be in this format
//
// +-- 8 bits-+----variable (8bit alignment)----+
// | Cmd Type | Packet Data |
// +----------+---------------------------------+
//
// For I2C Command packets, payload data must be in this format
//
// +-- 16 bits-+----variable (8bit alignment)----+
// | Address | Command Data |
// +-----------+---------------------------------+
//
// All packets must follow with a DWORD header with 0x0
//
Method (BLCP, 1, NotSerialized) {
// Create Response buffer
Name(RBUF, Buffer(0x100){})
// Details to be populated by OEM based on the platform requirements
// Return the packet data
Return(RBUF)
}

16
DSDT/polaris/backlightcfg2.asl Normal file
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//
// BLCP Method - Secondary display backlight control packet method, returns a
// command buffer for a specific backlight level
//
// Backlight configuration format is same as BLCP of primary panel in backlightcfg.asl
//
Method (BLC2, 1, NotSerialized) {
// Create Response buffer
Name(RBUF, Buffer(0x100){})
// Details to be populated by OEM based on the platform requirements
// Return the packet data
Return(RBUF)
}

678
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//
// Please note that not all the SE engine instances (I2C/SPI/UART) from below asl file can be used directly by icluding in the client ACPI,
// The corresponding Access Control needs to be enabled from TZ side to get the SE/usecase working End 2 End.
//
//
//
// QUPV3_ID0_SE7 (attached to BT SOC)
//
Device (UAR7)
{
Name (_HID, "QCOM0236")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 7)
Name (_DEP, Package() { \_SB_.PEP0 })
Name (_CCA, 0)
Method (_CRS)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0x00898000, 0x0004000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {639}
GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {48} // UART RX,
})
Return (RBUF)
}
Method (_STA)
{
Return (0x0B)
}
}
//
// QUPV3_ID1_SE2 (UART Debug port)
//
Device (UARD)
{
Name (_HID, "QCOM0236")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 10)
Name (_DEP, Package() { \_SB_.PEP0 })
Name (_CCA, 0)
Method (_CRS)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0x00A84000, 0x00004000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {386}
GpioInt(Edge, ActiveLow, Exclusive, PullDown, 0, "\\_SB.GIO0") {5} // UART RX
})
Return (RBUF)
}
}
//
// I2C4 - "Core I2C Bus"
//
// Device (I2C4)
// {
// Name (_HID, "QCOM0220")
// Alias(\_SB.PSUB, _SUB)
// Name (_UID, 4)
// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
// Name (_CCA, 0)
// Method (_CRS, 0x0, NotSerialized)
// {
// Name (RBUF, ResourceTemplate ()
// {
// Memory32Fixed (ReadWrite, 0x0088C000, 0x00004000)
// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {636}
// })
// Return (RBUF)
// }
// }
//
// I2C5 - "Core I2C Bus"
//
// Device (I2C6)
// {
// Name (_HID, "QCOM0220")
// Alias(\_SB.PSUB, _SUB)
// Name (_UID, 6)
// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
// Name (_CCA, 0)
// Method (_CRS, 0x0, NotSerialized)
// {
// Name (RBUF, ResourceTemplate ()
// {
// Memory32Fixed (ReadWrite, 0x894000, 0x00004000)
// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {638}
// })
// Return (RBUF)
// }
// }
//
// I2C11 - "Core I2C Bus"
//
// Device (IC11)
// {
// Name (_HID, "QCOM0220")
// Alias(\_SB.PSUB, _SUB)
// Name (_UID, 11)
// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
// Name (_CCA, 0)
// Method (_CRS, 0x0, NotSerialized)
// {
// Name (RBUF, ResourceTemplate ()
// {
// Memory32Fixed (ReadWrite, 0x00A88000, 0x00004000)
// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {387}
// })
// Return (RBUF)
// }
// }
//
// I2C15 - "Core I2C Bus"
//
//Device (IC15)
//{
// Name (_HID, "QCOM0220")
// Name (_UID, 15)
// Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP0})
// Name (_CCA, 0)
// Method (_CRS, 0x0, NotSerialized)
// {
// Name (RBUF, ResourceTemplate ()
// {
// Memory32Fixed (ReadWrite, 0x00A98000, 0x00004000)
// Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {391}
// })
// Return (RBUF)
// }
//}
//SPI9 - EPM
Device (SPI9)
{
Name (_HID, "QCOM021E")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 9)
Name (_DEP, Package(){\_SB_.PEP0,\_SB_.QGP1})
Name (_CCA, 0)
Method (_CRS)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed(ReadWrite, 0xA80000, 0x00004000)
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {385}
})
Return (RBUF)
}
}
//
// PEP resources for buses
//
Scope(\_SB_.PEP0)
{
Method(BSMD)
{
Return(BSRC)
}
Method(PQMD)
{
If (LLess(\_SB.SIDV,0x00020000))
{
Return(DFS1)
}
Else
{
Return(DFS2)
}
}
Name(BSRC, Package()
{
// "\\_SB.UAR7"
Package()
{
"DEVICE", "\\_SB.UAR7",
Package()
{
"COMPONENT", 0, // UART resources
Package()
{
"FSTATE", 0, // enable UART clocks
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk", 1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk", 1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 1}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}},
},
Package()
{
"FSTATE", 1, // disable UART clocks
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk", 2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk", 2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 2}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0}},
},
Package()
{
"PSTATE", 0, // enable GPIOs
Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 1, 0 }},
Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 0, 0 }},
Package(){"TLMMGPIO", Package(){ 47, 0, 1, 0, 0, 0 }},
Package(){"TLMMGPIO", Package(){ 48, 0, 1, 0, 1, 0 }},
},
Package()
{
"PSTATE", 1, // disable GPIOs
Package(){"TLMMGPIO", Package(){ 45, 0, 1, 0, 1, 0 }},
Package(){"TLMMGPIO", Package(){ 46, 0, 1, 0, 0, 0 }},
Package(){"TLMMGPIO", Package(){ 47, 0, 1, 0, 0, 0 }},
Package(){"TLMMGPIO", Package(){ 48, 0, 1, 0, 1, 0 }},
},
Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 7372800, 4}}},
Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 14745600, 4}}},
Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 29491200, 4}}},
Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 32000000, 4}}},
Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 48000000, 4}}},
Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 64000000, 4}}},
Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 80000000, 4}}},
Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3, 96000000, 4}}},
Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,102400000, 4}}},
Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,112000000, 4}}},
Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,117964800, 4}}},
Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s6_clk", 3,128000000, 4}}},
},
Package()
{
"COMPONENT", 1, // DMA resources
Package(){"FSTATE", 0}, // enable DMA clocks
Package(){"FSTATE", 1}, // disable DMA clocks
},
},
// "\\_SB.UARD"
Package()
{
"DEVICE", 0x2, //Debug device
"\\_SB.UARD",
Package()
{
"COMPONENT", 0, // UART resources
Package()
{
"FSTATE", 0, // enable UART clocks
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk",3, 7372800, 4}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 1}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000, 50000000}},
},
Package()
{
"FSTATE", 1, // disable UART clocks
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk", 2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk", 2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 2}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}},
},
Package()
{
"PSTATE", 0, // enable GPIOs
Package(){"TLMMGPIO", Package(){ 5, 0, 1, 0, 1, 0 }},
Package(){"TLMMGPIO", Package(){ 4, 0, 1, 0, 0, 0 }},
},
Package()
{
"PSTATE", 1, // disable GPIOs
Package(){"TLMMGPIO", Package(){ 5, 0, 1, 0, 1, 0 }},
Package(){"TLMMGPIO", Package(){ 4, 0, 1, 0, 0, 0 }},
},
Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 7372800, 4}}},
Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 14745600, 4}}},
Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 29491200, 4}}},
Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 32000000, 4}}},
Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 48000000, 4}}},
Package(){"PSTATE", 7, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 64000000, 4}}},
Package(){"PSTATE", 8, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 80000000, 4}}},
Package(){"PSTATE", 9, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3, 96000000, 4}}},
Package(){"PSTATE", 10, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,102400000, 4}}},
Package(){"PSTATE", 11, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,112000000, 4}}},
Package(){"PSTATE", 12, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,117964800, 4}}},
Package(){"PSTATE", 13, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s1_clk", 3,128000000, 4}}},
},
Package()
{
"COMPONENT", 1, // DMA resources
Package(){"FSTATE", 0}, // enable DMA clocks
Package(){"FSTATE", 1}, // disable DMA clocks
},
},
// "\\_SB.I2C4"
Package()
{
"DEVICE",
"\\_SB.I2C4",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",8,19200000, 4}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}},
// Configure SDA and then SCL
package() {"TLMMGPIO", package() {41, 1, 1, 1, 3, 0}},
package() {"TLMMGPIO", package() {42, 1, 1, 1, 3, 0}},
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s3_clk",2}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0 }},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0 }},
// Configure SCL and then SDA
package() { "TLMMGPIO", package() {41, 0, 0, 0, 3, 0}},
package() { "TLMMGPIO", package() {42, 0, 0, 0, 3, 0}},
},
},
// "\\_SB.I2C6"
Package()
{
"DEVICE",
"\\_SB.I2C6",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s5_clk",8,19200000, 4}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 148000000, 50000000}},
// Configure SDA and then SCL
package() {"TLMMGPIO", package() {85, 1, 1, 1, 3, 0}},
package() {"TLMMGPIO", package() {86, 1, 1, 1, 3, 0}},
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_m_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_0_s_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap0_s5_clk",2}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_1", "ICBID_SLAVE_EBI1", 0, 0 }},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_1", 0, 0 }},
// Configure SCL and then SDA
package() { "TLMMGPIO", package() {85, 0, 0, 0, 3, 0}},
package() { "TLMMGPIO", package() {86, 0, 0, 0, 3, 0}},
},
},
// "\\_SB.IC11"
Package()
{
"DEVICE",
"\\_SB.IC11",
Package()
{
"COMPONENT",
0x0, // Component 0.
Package()
{
"FSTATE",
0x0, // f0 state
},
},
Package()
{
"DSTATE",
0x0, // D0 state
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s2_clk",8,19200000, 4}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}},
// Configure SDA and then SCL
package() {"TLMMGPIO", package() {55, 1, 1, 1, 3, 0}},
package() {"TLMMGPIO", package() {56, 1, 1, 1, 3, 0}},
},
Package()
{
"DSTATE",
0x1, // D1 state
},
Package()
{
"DSTATE",
0x2, // D2 state
},
Package()
{
"DSTATE",
0x3, // D3 state
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s2_clk",2}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }},
// Configure SCL and then SDA
package() { "TLMMGPIO", package() {55, 0, 0, 0, 3, 0}},
package() { "TLMMGPIO", package() {56, 0, 0, 0, 3, 0}},
},
},
// "\\_SB.IC15"
//Package()
//{
//"DEVICE",
//"\\_SB.IC15",
//Package()
//{
//"COMPONENT",
//0x0, // Component 0.
//Package()
//{
//"FSTATE",
//0x0, // f0 state
//},
//},
//Package()
//{
//"DSTATE",
//0x0, // D0 state
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",8,19200000, 4}},
//Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666 }},
//Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000 }},
// Configure SDA and then SCL
//package() {"TLMMGPIO", package() {33, 1, 1, 1, 3, 0}},
//package() {"TLMMGPIO", package() {34, 1, 1, 1, 3, 0}},
//},
//Package()
//{
//"DSTATE",
//0x1, // D1 state
//},
//Package()
//{
//"DSTATE",
//0x2, // D2 state
//},
//Package()
//{
//"DSTATE",
//0x3, // D3 state
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
//Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s6_clk",2}},
//Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0 }},
//Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0 }},
// Configure SCL and then SDA
//package() { "TLMMGPIO", package() {33, 0, 0, 0, 3, 0}},
// package() { "TLMMGPIO", package() {34, 0, 0, 0, 3, 0}},
//},
//},
})
Name(DFS1, Package()
{
Package()
{
"DEVICE", "\\_SB.SPI9",
Package()
{
"COMPONENT", 0,
Package() {"FSTATE", 0},
Package(){"PSTATE", 0, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 19200000, 3}}},
Package(){"PSTATE", 1, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 32000000, 3}}},
Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 38400000, 3}}},
Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 48000000, 3}}},
Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 64000000, 3}}},
Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 96000000, 3}}},
Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 100000000, 3}}},
},
Package()
{
"DSTATE", 0, // enable clocks, enable GPIOs
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",1}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}},
Package(){"TLMMGPIO", Package(){ 65, 1, 2, 0, 1, 0}}, // MISO
Package(){"TLMMGPIO", Package(){ 66, 1, 2, 1, 1, 0}}, // MOSI
Package(){"TLMMGPIO", Package(){ 67, 1, 2, 1, 1, 0}}, // CLK
Package(){"TLMMGPIO", Package(){ 68, 1, 2, 1, 1, 0}}, // CS
},
Package() {"DSTATE", 1,},
Package() {"DSTATE", 2,},
Package()
{
"DSTATE", 3, // disable clocks, disable GPIOs
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",2}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}},
Package(){"TLMMGPIO", Package(){ 65, 0, 2, 0, 1, 0}}, // MOSI
Package(){"TLMMGPIO", Package(){ 66, 0, 2, 0, 1, 0}}, // MISO
Package(){"TLMMGPIO", Package(){ 67, 0, 2, 0, 1, 0}}, // CS
Package(){"TLMMGPIO", Package(){ 68, 0, 2, 0, 1, 0}}, // CLK
},
},
})
Name(DFS2, Package()
{
Package()
{
"DEVICE", "\\_SB.SPI9",
Package()
{
"COMPONENT", 0,
Package() {"FSTATE", 0},
Package(){"PSTATE", 0, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 19200000, 3}}},
Package(){"PSTATE", 1, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 32000000, 3}}},
Package(){"PSTATE", 2, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 48000000, 3}}},
Package(){"PSTATE", 3, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 64000000, 3}}},
Package(){"PSTATE", 4, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 96000000, 3}}},
Package(){"PSTATE", 5, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 100000000, 3}}},
Package(){"PSTATE", 6, Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk", 3, 120000000, 3}}},
},
Package()
{
"DSTATE", 0, // enable clocks, enable GPIOs
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",1}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",1}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 1400000000,1666}},
Package() {"BUSARB", Package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 148000000,50000000}},
Package(){"TLMMGPIO", Package(){ 65, 1, 2, 0, 1, 0}}, // MISO
Package(){"TLMMGPIO", Package(){ 66, 1, 2, 1, 1, 0}}, // MOSI
Package(){"TLMMGPIO", Package(){ 67, 1, 2, 1, 1, 0}}, // CLK
Package(){"TLMMGPIO", Package(){ 68, 1, 2, 1, 1, 0}}, // CS
},
Package() {"DSTATE", 1,},
Package() {"DSTATE", 2,},
Package()
{
"DSTATE", 3, // disable clocks, disable GPIOs
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_m_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap_1_s_ahb_clk",2}},
Package(){"CLOCK", Package(){"gcc_qupv3_wrap1_s0_clk",2}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_BLSP_2", "ICBID_SLAVE_EBI1", 0, 0}},
Package(){"BUSARB", Package(){3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_BLSP_2", 0, 0}},
Package(){"TLMMGPIO", Package(){ 65, 0, 2, 0, 1, 0}}, // MOSI
Package(){"TLMMGPIO", Package(){ 66, 0, 2, 0, 1, 0}}, // MISO
Package(){"TLMMGPIO", Package(){ 67, 0, 2, 0, 1, 0}}, // CS
Package(){"TLMMGPIO", Package(){ 68, 0, 2, 0, 1, 0}}, // CLK
},
},
})
}

898
DSDT/polaris/cust_adc.asl Normal file
View File

@ -0,0 +1,898 @@
/*============================================================================
FILE: cust_adc.asl
OVERVIEW: This file contains the board-specific configuration info for
ADC1 - qcadc analog-to-digital converter (ADC): channel
configurations, scaling functions, look-up tables, etc.
DEPENDENCIES: None
============================================================================*/
/*----------------------------------------------------------------------------
* QCADC
* -------------------------------------------------------------------------*/
Scope(\_SB.ADC1)
{
/*----------------------------------------------------------------------------
* Voltage ADC (VADC) Configuration
* -------------------------------------------------------------------------*/
/*
* VADC Channel Configuration Table
*
* The following table is the list of channels the ADC can read. Channels may
* be added or removed. Below is a description of each field:
*
* sName:
* Appropriate string name for the channel from AdcInputs.h.
*
* uAdcHardwareChannel:
* AMUX channel.
*
* eSettlingDelay:
* Holdoff time to allow the voltage to settle before reading the channel.
* 0 - VADC_SETTLING_DELAY_0_US
* 1 - VADC_SETTLING_DELAY_100_US
* 2 - VADC_SETTLING_DELAY_200_US
* 3 - VADC_SETTLING_DELAY_300_US
* 4 - VADC_SETTLING_DELAY_400_US
* 5 - VADC_SETTLING_DELAY_500_US
* 6 - VADC_SETTLING_DELAY_600_US
* 7 - VADC_SETTLING_DELAY_700_US
* 8 - VADC_SETTLING_DELAY_800_US
* 9 - VADC_SETTLING_DELAY_900_US
* 10 - VADC_SETTLING_DELAY_1_MS
* 11 - VADC_SETTLING_DELAY_2_MS
* 12 - VADC_SETTLING_DELAY_4_MS
* 13 - VADC_SETTLING_DELAY_6_MS
* 14 - VADC_SETTLING_DELAY_8_MS
* 15 - VADC_SETTLING_DELAY_10_MS
*
* eAverageMode:
* Obtains N ADC readings and averages them together.
* 0 - VADC_AVERAGE_1_SAMPLE
* 1 - VADC_AVERAGE_2_SAMPLES
* 2 - VADC_AVERAGE_4_SAMPLES
* 3 - VADC_AVERAGE_8_SAMPLES
* 4 - VADC_AVERAGE_16_SAMPLES
*
* eDecimationRatio:
* The decimation ratio.
* 0 - VADC_DECIMATION_RATIO_256
* 1 - VADC_DECIMATION_RATIO_512
* 2 - VADC_DECIMATION_RATIO_1024
*
* eCalMethod:
* Calibration method.
* 0 - VADC_CAL_METHOD_NO_CAL
* 1 - VADC_CAL_METHOD_RATIOMETRIC
* 2 - VADC_CAL_METHOD_ABSOLUTE
*
* scalingFactor.num:
* Numerator of the channel scaling
*
* scalingFactor.den:
* Denominator of the channel scaling
*
* eScalingMethod:
* The scaling method to use.
* 0 - VADC_SCALE_TO_MILLIVOLTS
* 1 - VADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
* 2 - VADC_SCALE_THERMISTOR (requires uPullUp and uInterpolationTableName)
*
* uPullUp:
* The pull up resistor value. Use with eScalingMethod == VADC_SCALE_THERMISTOR,
* otherwise, 0.
*
* uInterpolationTableName:
* The name of the lookup table in ACPI that will be interpolated to obtain
* a physical value. Note that the physical value (which has default units
* of millivolts unless custom scaling function is used) is passed as the
* input. This value corresponds to the first column of the table. The
* scaled output appears in the physical adc result.
* 0 - No interpolation table
* WXYZ - Where 'WXYZ' is the interpolation table name
*
* uScalingFunctionName:
* The name of the function to call in the ACPI table to perform custom
* scaling. The input to the custom scaling function is defined by
* eScalingFunctionInput. The output of the custom scaling function is
* the physical value.
* 0 - No scaling function
* WXYZ - Where 'WXYZ' is the scaling function name
*
* Note: if both a custon scaling function & interpolation table are used
* the custom scaling function is called first.
*
* eScalingFunctionInput:
* Defines which ADC result is passed to the custom scaling function.
* 0 - VADC_SCALING_FUNCTION_INPUT_PHYSICAL
* 1 - VADC_SCALING_FUNCTION_INPUT_PERCENT
* 2 - VADC_SCALING_FUNCTION_INPUT_MICROVOLTS
* 3 - VADC_SCALING_FUNCTION_INPUT_CODE
*
*/
Method (CHAN)
{
Return (Package()
{
/* VPH_PWR (VPH_PWR_SNS pin) */
Package()
{
/* .sName = */ "VPH_PWR",
/* .uAdcHardwareChannel = */ 0x83,
/* .eSettlingDelay = */ 0,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 2,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 3,
/* .eScalingMethod = */ 0,
/* .uPullUp = */ 0,
/* .uInterpolationTableName = */ 0,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* VCOIN (VCOIN pin) */
Package()
{
/* .sName = */ "VCOIN",
/* .uAdcHardwareChannel = */ 0x85,
/* .eSettlingDelay = */ 0,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 2,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 3,
/* .eScalingMethod = */ 0,
/* .uPullUp = */ 0,
/* .uInterpolationTableName = */ 0,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* PMIC_TEMP1 (internal sensor) */
Package()
{
/* .sName = */ "PMIC_THERM",
/* .uAdcHardwareChannel = */ 0x6,
/* .eSettlingDelay = */ 0,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 2,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 0,
/* .uPullUp = */ 0,
/* .uInterpolationTableName = */ 0,
/* .uScalingFunctionName = */ PTCF,
/* .eScalingFunctionInput = */ 2,
},
/* XO_THERM (XO_THERM pin) */
Package()
{
/* .sName = */ "XO_THERM",
/* .uAdcHardwareChannel = */ 0x4c,
/* .eSettlingDelay = */ 8,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ XTTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* XO_THERM_GPS (XO_THERM pin) */
Package()
{
/* .sName = */ "XO_THERM_GPS",
/* .uAdcHardwareChannel = */ 0x4c,
/* .eSettlingDelay = */ 8,
/* .eAverageMode = */ 2,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ XTTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* SYS_THERM1 (AMUX_1 pin) */
Package()
{
/* .sName = */ "SYS_THERM1",
/* .uAdcHardwareChannel = */ 0x4d,
/* .eSettlingDelay = */ 1,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* SYS_THERM2 (AMUX_2 pin) */
Package()
{
/* .sName = */ "SYS_THERM2",
/* .uAdcHardwareChannel = */ 0x4e,
/* .eSettlingDelay = */ 1,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* PA_THERM (AMUX_3 pin) */
Package()
{
/* .sName = */ "PA_THERM",
/* .uAdcHardwareChannel = */ 0x4f,
/* .eSettlingDelay = */ 1,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* PA_THERM1 (AMUX_4 pin) */
Package()
{
/* .sName = */ "PA_THERM1",
/* .uAdcHardwareChannel = */ 0x50,
/* .eSettlingDelay = */ 1,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
/* SYS_THERM3 (AMUX_5 pin) */
Package()
{
/* .sName = */ "SYS_THERM3",
/* .uAdcHardwareChannel = */ 0x51,
/* .eSettlingDelay = */ 1,
/* .eAverageMode = */ 0,
/* .eDecimationRatio = */ 2,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
},
})
}
/*
* System Thermistor Table
*
* The first column in the table is thermistor resistance R_T in ohms
* and the second column is the temperature in degrees C.
*
* VDD ___
* |
* >
* P_PU <
* >
* |
* |
* |- - - V_T
* |
* >
* R_T < 100 kOhms (NTCG104EF104FB)
* >
* |
* |
* Gnd
*
*/
Method (SYTB)
{
Return (Package()
{
Package(){4251000, 0xFFFFFFD8}, // -40
Package(){3004900, 0xFFFFFFDD}, // -35
Package(){2148900, 0xFFFFFFE2}, // -30
Package(){1553800, 0xFFFFFFE7}, // -25
Package(){1135300, 0xFFFFFFEC}, // -20
Package(){ 837800, 0xFFFFFFF1}, // -15
Package(){ 624100, 0xFFFFFFF6}, // -10
Package(){ 469100, 0xFFFFFFFB}, // -5
Package(){ 355600, 0},
Package(){ 271800, 5},
Package(){ 209400, 10},
Package(){ 162500, 15},
Package(){ 127000, 20},
Package(){ 100000, 25},
Package(){ 79200, 30},
Package(){ 63200, 35},
Package(){ 50700, 40},
Package(){ 40900, 45},
Package(){ 33200, 50},
Package(){ 27100, 55},
Package(){ 22200, 60},
Package(){ 18300, 65},
Package(){ 15200, 70},
Package(){ 12600, 75},
Package(){ 10600, 80},
Package(){ 8890, 85},
Package(){ 7500, 90},
Package(){ 6360, 95},
Package(){ 5410, 100},
Package(){ 4620, 105},
Package(){ 3970, 110},
Package(){ 3420, 115},
Package(){ 2950, 120},
Package(){ 2560, 125}
})
}
/*
* XO Thermistor Table
*
* This lookup table is used to convert the XO thermistor reading to temperature
* in degrees C multiplied by a factor of 1024.
*
* The first column in the table is thermistor resistance R_T in ohms
*
* The second column is the temperature in degrees Celsius multiplied by a factor
* of 1024.
*
* VDD ___
* |
* >
* P_PU < 100 kOhms
* >
* |
* |
* |- - - V_T
* |
* >
* R_T < 100 kOhms (NTCG104EF104FB)
* >
* |
* |
* Gnd
*
*/
Method (XTTB)
{
Return (Package()
{
Package(){4250657, 0xFFFF6000}, // -40960
Package(){3962085, 0xFFFF6400}, // -39936
Package(){3694875, 0xFFFF6800}, // -38912
Package(){3447322, 0xFFFF6C00}, // -37888
Package(){3217867, 0xFFFF7000}, // -36864
Package(){3005082, 0xFFFF7400}, // -35840
Package(){2807660, 0xFFFF7800}, // -34816
Package(){2624405, 0xFFFF7C00}, // -33792
Package(){2454218, 0xFFFF8000}, // -32768
Package(){2296094, 0xFFFF8400}, // -31744
Package(){2149108, 0xFFFF8800}, // -30720
Package(){2012414, 0xFFFF8C00}, // -29696
Package(){1885232, 0xFFFF9000}, // -28672
Package(){1766846, 0xFFFF9400}, // -27648
Package(){1656598, 0xFFFF9800}, // -26624
Package(){1553884, 0xFFFF9C00}, // -25600
Package(){1458147, 0xFFFFA000}, // -24576
Package(){1368873, 0xFFFFA400}, // -23552
Package(){1285590, 0xFFFFA800}, // -22528
Package(){1207863, 0xFFFFAC00}, // -21504
Package(){1135290, 0xFFFFB000}, // -20480
Package(){1067501, 0xFFFFB400}, // -19456
Package(){1004155, 0xFFFFB800}, // -18432
Package(){ 944935, 0xFFFFBC00}, // -17408
Package(){ 889550, 0xFFFFC000}, // -16384
Package(){ 837731, 0xFFFFC400}, // -15360
Package(){ 789229, 0xFFFFC800}, // -14336
Package(){ 743813, 0xFFFFCC00}, // -13312
Package(){ 701271, 0xFFFFD000}, // -12288
Package(){ 661405, 0xFFFFD400}, // -11264
Package(){ 624032, 0xFFFFD800}, // -10240
Package(){ 588982, 0xFFFFDC00}, // -9216
Package(){ 556100, 0xFFFFE000}, // -8192
Package(){ 525239, 0xFFFFE400}, // -7168
Package(){ 496264, 0xFFFFE800}, // -6144
Package(){ 469050, 0xFFFFEC00}, // -5120
Package(){ 443480, 0xFFFFF000}, // -4096
Package(){ 419448, 0xFFFFF400}, // -3072
Package(){ 396851, 0xFFFFF800}, // -2048
Package(){ 375597, 0xFFFFFC00}, // -1024
Package(){ 355598, 0},
Package(){ 336775, 1024},
Package(){ 319052, 2048},
Package(){ 302359, 3072},
Package(){ 286630, 4096},
Package(){ 271806, 5120},
Package(){ 257829, 6144},
Package(){ 244646, 7168},
Package(){ 232209, 8192},
Package(){ 220471, 9216},
Package(){ 209390, 10240},
Package(){ 198926, 11264},
Package(){ 189040, 12288},
Package(){ 179698, 13312},
Package(){ 170868, 14336},
Package(){ 162519, 15360},
Package(){ 154622, 16384},
Package(){ 147150, 17408},
Package(){ 140079, 18432},
Package(){ 133385, 19456},
Package(){ 127046, 20480},
Package(){ 121042, 21504},
Package(){ 115352, 22528},
Package(){ 109960, 23552},
Package(){ 104848, 24576},
Package(){ 100000, 25600},
Package(){ 95402, 26624},
Package(){ 91038, 27648},
Package(){ 86897, 28672},
Package(){ 82965, 29696},
Package(){ 79232, 30720},
Package(){ 75686, 31744},
Package(){ 72316, 32768},
Package(){ 69114, 33792},
Package(){ 66070, 34816},
Package(){ 63176, 35840},
Package(){ 60423, 36864},
Package(){ 57804, 37888},
Package(){ 55312, 38912},
Package(){ 52940, 39936},
Package(){ 50681, 40960},
Package(){ 48531, 41984},
Package(){ 46482, 43008},
Package(){ 44530, 44032},
Package(){ 42670, 45056},
Package(){ 40897, 46080},
Package(){ 39207, 47104},
Package(){ 37595, 48128},
Package(){ 36057, 49152},
Package(){ 34590, 50176},
Package(){ 33190, 51200},
Package(){ 31853, 52224},
Package(){ 30577, 53248},
Package(){ 29358, 54272},
Package(){ 28194, 55296},
Package(){ 27082, 56320},
Package(){ 26020, 57344},
Package(){ 25004, 58368},
Package(){ 24033, 59392},
Package(){ 23104, 60416},
Package(){ 22216, 61440},
Package(){ 21367, 62464},
Package(){ 20554, 63488},
Package(){ 19776, 64512},
Package(){ 19031, 65536},
Package(){ 18318, 66560},
Package(){ 17636, 67584},
Package(){ 16982, 68608},
Package(){ 16355, 69632},
Package(){ 15755, 70656},
Package(){ 15180, 71680},
Package(){ 14628, 72704},
Package(){ 14099, 73728},
Package(){ 13592, 74752},
Package(){ 13106, 75776},
Package(){ 12640, 76800},
Package(){ 12192, 77824},
Package(){ 11762, 78848},
Package(){ 11350, 79872},
Package(){ 10954, 80896},
Package(){ 10574, 81920},
Package(){ 10209, 82944},
Package(){ 9858, 83968},
Package(){ 9521, 84992},
Package(){ 9197, 86016},
Package(){ 8886, 87040},
Package(){ 8587, 88064},
Package(){ 8299, 89088},
Package(){ 8023, 90112},
Package(){ 7757, 91136},
Package(){ 7501, 92160},
Package(){ 7254, 93184},
Package(){ 7017, 94208},
Package(){ 6789, 95232},
Package(){ 6570, 96256},
Package(){ 6358, 97280},
Package(){ 6155, 98304},
Package(){ 5959, 99328},
Package(){ 5770, 100352},
Package(){ 5588, 101376},
Package(){ 5412, 102400},
Package(){ 5243, 103424},
Package(){ 5080, 104448},
Package(){ 4923, 105472},
Package(){ 4771, 106496},
Package(){ 4625, 107520},
Package(){ 4484, 108544},
Package(){ 4348, 109568},
Package(){ 4217, 110592},
Package(){ 4090, 111616},
Package(){ 3968, 112640},
Package(){ 3850, 113664},
Package(){ 3736, 114688},
Package(){ 3626, 115712},
Package(){ 3519, 116736},
Package(){ 3417, 117760},
Package(){ 3317, 118784},
Package(){ 3221, 119808},
Package(){ 3129, 120832},
Package(){ 3039, 121856},
Package(){ 2952, 122880},
Package(){ 2868, 123904},
Package(){ 2787, 124928},
Package(){ 2709, 125952},
Package(){ 2633, 126976},
Package(){ 2560, 128000},
Package(){ 2489, 129024},
Package(){ 2420, 130048}
})
}
/*----------------------------------------------------------------------------
* Voltage ADC Threshold Monitor (VADCTM) Configuration
* -------------------------------------------------------------------------*/
/*
* VADCTM Measurement Configuration Table
*
* The following is a list of periodic measurements that the VADCTM
* can periodically monitor. Thresholds for these measurements are set
* in software.
*
* sName:
* Appropriate string name for the channel from AdcInputs.h.
*
* uAdcHardwareChannel:
* AMUX channel.
*
* eSettlingDelay:
* Holdoff time to allow the voltage to settle before reading the channel.
* 0 - VADCTM_SETTLING_DELAY_0_US
* 1 - VADCTM_SETTLING_DELAY_100_US
* 2 - VADCTM_SETTLING_DELAY_200_US
* 3 - VADCTM_SETTLING_DELAY_300_US
* 4 - VADCTM_SETTLING_DELAY_400_US
* 5 - VADCTM_SETTLING_DELAY_500_US
* 6 - VADCTM_SETTLING_DELAY_600_US
* 7 - VADCTM_SETTLING_DELAY_700_US
* 8 - VADCTM_SETTLING_DELAY_800_US
* 9 - VADCTM_SETTLING_DELAY_900_US
* 10 - VADCTM_SETTLING_DELAY_1_MS
* 11 - VADCTM_SETTLING_DELAY_2_MS
* 12 - VADCTM_SETTLING_DELAY_4_MS
* 13 - VADCTM_SETTLING_DELAY_6_MS
* 14 - VADCTM_SETTLING_DELAY_8_MS
* 15 - VADCTM_SETTLING_DELAY_10_MS
*
* eMeasIntervalTimeSelect:
* The interval timer to use for the measurement period.
* 0 - VADCTM_MEAS_INTERVAL_TIME1
* 1 - VADCTM_MEAS_INTERVAL_TIME2
* 2 - VADCTM_MEAS_INTERVAL_TIME3
*
* bAlwaysOn:
* Keep the measurement always sampling even if no thresholds are set.
* 0 - FALSE
* 1 - TRUE
*
* eCalMethod:
* Calibration method.
* 0 - VADC_CAL_METHOD_NO_CAL
* 1 - VADC_CAL_METHOD_RATIOMETRIC
* 2 - VADC_CAL_METHOD_ABSOLUTE
*
* scalingFactor.num:
* Numerator of the channel scaling
*
* scalingFactor.den:
* Denominator of the channel scaling
*
* eScalingMethod:
* The scaling method to use.
* 0 - VADC_SCALE_TO_MILLIVOLTS
* 1 - VADC_SCALE_INTERPOLATE_FROM_MILLIVOLTS (requires uInterpolationTableName)
* 2 - VADC_SCALE_THERMISTOR (requires uPullUp and uInterpolationTableName)
*
* uPullUp:
* The pull up resistor value. Use with eScalingMethod == VADC_SCALE_THERMISTOR,
* otherwise, 0.
*
* uInterpolationTableName:
* The name of the lookup table in ACPI that will be interpolated to obtain
* a physical value. Note that the physical value (which has default units
* of millivolts unless custom scaling function is used) is passed as the
* input. This value corresponds to the first column of the table. The
* scaled output appears in the physical adc result.
* 0 - No interpolation table
* WXYZ - Where 'WXYZ' is the interpolation table name
*
* uScalingFunctionName:
* The name of the function to call in the ACPI table to perform custom
* scaling. The input to the custom scaling function is defined by
* eScalingFunctionInput. The output of the custom scaling function is
* the physical value.
* 0 - No scaling function
* WXYZ - Where 'WXYZ' is the scaling function name
*
* Note: if both a custon scaling function & interpolation table are used
* the custom scaling function is called first.
*
* uInverseFunctionName:
* The name of the inverse scaling for uScalingFunctionName.
* 0 - No scaling function
* WXYZ - Where 'WXYZ' is the scaling function name
*
* eScalingFunctionInput:
* Defines which ADC result is passed to the custom scaling function.
* 0 - VADC_SCALING_FUNCTION_INPUT_PHYSICAL
* 1 - VADC_SCALING_FUNCTION_INPUT_PERCENT
* 2 - VADC_SCALING_FUNCTION_INPUT_MICROVOLTS
* 3 - VADC_SCALING_FUNCTION_INPUT_CODE
*
* nPhysicalMin:
* Minimum threshold value in physical units.
*
* nPhysicalMax:
* Maximum threshold value in physical units.
*
*/
Method (VTCH)
{
Return (Package()
{
/* VPH_PWR (VPH_PWR_SNS pin) */
Package()
{
/* .sName = */ "VPH_PWR",
/* .uAdcHardwareChannel = */ 0x83,
/* .eSettlingDelay = */ 0,
/* .eMeasIntervalTimeSelect = */ 1,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 2,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 3,
/* .eScalingMethod = */ 0,
/* .uPullUp = */ 0,
/* .uInterpolationTableName = */ 0,
/* .uScalingFunctionName = */ 0,
/* .uInverseFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
/* .nPhysicalMin = */ 0,
/* .nPhysicalMax = */ 5625,
},
/* PMIC_TEMP1 (internal sensor) */
Package()
{
/* .sName = */ "PMIC_THERM",
/* .uAdcHardwareChannel = */ 0x6,
/* .eSettlingDelay = */ 0,
/* .eMeasIntervalTimeSelect = */ 0,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 2,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 0,
/* .uPullUp = */ 0,
/* .uInterpolationTableName = */ 0,
/* .uScalingFunctionName = */ PTCF,
/* .uInverseFunctionName = */ PTCI,
/* .eScalingFunctionInput = */ 2,
/* .nPhysicalMin = */ 0xFFFF3CB0, // -50000
/* .nPhysicalMax = */ 150000,
},
/* SYS_THERM1 (AMUX_1 pin) */
Package()
{
/* .sName = */ "SYS_THERM1",
/* .uAdcHardwareChannel = */ 0x4d,
/* .eSettlingDelay = */ 1,
/* .eMeasIntervalTimeSelect = */ 0,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .uInverseFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
/* .nPhysicalMin = */ 0xFFFFFFD8, // -40
/* .nPhysicalMax = */ 125,
},
/* SYS_THERM2 (AMUX_2 pin) */
Package()
{
/* .sName = */ "SYS_THERM2",
/* .uAdcHardwareChannel = */ 0x4e,
/* .eSettlingDelay = */ 1,
/* .eMeasIntervalTimeSelect = */ 0,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .uInverseFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
/* .nPhysicalMin = */ 0xFFFFFFD8, // -40
/* .nPhysicalMax = */ 125,
},
/* PA_THERM (AMUX_3 pin) */
Package()
{
/* .sName = */ "PA_THERM",
/* .uAdcHardwareChannel = */ 0x4f,
/* .eSettlingDelay = */ 1,
/* .eMeasIntervalTimeSelect = */ 0,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .uInverseFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
/* .nPhysicalMin = */ 0xFFFFFFD8, // -40
/* .nPhysicalMax = */ 125,
},
/* PA_THERM1 (AMUX_4 pin) */
Package()
{
/* .sName = */ "PA_THERM1",
/* .uAdcHardwareChannel = */ 0x50,
/* .eSettlingDelay = */ 1,
/* .eMeasIntervalTimeSelect = */ 0,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .uInverseFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
/* .nPhysicalMin = */ 0xFFFFFFD8, // -40
/* .nPhysicalMax = */ 125,
},
/* SYS_THERM3 (AMUX_5 pin) */
Package()
{
/* .sName = */ "SYS_THERM3",
/* .uAdcHardwareChannel = */ 0x51,
/* .eSettlingDelay = */ 1,
/* .eMeasIntervalTimeSelect = */ 0,
/* .bAlwaysOn = */ 0,
/* .eCalMethod = */ 1,
/* .scalingFactor.num = */ 1,
/* .scalingFactor.den = */ 1,
/* .eScalingMethod = */ 2,
/* .uPullUp = */ 100000,
/* .uInterpolationTableName = */ SYTB,
/* .uScalingFunctionName = */ 0,
/* .uInverseFunctionName = */ 0,
/* .eScalingFunctionInput = */ 0,
/* .nPhysicalMin = */ 0xFFFFFFD8, // -40
/* .nPhysicalMax = */ 125,
},
})
}
/*
* General VADCTM measurement timer properties
*
* eMeasIntervalTime1:
* Interval timer 1 periodic value.
* 0 - VADCTM_MEAS_INTERVAL_TIME1_0_MS
* 1 - VADCTM_MEAS_INTERVAL_TIME1_1P0_MS
* 2 - VADCTM_MEAS_INTERVAL_TIME1_2P0_MS
* 3 - VADCTM_MEAS_INTERVAL_TIME1_3P9_MS
* 4 - VADCTM_MEAS_INTERVAL_TIME1_7P8_MS
* 5 - VADCTM_MEAS_INTERVAL_TIME1_15P6_MS
* 6 - VADCTM_MEAS_INTERVAL_TIME1_31P1_MS
* 7 - VADCTM_MEAS_INTERVAL_TIME1_62P5_MS
* 8 - VADCTM_MEAS_INTERVAL_TIME1_125_MS
* 9 - VADCTM_MEAS_INTERVAL_TIME1_250_MS
* 10 - VADCTM_MEAS_INTERVAL_TIME1_500_MS
* 11 - VADCTM_MEAS_INTERVAL_TIME1_1000_MS
* 12 - VADCTM_MEAS_INTERVAL_TIME1_2000_MS
* 13 - VADCTM_MEAS_INTERVAL_TIME1_4000_MS
* 14 - VADCTM_MEAS_INTERVAL_TIME1_8000_MS
* 15 - VADCTM_MEAS_INTERVAL_TIME1_16000_MS
*
* eMeasIntervalTime2:
* Interval timer 2 periodic value.
* 0 - VADCTM_MEAS_INTERVAL_TIME2_0_MS
* 1 - VADCTM_MEAS_INTERVAL_TIME2_100_MS
* 2 - VADCTM_MEAS_INTERVAL_TIME2_200_MS
* 3 - VADCTM_MEAS_INTERVAL_TIME2_300_MS
* 4 - VADCTM_MEAS_INTERVAL_TIME2_400_MS
* 5 - VADCTM_MEAS_INTERVAL_TIME2_500_MS
* 6 - VADCTM_MEAS_INTERVAL_TIME2_600_MS
* 7 - VADCTM_MEAS_INTERVAL_TIME2_700_MS
* 8 - VADCTM_MEAS_INTERVAL_TIME2_800_MS
* 9 - VADCTM_MEAS_INTERVAL_TIME2_900_MS
* 10 - VADCTM_MEAS_INTERVAL_TIME2_1000_MS
* 11 - VADCTM_MEAS_INTERVAL_TIME2_1100_MS
* 12 - VADCTM_MEAS_INTERVAL_TIME2_1200_MS
* 13 - VADCTM_MEAS_INTERVAL_TIME2_1300_MS
* 14 - VADCTM_MEAS_INTERVAL_TIME2_1400_MS
* 15 - VADCTM_MEAS_INTERVAL_TIME2_1500_MS
*
* eMeasIntervalTime3:
* Interval timer 3 periodic value.
* 0 - VADCTM_MEAS_INTERVAL_TIME3_0_S
* 1 - VADCTM_MEAS_INTERVAL_TIME3_1_S
* 2 - VADCTM_MEAS_INTERVAL_TIME3_2_S
* 3 - VADCTM_MEAS_INTERVAL_TIME3_3_S
* 4 - VADCTM_MEAS_INTERVAL_TIME3_4_S
* 5 - VADCTM_MEAS_INTERVAL_TIME3_5_S
* 6 - VADCTM_MEAS_INTERVAL_TIME3_6_S
* 7 - VADCTM_MEAS_INTERVAL_TIME3_7_S
* 8 - VADCTM_MEAS_INTERVAL_TIME3_8_S
* 9 - VADCTM_MEAS_INTERVAL_TIME3_9_S
* 10 - VADCTM_MEAS_INTERVAL_TIME3_10_S
* 11 - VADCTM_MEAS_INTERVAL_TIME3_11_S
* 12 - VADCTM_MEAS_INTERVAL_TIME3_12_S
* 13 - VADCTM_MEAS_INTERVAL_TIME3_13_S
* 14 - VADCTM_MEAS_INTERVAL_TIME3_14_S
* 15 - VADCTM_MEAS_INTERVAL_TIME3_15_S
*
*/
Method (VTMT)
{
Return (Package()
{
/* .eMeasIntervalTime1 = */ 11, // 1000 ms
/* .eMeasIntervalTime2 = */ 1, // 100 ms
/* .eMeasIntervalTime3 = */ 5, // 5000 ms
})
}
}

39
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Device (BTNS)
{
Name(_HID, "ACPI0011")
Alias(\_SB.PSUB, _SUB)
Name(_UID, 0)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
//Power Button
GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullDown, 0, "\\_SB.PM01", ,) {0} // 0x40 - PM_INT__PON__KPDPWR_ON
// Volume Up button
GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {133} // 0x628 - PM_INT__PM1_GPIO6__GPIO_IN_STS
// Volume Down button
GpioInt(Edge, ActiveBoth, Exclusive, PullDown, 0, "\\_SB.PM01", ,) {1} // 0x41 - PM_INT__PON__RESIN_ON
// Camera Focus
GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {135} // 0x638 - PM_INT__PM1_GPIO8__GPIO_IN_STS
//Camera Snapshot
GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01", ,) {134} // 0x630 - PM_INT__PM1_GPIO7__GPIO_IN_STS
})
Return (RBUF)
}
Name(_DSD, Package(2) {
ToUUID("FA6BD625-9CE8-470D-A2C7-B3CA36C4282E"),
Package() {
Package(5) {0,1,0,0x01,0x0D}, // Portable Device Control Application Collection
Package(5) {1,0,1,0x01,0x81}, // Sleep
Package(5) {1,1,1,0x0C,0xE9}, // Volume Increment
Package(5) {1,2,1,0x0C,0xEA}, // Volume Decrement
Package(5) {1,3,1,0x90,0x20}, // Camera Auto Focus
Package(5) {1,4,1,0x90,0x21}, // Camera Shutter
},
})
}

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//==============================================================================
// <cust_camera.asl>
// DESCRIPTION
// This file contains resources (such as memory address, GPIOs, etc.) and
// methods needed by camera drivers.
//==============================================================================
Include("cust_camera_exasoc.asl")
//
// CAMERA MIPI CSI (based on Titan 170 v1 hardware)
//
Device (MPCS)
{
Name (_DEP, Package(0x1)
{
\_SB_.CAMP
})
Name (_HID, "QCOM02E8")
Name (_UID, 24)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0x0AC65000, 0x00000900) // PHY 0 memory
Memory32Fixed (ReadWrite, 0x0AC66000, 0x00000900) // PHY 1 memory
Memory32Fixed (ReadWrite, 0x0AC67000, 0x00000900) // PHY 2 memory
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {509} // PHY 0 interrupt, csiphy_0_irq
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {510} // PHY 1 interrupt, csiphy_1_irq
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {511} // PHY 2 interrupt, csiphy_2_irq
})
Return (RBUF)
}
// PERF, EBUF left blank intentionally as only F state support required at this point.
// PEP Proxy is not needed as it is there for D state support.
}
//
// JPEG ENCODER (JPGE)
// JPEG 0: a dedicated JPEG encode instance;
// JPEG 3: a DMA instance (for downscaling only, not for encoding).
// Each JPEG instance is controlled indpendently; having its own set of
// registers for control and hardware operation, and its own core clock.
//
Device (JPGE)
{
Name (_DEP, Package(0x2)
{
\_SB_.CAMP,
\_SB_.MMU0
})
Name (_HID, "QCOM0276")
Name (_UID, 23)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// TITAN_A_JPEG_0
Memory32Fixed ( ReadWrite, 0x0AC4E000, 0x0340 )
// TITAN_A_JPEG_3
Memory32Fixed ( ReadWrite, 0x0AC52000, 0x01B4 )
// titan_jpeg_0_irq (Destination Subsystem: Application Processor)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 506 }
// titan_jpeg_3_irq (Destination Subsystem: Application Processor)
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 507 }
})
Return (RBUF)
}
Method (PERF)
{
Name (EBUF, Package()
{
Package() // JPEG instance 0 PSET_0
{
"COMPONENT",
0, // Component ID: JPEG_0 = 0, JPEG_3/DMA = 1
Package()
{
"PSTATE_SET",
0, // P_Set Index
0, // CLK = 0, BW = 1
"JPEG0_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
600000000, // cam_cc_jpeg_clk supported configurations (TURBO = NOM / SVS / Low SVS)
600000000,
404000000,
200000000,
},
},
},
Package() // JPEG instance 3 PSET_0
{
"COMPONENT",
1,
Package() { "PSTATE_SET", 0, 0, "DMA_CLK", Package() { "PSTATE", 0, 600000000, 600000000, 200000000, }, }, // cam_cc_jpeg_clk: Turbo / Nominal / LowSVS
},
})
Return (EBUF)
}
}
//
// VFE
//
Device (VFE0)
{
Name (_DEP, Package(0x3)
{
\_SB_.MMU0,
\_SB_.PEP0,
\_SB_.CAMP
})
Name (_HID, "QCOM0243")
Name (_UID, 22)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// ICP
Memory32Fixed (ReadWrite, 0xAC00000, 0x20000)
//CPASS_CDM
Memory32Fixed (ReadWrite, 0xAC48000, 0x1000)
//FD_WRAPPER
Memory32Fixed (ReadWrite, 0xAC5A000, 0x4000)
// LRME
Memory32Fixed (ReadWrite, 0xAC6B000, 0x1000)
//BPS
Memory32Fixed (ReadOnly, 0xAC6F000, 0x8000)
// IPE0
Memory32Fixed (ReadOnly, 0xAC87000, 0xA000)
// IPE1
Memory32Fixed (ReadOnly, 0xAC91000, 0xA000)
// IFE0
Memory32Fixed (ReadWrite, 0xACAF000, 0x5000)
//IFE1
Memory32Fixed (ReadWrite, 0xACB6000, 0x5000)
//IFE_LITE
Memory32Fixed (ReadWrite, 0xACC4000, 0x5000)
//ICP FW
Memory32Fixed (ReadWrite, 0x8BF00000, 0x500000)
// CDM interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {493}
// ICP interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {495}
// IFE0 interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {497}
// IFE1 interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {499}
// IFE LITE interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {501}
// FD interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {494}
// IFE0 CSID interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {496}
// IFE1 CSID interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {498}
// IFE LITE CSDI interrupt
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) {500}
})
Return (RBUF)
}
Method (PERF)
{
Name (EBUF, Package()
{
//------------------------------------------------------------------------------
// VFE and CPP P-state values listed here specific to Platform
// These packages enumerates all of the expected P-state values that should be used
// for the P-state transitions decision by VFE/CPP cores
// Package format is mentioned below.
//------------------------------------------------------------------------------
// Package()
// {
// "COMPONENT"
// INTEGER, VFE0/JPEG = 0,VFE1 = 1,CPP = 2
// Package()
// {
// "PSTATE_SET",
// PSTATE_INDEX_INTEGER, PStateIndex to access clocktable by index that contains Clock
// having PState.
// PSTATESET_TYPE_INTEGER, CLK = 0 , BW = 1
// STRING, ResourceName
// Package()
// {
// "PSTATE" , Package type mentioned in ACPIPackageNames
// INTEGER, Chipversion list availabiliy
//
// Clock values , Chipversion supported,
// Clock values , Chipversion supported,
// Clock values , Chipversion supported,
// },
// },
// },
Package()
{
"COMPONENT",
0, // IFE0
// Clk Freq
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK = 0 , BW = 1
"IFE0_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
480000000,
404000000,
0,
},
},
// BW: TODO
Package()
{
"PSTATE_SET",
1, // PStateSet Index
1, // CLK =0 , BW =1
"HF0_UNCOMP_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
38000000000,
35000000000,
28000000000,
23000000000,
20000000000,
16000000000,
14000000000,
12000000000,
4000000000,
3500000000,
3300000000,
3100000000,
2900000000,
2700000000,
2500000000,
2300000000,
2100000000,
1900000000,
1700000000,
1500000000,
1300000000,
1100000000,
900000000,
700000000,
500000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
Package()
{
"PSTATE_SET",
2, // PStateSet Index
1, // CLK =0 , BW =1
"HF0_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
38000000000,
35000000000,
28000000000,
23000000000,
20000000000,
16000000000,
14000000000,
12000000000,
4000000000,
3500000000,
3300000000,
3100000000,
2900000000,
2700000000,
2500000000,
2300000000,
2100000000,
1900000000,
1700000000,
1500000000,
1300000000,
1100000000,
900000000,
700000000,
500000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
// CSID Clk Freq: TODO
},
Package()
{
"COMPONENT",
1, // IFE1
// Clk Freq
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK = 0 , BW = 1
"IFE1_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
480000000,
404000000,
0,
},
},
// BW: TODO
Package()
{
"PSTATE_SET",
1, // PStateSet Index
1, // CLK =0 , BW =1
"HF1_UNCOMP_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
38000000000,
35000000000,
28000000000,
23000000000,
20000000000,
16000000000,
14000000000,
12000000000,
4000000000,
3500000000,
3300000000,
3100000000,
2900000000,
2700000000,
2500000000,
2300000000,
2100000000,
1900000000,
1700000000,
1500000000,
1300000000,
1100000000,
900000000,
700000000,
500000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
Package()
{
"PSTATE_SET",
2, // PStateSet Index
1, // CLK =0 , BW =1
"HF1_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
38000000000,
35000000000,
28000000000,
23000000000,
20000000000,
16000000000,
14000000000,
12000000000,
4000000000,
3500000000,
3300000000,
3100000000,
2900000000,
2700000000,
2500000000,
2300000000,
2100000000,
1900000000,
1700000000,
1500000000,
1300000000,
1100000000,
900000000,
700000000,
500000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
// CSID Clk Freq: TODO
},
Package()
{
"COMPONENT",
2, // IFE_LITE
// Clk Freq
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK = 0 , BW = 1
"IFE_LITE_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
480000000,
404000000,
0,
},
},
// BW: ICBID_MASTER_CAMNOC_HF1_UNCOMP is used for both ife1 & ife_lite
// CSID Clk Freq: TODO
},
Package()
{
"COMPONENT",
3, // ICP
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK =0 , BW =1
"ICP_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
400000000,
0,
},
},
// AHB Clk: TODO
},
Package()
{
"COMPONENT",
4, // IPE
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK =0 , BW =1
"IPE0_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
480000000,
404000000,
0,
},
},
Package()
{
"PSTATE_SET",
1, // PStateSet Index
0, // CLK =0 , BW =1
"IPE1_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
480000000,
404000000,
0,
},
},
// BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
// AHB Clk : TODO
},
Package()
{
"COMPONENT",
5, // BPS
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK =0 , BW =1
"BPS_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
480000000,
404000000,
0,
},
},
// BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
// AHB Clk : TODO
},
Package()
{
"COMPONENT",
6, // LRME
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK =0 , BW =1
"LRME_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
400000000,
320000000,
269000000,
0,
},
},
// BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
},
Package()
{
"COMPONENT",
7, // FD
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK =0 , BW =1
"FD_CLK",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
// Clock value Chipversion supported
600000000,
538000000,
400000000,
0,
},
},
// BW: ICBID_MASTER_CAMNOC_SF_UNCOMP is used for ipe, bps, jepg, fd, icp, lrme
},
})
Return (EBUF)
}
}

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//==============================================================================
// <cust_camera_exasoc.asl>
// DESCRIPTION
// This file contains resources (such as memory address, GPIOs, etc.) and
// methods needed by camera drivers for external components like sensors,flash etc.
// Customers can update these files for different external components
//
//==============================================================================
//
// CAMERA PLATFORM
//
Device (CAMP)
{
Name (_DEP, Package(0x3)
{
\_SB_.PEP0,
\_SB_.PMIC,
\_SB_.PMAP
})
Name (_HID, "QCOM026F")
Name (_UID, 27)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// TITAN_A_CPAS_0_CPAS_TOP_0
Memory32Fixed ( ReadWrite, 0x0AC40000, 0x0000006C )
// TITAN_A_CAMNOC
Memory32Fixed ( ReadWrite, 0x0AC42000, 0x00004E8C )
// TITAN_A_CCI
Memory32Fixed ( ReadWrite, 0x0AC4A000, 0x00000C1C )
// titan_cci_irq (Destination Subsystem: Application Processor)
Interrupt( ResourceConsumer, Edge, ActiveHigh, Exclusive, , , ) { 492 }
})
Return (RBUF)
}
//
// PLATFROM CONFIGURATION (PCFG) METHOD
//
// [1] SENSOR PRESENCE
// -----------------------|-----------/-----------|-----------/-----------|-----------/------------
// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX
// -----------------------|-----------/-----------|-----------/-----------|-----------/------------
// | SENSOR PRESENCE [0/1] | << FIELD MEANING
// RESERVED | 7 6 5 4 3 2 1 0 | << SENSOR INDEX
// -----------------------|-----------------------|-----------------------|-------------------------
// 0b | 0 0 0 0 0 1 1 1 | << 0x07
// -----------------------|-----------/-----------|-----------/-----------|-----------/------------
// SENSOR INDEX: 0(RFC), 1(FFC), 2(AUX), etc.
// SENSOR PRESENCE: 0 (ABSENT) / 1(PRESENTED)
// [2-9] SENSOR CONNECTION CONFIGURATION (here we only utilize three entires)
// -----------------------|-----------/-----------|-----------/-----------|-----------/------------
// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX
// -----------------------|-----------/-----------|-----------/-----------|-----------/------------
// RESERVED | CSI_PHY | I2C_BUS | RSVD | FL_INX |FP| DIR | ORI | << FIELD MEANING
// ------------------- --|-----------------------|-----------|--------|--|-----------|------------
// 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 << 0x00000100 (RFC)
// 0b 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 << 0x00210010 (FFC)
// 0b 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 << 0x00110300 (AUX/IRIS); REVISIT AND DOUBLE CHECK FLASH_INDEX !!!
// -----------------------|-----------/-----------|-----------/-----------|-----------/------------
// CSIPHY INDEX: 4-bit field, valid values 0/1/2, respectively CSIPHY_0/1/2 LD20-NE182-9
// I2C_BUS INDEX: 4-bit field, valid values 0/1, respectively CCI_I2C_SDA/SCL0/1 LD20-NE182-7/42
// FLASH_INDEX: 3-bit field, valid values 0/1/2, respectively FLASH_LED0/1/2 LD20-NE182-19/45
// FLASH_PRESENCE: 1-bit field, valid values 0/1, respectively ABSENT/PRESENTED
// SENSOR_DIRECTION: 4-bit field, valid values 0/1, respectively Rear/Front
// SENSOR_ORIENTATION: 4-bit field, valid values 0/1/2/3 respectively 0/90/180/270 degrees
Method (PCFG, 0x0, Serialized)
{
Return
(
Package()
{
Package ()
{
0x00000007, // [1] SENSOR PRESENCE
0x00000102, // [2] SENSOR_0/RFC CONNECTION
0x00210010, // [3] SENSOR_1/FFC CONNECTION
0x00110310, // [4] SENSOR_2/AUX/IRIS CONNECTION
0x00000000, // [5] SENSOR_3 CONNECTION; RESERVED
0x00000000, // [6] SENSOR_4 CONNECTION; RESERVED
0x00000000, // [7] SENSOR_5 CONNECTION; RESERVED
0x00000000, // [8] SENSOR_6 CONNECTION; RESERVED
0x00000000 // [9] SENSOR_7 CONNECTION; RESERVED
}
}
)
}
// The method contains P state power setting used by the camera driver. The clock presented
// here MUST be consistent with the PSTATE_SET values under the CAMP section in the file of
// cust_camera_exasoc_resources.asl.
Method (PERF)
{
Name (EBUF, Package()
{
Package()
{
"COMPONENT",
0, // Platform = 0
Package()
{
"PSTATE_SET",
0, // PStateSet Index
0, // CLK = 0, BW = 1
"CAMP_CLK",
Package() // The indexes and frequencies be consistent
{ // with CCICLKFrqIdx in CCIResourceType.h and
"PSTATE", // cam_cc_cci_clk in cust_camera_exasoc_resources.asl
0, // Chipversion list availabiliy
37500000, // Index 0 clock
19200000, // Index 1 clock
},
},
Package()
{
"PSTATE_SET",
1, // PStateSet Index
1, // CLK =0 , BW =1
"NRT_UNCOMP_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
12000000000,
11500000000,
11000000000,
10500000000,
10000000000,
9500000000,
9000000000,
8500000000,
8000000000,
7500000000,
7000000000,
6500000000,
6000000000,
5500000000,
5000000000,
4500000000,
4000000000,
3500000000,
3300000000,
3100000000,
2900000000,
2700000000,
2500000000,
2300000000,
2100000000,
1900000000,
1700000000,
1500000000,
1300000000,
1100000000,
900000000,
700000000,
500000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
Package()
{
"PSTATE_SET",
2, // PStateSet Index
1, // CLK =0 , BW =1
"NRT_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
12000000000,
11500000000,
11000000000,
10500000000,
10000000000,
9500000000,
9000000000,
8500000000,
8000000000,
7500000000,
7000000000,
6500000000,
6000000000,
5500000000,
5000000000,
4500000000,
4000000000,
3500000000,
3300000000,
3100000000,
2900000000,
2700000000,
2500000000,
2300000000,
2100000000,
1900000000,
1700000000,
1500000000,
1300000000,
1100000000,
900000000,
700000000,
500000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
},
Package()
{
"COMPONENT",
1, // Platform = 0
Package()
{
"PSTATE_SET",
0, // PStateSet Index
1, // CLK =0 , BW =1
"HF0_UNCOMP_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
1100000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
Package()
{
"PSTATE_SET",
1, // PStateSet Index
1, // CLK =0 , BW =1
"HF0_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
1100000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
Package()
{
"PSTATE_SET",
2, // PStateSet Index
1, // CLK =0 , BW =1
"NRT_UNCOMP_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
1100000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
Package()
{
"PSTATE_SET",
3, // PStateSet Index
1, // CLK =0 , BW =1
"NRT_BANDWIDTH",
Package()
{
"PSTATE",
0, // Chipversion list availabiliy
1100000000,
400000000,
300000000,
200000000,
100000000,
0,
},
},
},
})
Return (EBUF)
}
}
//
// Primary Rear Camera (IMX318)
//
Device (CAMS)
{
Name (_DEP, Package(0x1)
{
\_SB_.MPCS // MPCS has dependency on CAMP, which eventually ends up with PEP0 and PMIC
})
Name (_HID, "QCOM0245")
Name (_UID, 21)
// Return 0x0 to disable CAMS sensor
Method (_STA)
{
Return (0xf)
}
//
// SENSOR CONFIGURATION (SCFG) METHOD
//
// [1/2] Driver/Tuning binary file name (no more than 50 characters)
//
// [3] I2C Slave Information for Sensor Probing
//------------------------|-----------/-----------|-----------------------|------------------------
// 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 | << BIT INDEX
// RESERVED | DTT | ADT | FRQ | SLAVE ADDRESS | << MEANING
// -----------------------------|-----|-----|-----|------------------------------------------------
// 0b 0 1 0 1 0 1 FROM IMX318 REG MAP | << 0x150034
// -----------------------|-----------/-----------|-----------------------|-----------/------------
// Register Data Type (DTT): 0b00 -- CAMERA_I2C_BYTE_DATA, 0b01 -- WORD, 0b10 -- DWORD
// Register Address Type (ADT): 0b00 -- CAMERA_I2C_BYTE_ADDR, 0b01 -- WORD, 0b10 -- 3B
// I2C Frequency mode: 0b00 -- 100 KHz (standard), 0b01 -- 400 KHz (fast), 0b10 -- 1 MHz (fast_plus).
//
// [4] Slave Data Part 1 for and from Probing
// Expected Reading (16 bits; 0x318) + Register Address (16 bits; 0x16)
//
// [5] Slave Data Part 2 for and from Probing
// Same format as above; Reserved for Revision # (if applied)
Method (SCFG, 0x0, Serialized)
{
Return
(
Package()
{
Package ()
{
"com.qti.sensormodule.liteon_imx318.bin", // [1] Driver binary file name
"com.qti.tuned.liteon_imx318.bin", // [2] Tuning binary file name
0x00150034, // [3] I2C Slave Information for Sensor Probing
0x03180016, // [4] Slave Data Part 1 for and from Probing
0x00000000 // [5] Slave Data Part 2 for and from Probing; Reserved
}
}
)
}
// PEP Proxy Support
Name(PGID, Buffer(10) {"\\_SB.CAMS"}) // Device ID buffer - PGID (Pep given ID)
Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID)
CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
// HIDDEN 1 BYTE (SIZE)
CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status
CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits)
Method (_S1D, 0) { Return (3) } // S1 => D3
Method (_S2D, 0) { Return (3) } // S2 => D3
Method (_S3D, 0) { Return (3) } // S3 => D3
Method(_PS0, 0x0, NotSerialized)
{
Store(Buffer(ESNL){}, DEID)
Store(0, DVAL)
Store(PGID, DEID)
If(\_SB.ABD.AVBL)
{
Store(DBUF, \_SB.PEP0.FLD0)
}
}
Method(_PS3, 0x0, NotSerialized)
{
Store(Buffer(ESNL){}, DEID)
Store(3, DVAL)
Store(PGID, DEID)
If(\_SB.ABD.AVBL)
{
Store(DBUF, \_SB.PEP0.FLD0)
}
}
}
//
// Primary Front Camera (IMX258)
//
Device (CAMF)
{
Name (_DEP, Package(0x1)
{
\_SB_.MPCS
})
Name (_HID, "QCOM024A")
Name (_UID, 26)
// Return 0x0 to disable CAMF sensor
Method (_STA)
{
Return (0xf)
}
Method (SCFG, 0x0, Serialized)
{
Return
(
Package()
{
Package ()
{
"com.qti.sensormodule.semco_imx258.bin",
"com.qti.tuned.semco_imx258.bin",
0x00150034, // I2C Slave Info for Probing, primary address 0x34, secondary 0x20
0x02580016,
0x00000000
}
}
)
}
// PEP Proxy Support
Name(PGID, Buffer(10) {"\\_SB.CAMF"}) // Device ID buffer - PGID (Pep given ID)
Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID)
CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
// HIDDEN 1 BYTE (SIZE)
CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status
CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits)
Method (_S1D, 0) { Return (3) } // S1 => D3
Method (_S2D, 0) { Return (3) } // S2 => D3
Method (_S3D, 0) { Return (3) } // S3 => D3
Method(_PS0, 0x0, NotSerialized)
{
Store(Buffer(ESNL){}, DEID)
Store(0, DVAL)
Store(PGID, DEID)
If(\_SB.ABD.AVBL)
{
Store(DBUF, \_SB.PEP0.FLD0)
}
}
Method(_PS3, 0x0, NotSerialized)
{
Store(Buffer(ESNL){}, DEID)
Store(3, DVAL)
Store(PGID, DEID)
If(\_SB.ABD.AVBL)
{
Store(DBUF, \_SB.PEP0.FLD0)
}
}
}
//
// Auxiliary sensor (OV2281, IRIS)
//
Device (CAMI)
{
Name (_DEP, Package(0x1)
{
\_SB_.MPCS
})
Name (_HID, "QCOM0247")
Name (_UID, 28)
// Return 0x0 to disable CAMI sensor
Method (_STA)
{
Return (0xf)
}
Method (SCFG, 0x0, Serialized)
{
Return
(
Package()
{
Package ()
{
"com.qti.sensormodule.sunny_ov2281.bin",
"UPDATEME.bin", // NEED UPDATE!!!
0x00150020,
0x0056300A,
0x00000000
}
}
)
}
// PEP Proxy Support
Name(PGID, Buffer(10) {"\\_SB.CAMI"}) // Device ID buffer - PGID (Pep given ID)
Name(DBUF, Buffer(DBFL) {}) // Device ID buffer - PGID (Pep given ID)
CreateByteField(DBUF, 0x0, STAT) // STATUS 1 BYTE
// HIDDEN 1 BYTE (SIZE)
CreateByteField(DBUF, 2, DVAL) // Packet value, 1 BYTES Device Status
CreateField(DBUF, 24, 160, DEID) // Device ID, 20 BYTES (160 Bits)
Method (_S1D, 0) { Return (3) } // S1 => D3
Method (_S2D, 0) { Return (3) } // S2 => D3
Method (_S3D, 0) { Return (3) } // S3 => D3
Method(_PS0, 0x0, NotSerialized)
{
Store(Buffer(ESNL){}, DEID)
Store(0, DVAL)
Store(PGID, DEID)
If(\_SB.ABD.AVBL)
{
Store(DBUF, \_SB.PEP0.FLD0)
}
}
Method(_PS3, 0x0, NotSerialized)
{
Store(Buffer(ESNL){}, DEID)
Store(3, DVAL)
Store(PGID, DEID)
If(\_SB.ABD.AVBL)
{
Store(DBUF, \_SB.PEP0.FLD0)
}
}
}
//
// CAMERA WHITE LED FLASH
//
Device (FLSH)
{
Name (_DEP, Package(0x1)
{
\_SB_.CAMP
})
Name (_HID, "QCOM025C")
Name (_UID, 25)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// "GPIO Interrupt Connection Resource Descriptor Macro" Format (ACPI $19.5.53):
// GpioInt (EdgeLevel, ActiveLevel, Shared, PinConfig, DebounceTimeout, ResourceSource,
// ResourceSourceIndex, ResourceUsage, DescriptorName, VendorData) {PinList}
})
Return (RBUF)
}
}

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//===========================================================================
// <cust_camera_exasoc_resources.asl>
// DESCRIPTION
// This file contains the resources needed by camera drivers for external components like sensors,flash etc.
// Customers can update these files for different external components.
//
// [1] Refer Table 3-10 "Titan 170 Power Use Cases" in "Titan Camera
// Hardware Architecture Specification" for the detailed information on
// the operating points under different use case scenarios. Based on
// the information in the table, this ACPI planned to support SVS and
// NOM frequencies.
//
// [2] Refer Chapter 2 "Defintions of Terms" in the ACPI Specification for
// the definitions of D, F, and P states. Refer the manual of PEP
// driver for the syntax of defining the power and clock resources.
//
// [3] ACPI keeps 2 mA for most GPIO pins by setting the field of
// "PullDriveStrength" to 0 on TLMMGPIO. For high frequency clock pins
// (such as cam_mclk0/1/2/3 running at 24 MHz), the strength shall be
// set to 6 mA to meet the timing requirement.
//
//===========================================================================
// Placeholder only, NOT WORKING yet!
Scope(\_SB_.PEP0)
{
// Exa-SoC Devices
Method(CPMX)
{
Return (CPXC)
}
Name(CPXC,
Package ()
{
// Flash device (ISRC_R/G/B_LED, ISRC_FLASH_1/2/3)
Package()
{
"DEVICE",
"\\_SB.FLSH",
Package()
{
"COMPONENT",
0x0, // Component ID
Package() { "FSTATE", 0x0, }, // Dummy F0
Package() { "FSTATE", 0x1, }, // Dummy F1
},
},
// Device CAMP Data
Package()
{
"DEVICE",
"\\_SB.CAMP",
Package()
{
"COMPONENT",
0x0, // Component 0
Package()
{
"FSTATE",
0x0, // F0 state (fully on)
// FORMAT: FOOTSWITCH NAME; ACTION: 1 == ENABLE, 2 == DISABLE, 3 == HW_CONTROL_ENABLE, 4 == HW_CONTROL_
// DISABLE. When the ACTION field is set to 1, the CLOCK driver shall set SW_COLLAPSE bit to 1 (which
// means DISABLING/NO SW_COLLAPSE) and poll PWR_ON bit on TITAN_CAM_CC_TITAN_TOP_GDSCR register (as
// inidicated in "$2.3.1.4 Core Power On Sequence" of Titan HPG). The CLOCK driver MUST ensure that
// the power domain has been enabled before returning. It shall be a blocking operation. If a HW block
// (e.g., IPE) is involved, use 3/4 to enable/disable it. HW ENABLING always overrides other settings.
package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
Package() { "PSTATE_ADJUST", Package() { 1, 35 } }, // Set to 2nd lowest BW, need revisit
Package() { "PSTATE_ADJUST", Package() { 2, 35 } }, // Set to 2nd lowest BW, need revisit
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
// Action: 1 == ENABLE, 2 == DISABLE, 3 == SET_FREQ, 8 == ENABLE_SET_FREQ, 9 == CONFIGURE,
// 12 == Disable and Set Frequency (combines actions 2 & 3)(must pair with 8)
// Match_Type: 1 == CLOCK_FREQUENCY_HZ_AT_LEAST, 3 == CLOCK_FREQUENCY_HZ_CLOSEST
// -----------------------------------------------------------------------------------------------------
// CLOCK Clock Name Action Freq (Hz) MatchType
// -----------------------------------------------------------------------------------------------------
package() { "CLOCK", package() { "cam_cc_cci_clk", 1} }, // Func: CCI. For CCI operations.
// Valid only in F-State; Used to adjust one or more current P-State within their respective P-State
// Sets. In this case, it will adjust to P state 0 in PSET 0 (to set cam_cc_cci_clk to 37.5 MHz).
Package() { "PSTATE_ADJUST", Package() { 0, 0 } },
// -----------------------------------------------------------------------------------------------------
// GPIO PIN (Refer CAMS TLMMGPIO) Pin|State|FuncSel|Dirc|PullType|DriveStrength
// -----------------------------------------------------------------------------------------------------
// Camera CCI 0/1
package() { "TLMMGPIO", package() { 17, 1, 1, 1, 3, 0, }, }, // cci_i2c_sda0
package() { "TLMMGPIO", package() { 18, 1, 1, 1, 3, 0, }, }, // cci_i2c_scl0
package() { "TLMMGPIO", package() { 19, 1, 1, 1, 3, 0, }, }, // cci_i2c_sda1
package() { "TLMMGPIO", package() { 20, 1, 1, 1, 3, 0, }, }, // cci_i2c_scl1
// Camera MCLK
package() { "TLMMGPIO", package() { 13, 1, 1, 1, 0, 2, }, }, // cam_mclk0, for CAM0/RFC/IMX318
package() { "TLMMGPIO", package() { 14, 1, 1, 1, 0, 2, }, }, // cam_mclk1, for CAM1/FFC/IMX258
package() { "TLMMGPIO", package() { 15, 1, 1, 1, 0, 2, }, }, // cam_mclk2, unused
package() { "TLMMGPIO", package() { 16, 1, 1, 1, 0, 2, }, }, // cam_mclk3, for CAM2/IRIS/OV2281
},
Package()
{
"FSTATE",
0x1, // F1 state (OFF)
package() { "TLMMGPIO", package() { 16, 0, 0, 0, 1, 2, }, },
package() { "TLMMGPIO", package() { 15, 0, 0, 0, 1, 2, }, },
package() { "TLMMGPIO", package() { 14, 0, 0, 0, 1, 2, }, },
package() { "TLMMGPIO", package() { 13, 0, 0, 0, 1, 2, }, },
package() { "TLMMGPIO", package() { 20, 0, 0, 0, 1, 0, }, },
package() { "TLMMGPIO", package() { 19, 0, 0, 0, 1, 0, }, },
package() { "TLMMGPIO", package() { 18, 0, 0, 0, 1, 0, }, },
package() { "TLMMGPIO", package() { 17, 0, 0, 0, 1, 0, }, },
package() { "CLOCK", package() { "cam_cc_cci_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
Package() { "PSTATE_ADJUST", Package() { 2, 37 } },
Package() { "PSTATE_ADJUST", Package() { 1, 37 } },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
},
// This packet contains P state power setting used by the PEP driver. The clock presented here
// MUST be consistent with the clock values under the PERF method in the file of cust_camera_exasoc.asl.
Package()
{
"PSTATE_SET",
0,
// Format: name / action / freq / match_type. The driver shall select the lowest frequency required to perform the task at the acceptable performance
// point. HPG recommends to limit the freq under 50 MHz. It is allowed to have multiple clock resources in one PSTATE package. The indexes and
// frequencies MUST be consistent with CCICLKFrqIdx in CCIResourceType.h and CAMP_CLK in cust_camera_exasoc.asl.
Package() { "PSTATE", 0, package() { "CLOCK", package() { "cam_cc_cci_clk", 3, 37500000, 3, } }, }, // LowSVS for all speeds from 100 KHz to 1 MHz.
Package() { "PSTATE", 1, package() { "CLOCK", package() { "cam_cc_cci_clk", 3, 19200000, 3, } }, }, // MinSVS, not used.
},
Package()
{
"PSTATE_SET", // PSET 1: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth); Driver limits the MaxComponentNameLen number as 40.
1,
// Format: Type-3 Bus Arbiter Req | Master Name | Slave Name | IB in bytes/sec | AB
Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 12000000000, 12000000000 } }, },
Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 11500000000, 11500000000 } }, },
Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 11000000000, 11000000000 } }, },
Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 10500000000, 10500000000 } }, },
Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 10000000000, 10000000000 } }, },
Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 9500000000, 9500000000 } }, },
Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 9000000000, 9000000000 } }, },
Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 8500000000, 8500000000 } }, },
Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 8000000000, 8000000000 } }, },
Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 7500000000, 7500000000 } }, },
Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 7000000000, 7000000000 } }, },
Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 6500000000, 6500000000 } }, },
Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 6000000000, 6000000000 } }, },
Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 5500000000, 5500000000 } }, },
Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 5000000000, 5000000000 } }, },
Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4500000000, 4500000000 } }, },
Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 4000000000, 4000000000 } }, },
Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3500000000, 3500000000 } }, },
Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3300000000, 3300000000 } }, },
Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 3100000000, 3100000000 } }, },
Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2900000000, 2900000000 } }, },
Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2700000000, 2700000000 } }, },
Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2500000000, 2500000000 } }, },
Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2300000000, 2300000000 } }, },
Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 2100000000, 2100000000 } }, },
Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1900000000, 1900000000 } }, },
Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1700000000, 1700000000 } }, },
Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1500000000, 1500000000 } }, },
Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1300000000, 1300000000 } }, },
Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } }, },
Package() { "PSTATE", 30, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 900000000, 900000000 } }, },
Package() { "PSTATE", 31, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 700000000, 700000000 } }, },
Package() { "PSTATE", 32, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 500000000, 500000000 } }, },
Package() { "PSTATE", 33, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } }, },
Package() { "PSTATE", 34, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } }, },
Package() { "PSTATE", 35, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } }, },
Package() { "PSTATE", 36, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } }, },
Package() { "PSTATE", 37, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } }, },
},
Package()
{
"PSTATE_SET", // PSET 2: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth)
2,
// Format: Type-3 Bus Arbiter Req | Master Name | Slave Name | IB in bytes/sec | AB
Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 12000000000, 12000000000 } }, },
Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 11500000000, 11500000000 } }, },
Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 11000000000, 11000000000 } }, },
Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 10500000000, 10500000000 } }, },
Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 10000000000, 10000000000 } }, },
Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 9500000000, 9500000000 } }, },
Package() { "PSTATE", 6, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 9000000000, 9000000000 } }, },
Package() { "PSTATE", 7, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 8500000000, 8500000000 } }, },
Package() { "PSTATE", 8, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 8000000000, 8000000000 } }, },
Package() { "PSTATE", 9, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 7500000000, 7500000000 } }, },
Package() { "PSTATE", 10, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 7000000000, 7000000000 } }, },
Package() { "PSTATE", 11, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 6500000000, 6500000000 } }, },
Package() { "PSTATE", 12, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 6000000000, 6000000000 } }, },
Package() { "PSTATE", 13, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 5500000000, 5500000000 } }, },
Package() { "PSTATE", 14, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 5000000000, 5000000000 } }, },
Package() { "PSTATE", 15, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 4500000000, 4500000000 } }, },
Package() { "PSTATE", 16, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 4000000000, 4000000000 } }, },
Package() { "PSTATE", 17, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3500000000, 3500000000 } }, },
Package() { "PSTATE", 18, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3300000000, 3300000000 } }, },
Package() { "PSTATE", 19, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 3100000000, 3100000000 } }, },
Package() { "PSTATE", 20, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2900000000, 2900000000 } }, },
Package() { "PSTATE", 21, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2700000000, 2700000000 } }, },
Package() { "PSTATE", 22, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2500000000, 2500000000 } }, },
Package() { "PSTATE", 23, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2300000000, 2300000000 } }, },
Package() { "PSTATE", 24, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 2100000000, 2100000000 } }, },
Package() { "PSTATE", 25, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1900000000, 1900000000 } }, },
Package() { "PSTATE", 26, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1700000000, 1700000000 } }, },
Package() { "PSTATE", 27, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1500000000, 1500000000 } }, },
Package() { "PSTATE", 28, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1300000000, 1300000000 } }, },
Package() { "PSTATE", 29, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } }, },
Package() { "PSTATE", 30, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 900000000, 900000000 } }, },
Package() { "PSTATE", 31, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 700000000, 700000000 } }, },
Package() { "PSTATE", 32, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 500000000, 500000000 } }, },
Package() { "PSTATE", 33, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 400000000, 400000000 } }, },
Package() { "PSTATE", 34, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 300000000, 300000000 } }, },
Package() { "PSTATE", 35, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 200000000, 200000000 } }, },
Package() { "PSTATE", 36, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 100000000, 100000000 } }, },
Package() { "PSTATE", 37, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 0, 0 } }, },
},
},
Package()
{
"COMPONENT",
0x1, // Component 1
Package()
{
"FSTATE",
0x0, // F0 state (fully on)
package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
Package() { "PSTATE_ADJUST", Package() { 3, 4 } },
Package() { "PSTATE_ADJUST", Package() { 2, 4 } },
Package() { "PSTATE_ADJUST", Package() { 1, 4 } },
Package() { "PSTATE_ADJUST", Package() { 0, 4 } },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
package() { "CLOCK", package() { "cam_cc_cci_clk", 1} }, // Func: CCI. For CCI operations.
},
Package()
{
"FSTATE",
0x1, // F1 state (OFF)
package() { "CLOCK", package() { "cam_cc_cci_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
Package() { "PSTATE_ADJUST", Package() { 0, 5 } },
Package() { "PSTATE_ADJUST", Package() { 1, 5 } },
Package() { "PSTATE_ADJUST", Package() { 2, 5 } },
Package() { "PSTATE_ADJUST", Package() { 3, 5 } },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_xo_clk", 2} },
},
Package()
{
"PSTATE_SET",
0,
Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } } },
Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } } },
Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } } },
Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } } },
Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } } },
Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } } },
},
// BW - compressed
Package()
{
"PSTATE_SET",
1,
Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } } },
Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 400000000, 400000000 } } },
Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 300000000, 300000000 } } },
Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 200000000, 200000000 } } },
Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 100000000, 100000000 } } },
Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_HF0", "ICBID_SLAVE_EBI1", 0, 0 } } },
},
// Moved BW from CAMP to here. this is temporary.
Package()
{
"PSTATE_SET", // PSET 3: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth)
2,
Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 1100000000, 1100000000 } }, },
Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 400000000, 400000000 } }, },
Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 300000000, 300000000 } }, },
Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 200000000, 200000000 } }, },
Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 100000000, 100000000 } }, },
Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF_UNCOMP", "ICBID_SLAVE_CAMNOC_UNCOMP", 0, 0 } }, },
},
// Moved BW from CAMP to here. this is temporary.
Package()
{
"PSTATE_SET", // PSET 3: Bandwidth adjustments (Type 3: Instantaneous and Arbitrated bandwidth)
3,
Package() { "PSTATE", 0, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 1100000000, 1100000000 } }, },
Package() { "PSTATE", 1, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 400000000, 400000000 } }, },
Package() { "PSTATE", 2, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 300000000, 300000000 } }, },
Package() { "PSTATE", 3, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 200000000, 200000000 } }, },
Package() { "PSTATE", 4, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 100000000, 100000000 } }, },
Package() { "PSTATE", 5, Package() { "BUSARB", Package() { 3, "ICBID_MASTER_CAMNOC_SF", "ICBID_SLAVE_EBI1", 0, 0 } }, },
},
},
Package()
{
"COMPONENT",
0x2, // Component 2 (SHARED_RES: AFVDD)
Package()
{
"FSTATE",
0x0, // F0 state (fully on)
// CAM1_STBY_N / CAM_ELDO3_EN (AF_VDD LDO Enable All Cameras)
// VIN_PM8998 - VIN_PMI8998 - BOB - ELDO3 - AF_VDD; LD20-NE182-7-C6;
// Format: Pin|State|FuncSel|Dirc|PullType|DriveStrength
package() { "TLMMGPIO", package() { 27, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
},
Package()
{
"FSTATE",
0x1, // F1 state (OFF)
// AF_VDD OFF
package() { "TLMMGPIO", package() { 27, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
},
},
},
// Primary RFC (IMX318) Power Setting Array from imx318_lib.h (sensor vendor supplied). Mapping
// between lib and IP_CAT: VDIG (DVDD), VIO (DOVDD), VANA (AVDD), VAF (AF_VDD). Sony IMX318
// Application Note (AN): During power on, VANA, VDIG, and VIF may rise in any order. The XCLR
// pin needs to be LOW until all power supplies complete power-on. During power off, VANA, VDIG,
// and VIF may fall in any order. For delays, refer AN "Startup sequence timing constraints"
// and "Power down sequence timing constraints".
Package()
{
"DEVICE",
"\\_SB.CAMS",
Package()
{
"DSTATE",
0x0, // D0 state (ON)
package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
// [1] TLMM_GPIO: set CAM0_RST_N to LOW; LD20-NE182-8-C5
package()
{
"TLMMGPIO", // Identifier: PMIC GPIO. Top Level Mode Mux (TLMM)
package()
{
80, // Pin Number: CAM0_RST_N (Primary RFC)
0, // State / OutVal: 0 == Low, 1 == High
0, // Function Select: 0 == Generic I/O Pin, non-zero == Alternate Function
1, // Direction: 0 == Input, 1 == Output
0, // Pull Type: 0 == No Pull, 1 == Pull Down, 2 == Keeper, 3 == Pull Up
0, // Strength: 0 == 2 mA, 1 == 4 mA, 2 == 6 mA, 3 == 8 mA, 4 == 10 mA, 5 == 12 mA, 4 == 14 mA, 7 == 16 mA
},
},
package() { "DELAY", package() { 1, }, }, // 1 ms(millisecond) delay
// [2] TLMM_GPIO: VIN_PM8998 - VIN_PMI8998 - BOB - ELDO9 - AVDD (VANA); CAM0_STBY_N / CAM_ELDO9_EN;
// Primary Rear Camera AVDD LDO Enable. LD20-NE182-8-C5. L22A, IMX318_AVDD_ALT is not used.
package() { "TLMMGPIO", package() { 79, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [3] PMIC_GPIO: VIN_PM8998 - S3A - ELDO1 - DVDD; LD20-NE182-27-A6/41-D7
package()
{
"PMICGPIO",
package()
{
"IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT",
0, // PMIC Number: 0 == PM8998, 1 == PMI8998, 2 == PM8005
11, // GPIO Number: PM_GPIO_12 / CAM_ELDO1_EN
0, // Out Buffer Config: 0 == PM_GPIO_OUT_BUFFER_CONFIG_CMOS, 1 == NMOS, 2 == CMOS
1, // VIN: 0 == PM_GPIO_VIN0, 1 == VIN1
1, // Source: 0 == PM_GPIO_SOURCE_LOW, 1 == HIGH, 2 == PAIRED_GPIO, 3-4 == SPECIAL_FUNCTION1-2, 5-8 == DTEST1-4
3, // Out Buffer Strength: 0 == PM_GPIO_OUT_BUFFER_RESERVED, 1 == LOW, 2 == MEDIUM, 3 == HIGH
0, // I Source Pull: 0 == PM_GPIO_I_SOURCE_PULL_UP_30uA, 1 == UP_1_5uA, 2 == UP_31_5uA, 3 == UP_1_5uA_PLUS_30uA_BOOST, 4 == DOWN_10uA, 5 == NO_PULL
},
},
package() { "DELAY", package() { 1, }, },
// [4] PMIC_VREG_VOTE: VIN_PM8998 - S4A - VIN_LVS1_LVS2 - LVS1A - DOVDD. LD20-NE182-41-B4.
// Regulator name from //deploy/qcom/qct/platform/wpci/prod/woa/QCDK/main/latest/inc/pmic/PmicIVreg.h
package()
{
"PMICVREGVOTE", // Identifier: PMIC VREG Resource
package()
{
"PPP_RESOURCE_ID_LVS1_A", // Voltage Regulator ID (Type VS)
4, // TYPE of VREG: 4 == LVS (Low Voltage Switch), 5 == MVS (Medium Voltage Switch)
1800000, // Voltage: 1.8 V
1, // Software Enable: 0 == Disable, 1 == Enable (Recommended)
// "HLOS_DRV", // Optional: DRV ID (Default: HLOS_DRV; Valid: HLOS_DRV / DISPLAY_DRV)
// "REQUIRED", // Optional: Suppressible Type (Default: REQUIRED; Valid: REQUIRED / SUPPRESSIBLE)
},
},
// [5] CLOCK; LD20-NE182-45-D4
package() { "CLOCK", package() { "cam_cc_mclk0_clk", 8, 24000000, 3, } }, // Frequency from imx318_lib.h
package() { "DELAY", package() { 1, }, },
// [6] TLMM_GPIO: set CAM0_RST_N to HIGH
package() { "TLMMGPIO", package() { 80, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 18, }, }, // 18 ms wait time between XCLR rising and sending streaming command
},
Package()
{
"DSTATE",
0x3, // D3 state (OFF)
// [1] CLOCK OFF
package() { "CLOCK", package() { "cam_cc_mclk0_clk", 2} },
package() { "DELAY", package() { 1, }, },
// [2] CAM0_RST_N LOW
package() { "TLMMGPIO", package() { 80, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [3] DOVDD OFF
package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, },
// [4] DVDD OFF
package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 11, 0, 1, 0, 3, 0, }, },
package() { "DELAY", package() { 1, }, },
// [5] AVDD (VANA) OFF
package() { "TLMMGPIO", package() { 79, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
},
},
// Primary FFC (IMX258) Power Setting Array from imx258_lib.h. Sony IMX258 Application Note: During
// power on, VANA, VDIG, and VIF may rise in any order. The XCLR pin is set to "LOW" and the power
// suppliers are brought up. Then the XCLR pin should be set to "HIGH" after INCK supplied. During
// power off, VANA, VDIG, and VIF may fall in any order. For delays, refer AN "Startup sequence
// timing constraints" and "Power down sequence timing constraints".
Package()
{
"DEVICE",
"\\_SB.CAMF",
Package()
{
"DSTATE",
0x0,
package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1} },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1} },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
// [1] TLMM_GPIO: set CAM1_RST_N to LOW; LD20-NE182-7-C6
package() { "TLMMGPIO", package() { 28, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [2] TLMM_GPIO: VIN_PM8998 - VIN_PMI8998 - BOB - ELDO2 (GPIO_8 / CAM_ELDO2_EN / Front Camera AVDD LDO Enable) - AVDD (VANA); LD20-NE182-41-C7
package() { "TLMMGPIO", package() { 8, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [3] PM_IC_GPIO: VIN_PM8998 - S3A - ELDO4 ( PM_GPIO_09 / CAM_ELDO4_EN / Camera Front DVDD LDO Enable) - DVDD; LD20-NE182-41-B6
package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 1, 3, 0, }, },
package() { "DELAY", package() { 1, }, },
// [4] PM_IC_VREG_VOTE: VIN_PM8998 - S4A - VIN_LVS1_LVS2 - LVS1A - DOVDD; LD20-NE182-41-B4
package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 1800000, 1, }, },
// [5] CLOCK; LD20-NE182-43-C2
package() { "CLOCK", package() { "cam_cc_mclk1_clk", 8, 24000000, 3, } },
package() { "DELAY", package() { 1, }, },
// [6] TLMM_GPIO: set CAM1_RST_N to HIGH; LD20-NE182-7-C6
package() { "TLMMGPIO", package() { 28, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 12, }, }, // Delay between INCK-start-and-XCLR-rising and Sending-streaming-command
},
Package()
{
"DSTATE",
0x3,
// [1] CAM1_RST_N LOW
package() { "TLMMGPIO", package() { 28, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [2] CLOCK OFF
package(){ "CLOCK", package(){ "cam_cc_mclk1_clk", 2} },
package() { "DELAY", package() { 1, }, },
// [3] DOVDD OFF
package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, },
// [4] DVDD OFF
package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 0, 3, 0, }, },
package() { "DELAY", package() { 1, }, },
// [5] AVDD (VANA) OFF
package() { "TLMMGPIO", package() { 8, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
},
},
// FFC Auxiliary (OV2281) Power Setting Array from ov2281_lib.h. Refer OV2281 datasheet
// "power up sequence", figure 2-3, "power down sequence", and figure 2-6 for more
// information.
Package()
{
"DEVICE",
"\\_SB.CAMI",
Package()
{
"DSTATE",
0x0,
package() { "CLOCK", package() { "gcc_camera_xo_clk", 1} },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 1} },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 1} },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 1} },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 1 } }, // AHB clock for all register access within the JPEG core; SVS
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 1 } }, // Same as above; SVS
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 1} }, // For DDR access through CAMNOC
// [1] VIO / DOVDD - VREG_LVS1A_1P8 (All camera 1.8 V IO); PM_IC_VREG_VOTE; LD20-NE182-41-B4, 42-D6
package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 1800000, 1, }, },
// [2] AVDD 2.8 V - P2V85_AVDD_CAM1_2; LD20-NE182-41-C5, 42-D6; TLMM_GPIO: ELDO2 (GPIO_8 / CAM_ELDO2_EN / Front Camera AVDD LDO Enable / CAM2_STBY_N)
package() { "TLMMGPIO", package() { 8, 1, 0, 1, 0, 0, }, },
// [3] VDD 1.2 V - P1V2_DVDD_CAM1_2; PM_IC_GPIO: ELDO4 ( PM_GPIO_09 / CAM_ELDO4_EN / Camera Front DVDD LDO Enable) - DVDD; LD20-NE182-41-B6
package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 1, 3, 0, }, },
// [4] CAM2_RST_N LOW (AUX1, 3rd camera in system); LD20-NE182-7-D6
package() { "TLMMGPIO", package() { 9, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [5] CAM2_RST_N HIGH
package() { "TLMMGPIO", package() { 9, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [6] CLOCK; LD20-NE182-42-C6
package() { "CLOCK", package() { "cam_cc_mclk3_clk", 8, 24000000, 3, } },
package() { "DELAY", package() { 1, }, },
},
Package()
{
"DSTATE",
0x3,
// [1] CLOCK OFF
package(){ "CLOCK", package(){ "cam_cc_mclk3_clk", 2} },
package() { "DELAY", package() { 1, }, },
// [2] CAM2_RST_N HIGH
package() { "TLMMGPIO", package() { 9, 1, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [3] CAM2_RST_N LOW
package() { "TLMMGPIO", package() { 9, 0, 0, 1, 0, 0, }, },
package() { "DELAY", package() { 1, }, },
// [4] VDD OFF
package() { "PMICGPIO", package() { "IOCTL_PM_GPIO_CONFIG_DIGITAL_OUTPUT", 0, 8, 0, 1, 0, 3, 0, }, },
// [5] AVDD OFF
package() { "TLMMGPIO", package() { 8, 0, 0, 1, 0, 0, }, },
// [6] DOVDD OFF
package() { "PMICVREGVOTE", package() { "PPP_RESOURCE_ID_LVS1_A", 4, 0, 0, }, },
package() { "CLOCK", package() { "cam_cc_camnoc_axi_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_cpas_ahb_clk", 2 } },
package() { "CLOCK", package() { "cam_cc_soc_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_axi_clk", 2 } },
Package() { "FOOTSWITCH", Package() { "titan_top_gdsc", 2 } },
package() { "CLOCK", package() { "gcc_camera_ahb_clk", 2 } },
package() { "CLOCK", package() { "gcc_camera_xo_clk", 2 } },
},
}
})
}

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DSDT/polaris/cust_dsdt.asl Normal file
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//
// Camera Platform, Camera Sensors, White LED Flash, JPEG HW, VFE Moved to a dedicated asl
// This is done to support Multiple platforms and Multiple OEM Projects in CRM Builds
//
Include("cust_camera.asl")
Include("cust_sensors.asl")
// GPIO_11
Method (ADDR)
{
If(Lequal(\_SB_.SVMJ, 1))
{
return(0x390B000)
}
ElseIf(Lequal(\_SB_.SVMJ, 2))
{
return(0x350B000)
}
}
OperationRegion(NM11, SystemMemory, ADDR, 0x14)
Field(NM11, DWordAcc, NoLock, Preserve){
PI1C, 32,
PIN1, 32,
PI1N, 32,
PI1S, 32,
PI1L, 32,
}
// BOARD VERSION (NBID)
// NBID == 0x0 i.e. FULL MODEM BUILD
// NBID == 0x1 i.e. NO MODEM BUILD
Method (_MID, 0, Serialized) {
Name(NMID, Zero)
Store(PIN1, NMID)
Return (NMID)
}

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Name(HWNH, 1)
Name(HWNL, 1)
//
// HWN Haptics
//
Device (HWN1)
{
Name (_HID, "QCOM02A9")
Alias(\_SB.PSUB, _SUB)
Method (_STA)
{
if(LEqual(\_SB_.HWNH, 0)) {
Return (0)
}
else {
Return (0x0F)
}
}
Name (_DEP,
Package(0x1)
{
\_SB_.PMIC
}
)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF,
ResourceTemplate ()
{
// Short Circuit IRQ
GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.PM01", , , , ) {400} // 0xE00 - PM_INT__HAPTICS__SC_INT
// Play IRQ
// GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, "\\_SB.PM01", , , , ) {401} // 0xE01 - PM_INT__HAPTICS__PLAY_INT
}
)
Return(RBUF)
}
/* ACPI methods for HAPI - Haptics Device info */
Method(HAPI, 0x0, NotSerialized)
{
Name (CFG0,
Package()
{
1, // TotalHwnVib - Total HWN Vibs
1, // PmicNumber - PMIC Number for HWN Vibs
1, // HapticsConfigInputSource - Read configuration from 0: Registry, 1: ACPI (HAPC method)
}
)
Return (CFG0)
}
/* ACPI methods for HAPC - Haptics configuration method */
Method(HAPC, 0x0, NotSerialized)
{
Name (CFG0,
Package()
{
//------------------------ Actuator Config -----------------------------------------------------
0, // VibType - 0: LRA, 1: ERM
2436, // VibVmaxCfg - 2436 mV
0, // PeakCurrentLimit - 0: 400ma, 1: 800ma
1, // ShortCircuitDebounce - 0: No Deb, 1: 8 clk cycles, 2: 16 clk cycles, 3: 32 clk cycles
1, // InternalPWMFreq - 0: 253KHz, 1: 505KHz, 2: 739KHz, 3: 1076KHz
1, // PWMCapacitance - 0: 26PF, 1: 13PF, 2: 8p7PF, 3: 6p5PF
1, // SlewRate - 0: 6ns, 1: 16ns
0, // LRASignalType - 0: Sinusoidal, 1: Square
//----------------------------------------------------------------------------------------------
//------------------------ LRA Auto Resonance Config -------------------------------------------
4, // LRAAutoResMode - 0: No auto resonance, 1: ZXD, 2: QWD, 3: MAX QWD, 4: ZXD with EOP
1, // LRAAutoResHighZDuration - 0: No HighZ,
// 1: [2 LRA period (ZXD), 1/8 LRA period (QWD)],
// 2: [3 LRA period (ZXD), 1/4 LRA period (QWD)],
// 3: [4 LRA period (ZXD), 1/2 LRA period (QWD)]
3, // LRAAutoResCalibFreqZXD - 0: 4 LRA periods, 1: 8 LRA periods,
// 2: 16 LRA periods, 3: 32 LRA periods
20, // InitialAutoResDelayQWD - Delay(in ms) used for QWD mode before enabling auto-resonance
// Typical value is 5-20ms. This is to ensure there is enough
// back emf for Auto Resonance to work fine.
// - This is a don't care in ZXD mode
//----------------------------------------------------------------------------------------------
//------------------------ Braking Config ------------------------------------------------------
1, // AutoBrakingEnable - 0: Disable, 1: Enable
0x03, // BrakePattern - brake pattern of [0,0,0,VMAX] = [ 00 00 00 11] = 0x03
0, // BrakeWithMaxVoltageEnable - 0: Disable, 1: Enable - Brake pattern applied with max voltage
// that can be supplied by PMIC Haptics module
//----------------------------------------------------------------------------------------------
//------------------------ Acceleration Config -------------------------------------------------
0, // DirectModeAccelerationEnable - 0: Disable, 1: Enable
6, // DirectModeAccelerationDuration - in milli seconds
//----------------------------------------------------------------------------------------------
0, // HapticsSource - 0: VMAX, 1: BUFFER, 2: AUDIO, 3: EXT PWM
0, // HapticsTrigger - 0: Play, 1: Line In
1333, // PlayRateCode - LRA Freq 150Hz, PlayRateCode = (200 * 1000) / LRA_Freq
3, // MaxSCIntrRetries - Max SC Interrupt retries before crashing the device
1, // HapticsAutoResErrorRecover - Enable Auto Resonance Error recovery support
}
)
Return (CFG0)
}
}
//
// HWN LED
//
Device (HWN0)
{
Name (_HID, "QCOM02A8")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Method (_STA)
{
if(LEqual(\_SB_.HWNL, 0)) {
Return (0)
}
else {
Return (0x0F)
}
}
// ACPI method for LED Configs
Method(HWNL, 0x0, NotSerialized)
{
Name (CFG0,
Package()
{
1, // PMIC number PMI8994
3, // Total HWN LEDs
//RGB LEDs
411, // Fade interval in ms (0-511 ms)
20, // Fade Steps i.e 5, 10, 15, 20(max)
0x20, // LED0 Id (BLUE)
0x02, // LED0 bank on PMI8998 (LPG_CHAN3)
0x40, // LED1 Id (GREEN)
0x03, // LED1 bank on PMI8998 (LPG_CHAN4)
0x80, // LED2 Id (RED)
0x04, // LED2 bank on PMI8998 (LPG_CHAN5)
//RGB PWM Config
1, //PWM bit Resoultion
//Valid Inputs ( 0 - 6 bit mode, 1 - 9 bit mode)
1, //PWM_EN_HI
1, //PWM_EN_LO
3, //PWM_MASTER_CLK_FREQ
//Valid Inputs(0- No Clk, 1 - 1.024 KHz, 2 - 32.764 KHz, 3 - 19.2 MHz)
1, //Clock Pre Divide (Values can be 1, 3, 5, 6)
1, //Exponent (Values range 0 - 7)
})
Return (CFG0)
}
}

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// This file contains the Power Management IC (PMIC)
// customer-modifiable ACPI configurations.
//
//******************************************
//Configs for Battery Manager Device: PMBT
//******************************************
//--------------------
//PMBT: Method(BBAT)
//--------------------
Name(BFCC, 13110) //* (mWh), Full Charge Capacity
Name(PCT1, 5) //* (% of FCC), Default Alert 1
Name(PCT2, 9) //* (% of FCC), Default Alert 2
//--------------------
//PMBT: Method(BMNR)
//--------------------
Name(CUST, "850_MTP") //* cust file identifier
//--------------------
//PMBT: Method(BPLT)
//--------------------
Name(VNOM, 3800) //* (mV), Nominal Battery Voltage
Name(VLOW, 3300) //* (mV), Low Battery Voltage
Name(EMPT, 3200) //* (mV), VCutOff
Name(DCMA, 900) //* (mA), DC Current
Name(BOCP, 4500) //* (mA), OCP current used in BCL
Name(BVLO, 3000) //* (mV), BCL low Vbatt
Name(BLOP, 20) //* (%), BCL Low batt percent notification
Name(BNOP, 22) //* (%), BCL normal batt percent notification
Name(IFGD, 50) //* (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
Name(VFGD, 50) //* (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
//--------------------------------
//PMBT: Method(BJTA)/Method(BAT1)
//--------------------------------
Name(VDD1, 4350) //* (mV), Battery-1: Float Voltage (Standard Zone)
Name(FCC1, 2100) //* (mA), Battery-1: Full Charge Current (Standard Zone)
Name(HCLI, 0) //* (degree C), hard-cold temperature limit
Name(SCLI, 10) //* (degree C), soft-cold temperature limit
Name(SHLI, 45) //* (degree C), soft-hot temperature limit
Name(HHLI, 55) //* (degree C), hard-hot temperature limit
Name(FVC1, 105) //* (mV), Float voltage compensation, when battery in JEITA soft-limit
Name(CCC1, 1000) //* (mA), Charge current compensation, when battery in JEITA soft-limit
//--------------------
//PMBT: Method(CTMC)
//--------------------
Name(RID2, 15000) //* (Ohm), min RID for NORMAL category: 15K
Name(RID3, 140000) //* (Ohm), max RID for NORMAL category: 140K

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// This file contains the sensor ACPI device definitions.
//
// Qualcomm Sensor Collection
Device (SEN2)
{
Name (_DEP, Package(0x3)
{
\_SB_.IPC0, //IPC Router used by QMI
\_SB_.SCSS, //SCSS loads the sensors image
\_SB_.ARPC //Dependency on FastRPC
})
Name (_HID, "QCOM0308")
Alias(\_SB.PSUB, _SUB)
Name (_CID, "QCOM02A2")
// Enable below for Dual Sensor Multinode
//Device (SEN3)
//{
// Name (_DEP, Package(0x4)
// {
// \_SB_.IPC0, //IPC Router used by QMI
// \_SB_.SCSS, //SCSS loads the sensors image
// \_SB_.ARPC, //Dependency on FastRPC
// \_SB_.SEN2 //Dependency on SEN2
// })
// Name (_HID, "QCOM0309")
// Alias(\_SB.PSUB, _SUB)
// Name (_CID, "QCOM02A2")
//}
// Methods used for parsing the sensors configuration (.conf) file.
// HARD corresponds to ":hardware"
// PLAT corresponds to ":platform"
Method(HARD, 0x0, NotSerialized) {
Return("845")
}
Method(PLAT, 0x0, NotSerialized) {
Return("MTP")
}
//Disable Sensors for V1s to support new SLPI
Method(_STA, 0)
{
If(Lequal(\_SB_.SVMJ, 1))
{
return (0x0)
}
Else
{
return (0xFF)
}
}
}

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//
//CPU Aggregator Device -- Required for Thermal Parking
Device(AGR0)
{
Name(_HID, "ACPI000C")
Name(_PUR, Package() {1, 0})
Method(_OST, 0x3, NotSerialized)
{
Store(Arg2, \_SB_.PEP0.ROST)
}
}
//---------------------------------------------------------------------
//
// Thermal Zones for QC reference hardware
//
//TZ0 - TZ39 are thermal zones developed by QC for reference hardware
//and can be modified by the OEMs.
//---------------------------------------------------------------------
//---------------------------------------------------------------------
// Thermal Zones(0-19) for CPU sensors
//24AD - Little CPU virtual sensor
//24AE - Big CPU virtual sensor
// This thermal zone is only used for temperature logging for little CPUs
// as you may notice that _PSV, _TC1, _TC2, _TSP params are removed.
// This is the passive cooling mechanism by dialing down frequency is now
// done actively by hardware.
//---------------------------------------------------------------------
ThermalZone (TZ0) {
Name (_HID, "QCOM02B0")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3})
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ0
//Regular Thermal Zone for Little CPU TSENS to Park cores at 110C
ThermalZone (TZ1) {
Name (_HID, "QCOM02B0")
Name (_UID, 1)
Name(_TZD, Package (){\_SB.PEP0})
Name(TPSV, 3830)
Method(_PSV) { Return (\_SB.TZ1.TPSV) }
Name(_MTL, 20) // minimum throttle limit
//Control how aggressively the thermal manager applies thermal
//throttling performance against temperature change.
Name(TTC1, 0)
Method(_TC1) { Return (\_SB.TZ1.TTC1) }
// _TC2 Controls how aggressively the thermal manager applies thermal
// throttling performance against temperature delta between the
// current temperature and _PSV.
// once the temp goes above _PSV, we like to have aggressive
// throttling based on how far above the temp is above the threshold.
// Since that is controlled via _TC2, we like it to be high.
// please refer to the ACPI spec 6.0 to understand the significance of
// _TC2 or take a look at the explanation at the top of this file.
Name(TTC2, 1)
Method(_TC2) { Return (\_SB.TZ1.TTC2) }
// Appropriate temperature sampling interval for the zone in tenths
// of a second. The thermal manager uses this interval to determine
// how often it should evaluate the thermal throttling performance.
// Must be greater than zero. For more information, see Thermal
// throttling algorithm on msdn page
// https://msdn.microsoft.com/en-us/library/windows/hardware/mt643928(v=vs.85).aspx
Name(TTSP, 50)
Method(_TSP) { Return (\_SB.TZ1.TTSP) }
// This optional object evaluates to a recommended polling frequency
// (in tenths of seconds) for this thermal zone. A value of zero indicates
// that OSPM does not need to poll the temperature of this thermal zone in
// order to detect temperature changes (the hardware is capable of
// generating asynchronous notifications).
// TZP should be marked 0 for all thermal zones as our TSENS sensors
// generate interrupts to complete thermal IOCTL read call.
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ1
// This thermal zone is only used for temperature logging for Big CPUs
// as you may notice that _PSV, _TC1, _TC2, _TSP params are removed.
// This is the passive cooling mechanism by dialing down frequency is now
// done actively by hardware.
ThermalZone (TZ2) {
Name (_HID, "QCOM02B1")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7})
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ2
//Regular Thermal Zone for BigCPU TSENS to Park cores at 110C
ThermalZone (TZ3) {
Name (_HID, "QCOM02B1")
Name (_UID, 1)
Name(_TZD, Package (){\_SB.PEP0})
Name(TPSV, 3830)
Method(_PSV) { Return (\_SB.TZ3.TPSV) }
Name(TTC1, 0)
Method(_TC1) { Return (\_SB.TZ3.TTC1) }
Name(TTC2, 1)
Method(_TC2) { Return (\_SB.TZ3.TTC2) }
Name(TTSP, 1)
Method(_TSP) { Return (\_SB.TZ3.TTSP) }
Name(_MTL, 20) // minimum throttle limit
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ3
//---------------------------------------------------------------------
// Thermal Zones(20-21) for GPU TSENS
//
// \_SB.GPU0 should be used for GPU thermal mitigation, and
// \_SB.GPU0.AVS0 should be used for MDSS/Video thermal mitigation.
// Currently there is no handling for Video thermal mitigation.
// When needed, Video will be added to GPU0.AVS0 interface.
//---------------------------------------------------------------------
//Thermal zone for TSENS11 dial back GPUs at 95C
ThermalZone (TZ20) {
Name (_HID, "QCOM02AB")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.GPU0})
Name(TPSV, 3680)
Method(_PSV) { Return (\_SB.TZ20.TPSV) }
Name(TTC1, 1)
Method(_TC1) { Return (\_SB.TZ20.TTC1) }
// For non-cpu devices, tc2 should be atleast 5, please refer to the
// explanation at the top of the file or msdn link for thermal guide.
Name(TTC2, 2)
Method(_TC2) { Return (\_SB.TZ20.TTC2) }
// For non-cpu devices, _tsp should be 20 or 30
Name(TTSP, 2)
Method(_TSP) { Return (\_SB.TZ20.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ20
//Thermal zone for TSENS12 to dial back GPUs at 95C
ThermalZone (TZ21) {
Name (_HID, "QCOM02AC")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.GPU0})
Name(TPSV, 3680)
Method(_PSV) { Return (\_SB.TZ21.TPSV) }
Name(TTC1, 1)
Method(_TC1) { Return (\_SB.TZ21.TTC1) }
Name(TTC2, 2)
Method(_TC2) { Return (\_SB.TZ21.TTC2) }
Name(TTSP, 2)
Method(_TSP) { Return (\_SB.TZ21.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ21
//---------------------------------------------------------------------
// Thermal Zones for QDSP TSENS
//4/16/15: TODO waiting to get a new HID assigned for TSENS17
//---------------------------------------------------------------------
//Thermall zone for TSENS14 dial back MSM at 95C
//ThermalZone (TZ31) {
//Name (_HID, "QCOM02AE")
//Name (_UID, 0)
//Name(_TZD, Package (){
//\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
//\_SB.PEP0, \_SB.GPU0.MON0, \_SB.GPU0})
//Method(_PSV) { Return (3680) }
//Name(_TC1, 1)
//Name(_TC2, 2)
//Name(_TSP, 10)
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
//} // end of TZ31
//---------------------------------------------------------------------
// Thermal Zones for Camera TSENS
//---------------------------------------------------------------------
//Thermal zone for TSENS17 to dial back MSM at 95C
ThermalZone (TZ32) {
Name (_HID, "QCOM02C9")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.GPU0.AVS0})
Name(TPSV, 3680)
Method(_PSV) { Return (\_SB.TZ32.TPSV) }
Name(TTC1, 1)
Method(_TC1) { Return (\_SB.TZ32.TTC1) }
// For non-cpu devices, tc2 should be atleast 5, please refer to the
// explanation at the top of the file or msdn link for thermal guide.
Name(TTC2, 2)
Method(_TC2) { Return (\_SB.TZ32.TTC2) }
// For non-cpu devices, _tsp should be 20 or 30
Name(TTSP, 10)
Method(_TSP) { Return (\_SB.TZ32.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ32
ThermalZone (TZ33) {
Name (_HID, "QCOM02CB")
Name (_UID, 1)
Name(_TZD, Package (){\_SB.AMSS})
Name(TPSV, 3680)
Method(_PSV) { Return (\_SB.TZ33.TPSV) }
Name(TTC1, 1)
Method(_TC1) { Return (\_SB.TZ33.TTC1) }
Name(TTC2, 2)
Method(_TC2) { Return (\_SB.TZ33.TTC2) }
Name(TTSP, 10)
Method(_TSP) { Return (\_SB.TZ33.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
}
//---------------------------------------------------------------------
// Thermal Zones for MDSS TENS (Display Subsystem)
// Only the MDP Blt engine and Rotator engines on the MDSS are cooled
// using this interface. Display cooling is not supported currently.
//---------------------------------------------------------------------
//Thermal zone for TSENS18 to dial back MSM at 95C
//ThermalZone (TZ34) {
//Name (_HID, "QCOM02CA")
//Name (_UID, 0)
//Name(_TZD, Package (){\_SB.GPU0.AVS0})
//Method(_PSV) { Return (3680) }
//Name(_TC1, 1)
//Name(_TC2, 2)
//Name(_TSP, 10)
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
//} // end of TZ34
//---------------------------------------------------------------------
// Thermal Zones for ADC Channels
//---------------------------------------------------------------------
//Thermal zone for PMIC_THERM
ThermalZone (TZ36) {
Name (_HID, "QCOM029E")
Name (_UID, 0)
Name(_TZD, Package (){
\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7,
\_SB.PMBM})
Name(TPSV, 3780)
Method(_PSV) { Return (\_SB.TZ36.TPSV) }
Name(TTC1, 4)
Method(_TC1) { Return (\_SB.TZ36.TTC1) }
Name(TTC2, 3)
Method(_TC2) { Return (\_SB.TZ36.TTC2) }
Name(TTSP, 50)
Method(_TSP) { Return (\_SB.TZ36.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0, \_SB.ADC1})
}
} // end of TZ36
//Thermal zone for PMIC_THERM
ThermalZone (TZ37) {
Name (_HID, "QCOM029E")
Name (_UID, 1)
Name(_TZD, Package (){
\_SB.PEP0, \_SB.PMBM})
Name(TPSV, 3980)
Method(_PSV) { Return (\_SB.TZ37.TPSV) }
Name(TCRT, 4180)
Method(_CRT) { Return (\_SB.TZ37.TCRT) }
Name(TTC1, 4)
Method(_TC1) { Return (\_SB.TZ37.TTC1) }
Name(TTC2, 3)
Method(_TC2) { Return (\_SB.TZ37.TTC2) }
Name(TTSP, 50)
Method(_TSP) { Return (\_SB.TZ37.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0, \_SB.ADC1})
}
} // end of TZ37
//Example: Inverse Thermal zone for PMIC_THERM
ThermalZone (TZ38) {
Name (_HID, "QCOM029E")
Name (_UID, 2) //Update UID on addition of new thermal zone with same HID
Name(_TZD, Package (){
\_SB.PEP0})
Method(INVT) { Return (1) }
Method(_MTL) { Return (60) }
Name(TPSV, 2830)
Method(_PSV) { Return (\_SB.TZ38.TPSV) }
Name(TTC1, 4)
Method(_TC1) { Return (\_SB.TZ38.TTC1) }
Name(TTC2, 3)
Method(_TC2) { Return (\_SB.TZ38.TTC2) }
Name(TTSP, 10)
Method(_TSP) { Return (\_SB.TZ38.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0, \_SB.ADC1})
}
} // end of TZ38
//------------------------------------------------------------------------
// Thermal Zones for Wlan
//------------------------------------------------------------------------
//Thermal zone for iHelium, Wlan MAC&PHY on SOC
ThermalZone (TZ40) {
Name (_HID, "QCOM02AF")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.COEX})
Name(TPSV, 3580)
Method(_PSV) { Return (\_SB.TZ40.TPSV) }
Name(TTC1, 1)
Method(_TC1) { Return (\_SB.TZ40.TTC1) }
Name(TTC2, 5) // For non-cpu devices, tc2 should be atleast 5
Method(_TC2) { Return (\_SB.TZ40.TTC2) }
Name(TTSP, 30) // For non-cpu devices, _tsp should be 20 or 30
Method(_TSP) { Return (\_SB.TZ40.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ40
//Thermal zone for Cherokee, Wlan radio on WCN3990
ThermalZone (TZ41) {
Name (_HID, "QCOM0295")//virtual sensor by wlan WMI thermal interface
Name (_UID, 1)
//Name(_TZD, Package (){\_SB.COEX}) // Temperature report only
//Method(_PSV) { Return (4030) }
//Name(_TC1, 4)
//Name(_TC2, 3)
Name(_TSP, 50)
Name(_TZP, 0)
} // end of TZ41
//------------------------------------------------------------------------
// Thermal Zones for DDR/POP
//------------------------------------------------------------------------
//Thermal zone for DDR
//Thermal zone for TSENS20 to dial back Big CPU's at 95C
ThermalZone (TZ44) {
Name (_HID, "QCOM02CC")
Name (_UID, 0)
Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5, \_SB.SYSM.CLUS.CPU6, \_SB.SYSM.CLUS.CPU7})
Name(TPSV, 3680)
Method(_PSV) { Return (\_SB.TZ44.TPSV) }
Name(TTC1, 0)
Method(_TC1) { Return (\_SB.TZ44.TTC1) }
Name(TTC2, 1)
Method(_TC2) { Return (\_SB.TZ44.TTC2) }
Name(TTSP, 1)
Method(_TSP) { Return (\_SB.TZ44.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ44
//---------------------------------------------------------------------
//
// QC Recommended thermal limits starts
//
//TZ80 - TZ98 represent the thermal zones corresponding to QC
//recommended thermal limits. These thermal zones must not be removed
//or tampered with.
//---------------------------------------------------------------------
//Thermal zone for TSENS2 at 70C to match the LA thermal limits
//ThermalZone (TZ80) {
//Name (_HID, "QCOM2472")
//Name (_UID, 0)
//Name(_TZD, Package (){
// \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
//Method(_PSV) { Return (3430) }
//Name(_TC1, 1)
//Name(_TC2, 2)
//Name(_TSP, 10)
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
//} // end of TZ80
//Thermal zone near for TSENS2 to shutdown the system at 85C to match LA
//thermal limits
//ThermalZone (TZ81) {
//Name (_HID, "QCOM2472")
//Name (_UID, 1)
//Name(_TZD, Package (){
// \_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,
// \_SB.PEP0})
//Method(_PSV) { Return (3530) }
//Method(_CRT) { Return (3580) }
//Name(_TC1, 1)
//Name(_TC2, 2)
//Name(_TSP, 10)
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
//} // end of TZ81
//Entry for BCL thermal zone
ThermalZone (TZ98) {
Name (_HID, "QCOM0294")
Name (_UID, 0)
Name(_TZD, Package (){
\_SB.GPU0.MON0, \_SB.GPU0})
Name(TPSV, 3630)
Method(_PSV) { Return (\_SB.TZ98.TPSV) }
Name(TTC1, 1)
Method(_TC1) { Return (\_SB.TZ98.TTC1) }
//Method(_CRT) { Return (5630) }
Name(TTC2, 5)
Method(_TC2) { Return (\_SB.TZ98.TTC2) }
Name(TTSP, 20)
Method(_TSP) { Return (\_SB.TZ98.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package(0x2) {\_SB.PEP0,\_SB_.BCL1})
}
} // end of TZ98
//---------------------------------------------------------------------
// Critical Thermal Zones for ALL TSENS
//This sensor aggregates all the on chip TSENS into a single sensor
//for ACPI thermal manager. By having a critical thermal zone on this
//"virtual sensor" we don't have to add a critical thermal zone on every
//sensor and hence reduce the number of thermal zones.
//---------------------------------------------------------------------
//Critical Thermal zone on MSM virtual sensor to shutdown entire system
//at 110C.
ThermalZone (TZ99) {
Name (_HID, "QCOM02B2")
Name (_UID, 100)
Name(TCRT, 3830)
Method(_CRT) { Return (\_SB.TZ99.TCRT) }
Name(TTC1, 4)
Method(_TC1) { Return (\_SB.TZ99.TTC1) }
Name(TTC2, 3)
Method(_TC2) { Return (\_SB.TZ99.TTC2) }
Name(TTSP, 10)
Method(_TSP) { Return (\_SB.TZ99.TTSP) }
Name(_TZP, 0)
Method(_DEP) {
Return (Package() {\_SB.PEP0})
}
} // end of TZ99
//---------------------------------------------------------------------
// QC Recommended thermal limits ends
//---------------------------------------------------------------------
//---------------------------------------------------------------------
//
// Sample Thermal Zones for OEMs TZ40 - TZ79
//
//Sample TSENS thermal zone that can be added on any TSENS
//---------------------------------------------------------------------
//ThermalZone (TZ40) {
//Name (_HID, "QCOM2470")
//Name (_UID, 0)
//Name(_TZD, Package (){
//\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,
//\_SB.PEP0, <Your cooling device>})
//Method(_PSV) { Return (3730) }
//Method(_CRT) { Return (3780) }
//Name(_TC1, 1)
//Name(_TC2, 2)
//Name(_TSP, 10) //Sampling rate of 1sec
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
//} // end of TZ40
//ThermalZone (TZ41) {
//Name (_HID, "QCOM2470")
//Name (_UID, 0)
//Name(_TZD, Package (){
//\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,
//\_SB.PEP0, <Your cooling device>})
//Method(_PSV) { Return (3730) }
//Method(_CRT) { Return (3780) }
//Name(_TC1, 1)
//Name(_TC2, 2)
//Name(_TSP, 50) //Sampling rate of 5sec
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
//} // end of TZ41
//--------------------------------------------------------------------------//
//
// Sample VADC Thermal zones for OEMs
//
//Following are sample thermal zones that use the off chip ADC thermistors
//they are all currently using CPUs as a cooling device for a lack of better
//option. The OEMs should change this.
//--------------------------------------------------------------------------//
//Thermal zone for SYS_THERM2
// ThermalZone (TZ51) {
// Name (_HID, "QCOM248D")
// Name (_UID, 0)
// Name(_TZD, Package (){
//\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3,\_SB.SYSM.CLUS.CPU4, \_SB.SYSM.CLUS.CPU5,})
// Method(_PSV) { Return (3830) }
//Name(_TC1, 4)
//Name(_TC2, 3)
// Name(_TSP, 50)
//Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
// } // end of TZ51
//Thermal zone for PA_THERM1
// ThermalZone (TZ52) {
// Name (_HID, "QCOM248E")
// Name (_UID, 0)
// Name(_TZD, Package (){\_SB.SYSM.CLUS.CPU0, \_SB.SYSM.CLUS.CPU1, \_SB.SYSM.CLUS.CPU2, \_SB.SYSM.CLUS.CPU3})
// Method(_PSV) { Return (3430) }
// Name(_TC1, 4)
// Name(_TC2, 3)
// Name(_TSP, 50)
// Name(_TZP, 0)
//Method(_DEP) {
// Return (Package() {\_SB.PEP0})
//}
// } // end of TZ52

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//Improve Touch Driver, no it's not for polaris
Device (TSC5)
{
Name (_HID, "QCOM02F5")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
Name(_DEP, Package()
{
\_SB_.ARPC
})
//Disable Touch for V1s to support new SLPI
Method(_STA, 0)
{
If(Lequal(\_SB_.SVMJ, 1))
{
return (0x0)
}
Else
{
return (0xFF)
}
}
}

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//===========================================================================
// <cust_touch_resources.asl>
// DESCRIPTION
// This file contains the resources needed by touch driver.
//
//
//===========================================================================
Scope(\_SB_.PEP0)
{
Method(LPMX)
{
Return(LPXC)
}
Name(LPXC,
Package(){
})
}

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//
// This file contains the ACPI Extensions for Display Adapters
//
///
// _ROM Method - Used to retrieve proprietary ROM data for primary panel
//
Method (_ROM, 3, NotSerialized) {
// Include primary panel specific ROM data
Include("panelcfg.asl")
//======================================================================================
// Based on the panel Id(Arg2), store the buffer object into Local2
//
// IMPORTANT:
// PCFG is buffer name for all default panel configurations
// All other dynamically detected panel configurations must not use this name
//======================================================================================
Switch ( ToInteger (Arg2) )
{
// Truly WQHD Dual DSI Command Mode
Case (0x008010) {
Store (PCFG, Local2)
}
// Truly WQHD Dual DSI Video Mode
Case (0x008011) {
Store (PCF1, Local2)
}
// Truly WQHD Single DSI DSC Command Mode
Case (0x008012) {
Store (PCF2, Local2)
}
// Truly WQHD Single DSI DSC Video Mode
Case (0x008013) {
Store (PCF3, Local2)
}
// 4k Dual DSC Sharp Command Mode
Case (0x00008000) {
Store (PCF4, Local2)
}
// 4k Dual DSC Sharp Video Mode
Case (0x00008056) {
Store (PCF5, Local2)
}
// All others
Default {
Store (PCFG, Local2)
}
}
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(Local2)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(Local2), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBuf
CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
Return(RBUF)
}
//
// IGC method - panel inverse gamma correction table.
//
// The buffer contains inverse gamma correction data for 3 color components, each with 256 16-bit integers.
// The buffer size is 3*256*2 = 1536 bytes.
// each table entry is represend by a 16-bit integer and data format in the buffer is described below:
//
// +--- 16 bits ---+--- 16 bits ---+--- 16 bits ---+---------+--- 16 bits ---+ 0
// | Red[0] | Red[1] | Red[2] | ... | Red[255] |
// +---------------+---------------+---------------+---------+---------------+ 512
// | Green[0] | Green[1] | Green[2] | ... | Green[255] |
// +---------------+---------------+---------------+---------+---------------+ 1024
// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[255] |
// +---------------+---------------+---------------+---------+---------------+ 1536
//
Method (PIGC, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the IGC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// PCC method - panel color correction matrix
//
// Buffer format for HW which support 3X8 color correction matrix.
//
// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers.
// The buffer size is 3*11*8 = 264 bytes.
// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the
// buffer is described below:
//
// +--64 bits--+--64 bits--+--------+--64 bits--+--64 bits--+--64 bits--+--64 bits--+ 0
// | Red[0] | Red[1] | ... | Red[7] | 0 | 0 | 0 |
// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 88
// | Green[0] | Green[1] | ... | Green[7] | 0 | 0 | 0 |
// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 176
// | Blue[0] | Blue[1] | ... | Blue[7] | 0 | 0 | 0 |
// +-----------+-----------+--------+-----------+-----------+-----------+-----------+ 264
//
// Buffer format for HW which support 3X11 color correction matrix.
//
// The buffer contains color correction coefficients for 3 color components, each with 11 64-bit integers.
// The buffer size is 3*11*8 = 264 bytes.
// each coefficient in the matrix is represented by a long long integer (64-bit), and data format in the
// buffer is described below:
//
// +--- 64 bits ---+--- 64 bits ---+--- 64 bits ---+-----------+--- 64 bits ---+ 0
// | Red[0] | Red[1] | Red[2] | ... | Red[10] |
// +---------------+---------------+---------------+-----------+---------------+ 88
// | Green[0] | Green[1] | Green[2] | ... | Green[10] |
// +---------------+---------------+---------------+-----------+---------------+ 176
// | Blue[0] | Blue[1] | Blue[2] | ... | Blue[10] |
// +---------------+---------------+---------------+-----------+---------------+ 264
//
Method (PPCC, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the PCC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// PGC method - panel segment gamma correction table
//
// there're thee components and each with 16 gamma correction segments. Each segment is defined
// as below with parameters, and each parameter is represented by a 32-bit integer (DWORD):
//
// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+
// | enable | start | gain | offset | one gamma correction segment(16 bytes)
// +-----------+-----------+-----------+-----------+
//
// +--- 16 bytes ---+--- 16 bytes ---+--- 16 bytes ---+-----------+--- 16 bytes ---+ 0
// | red_seg[0] | red_seg[1] | red_seg[2] | ... | red_seg[15] |
// +----------------+----------------+----------------+-----------+----------------+ 256
// | green_seg[0] | green_seg[1] | green_seg[2] | ... | green_seg[15] |
// +----------------+----------------+----------------+-----------+----------------+ 512
// | blue_seg[0] | blue_seg[1] | blue_seg[2] | ... | blue_seg[15] |
// +----------------+----------------+----------------+-----------+----------------+ 768
//
Method (PGCT, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the GCT buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// PLGC method - panel linear gamma correction table
//
// There are three color components, each color component has 1024 entries. each entry is 2 bytes.
//
// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+ 0
// | red[0] | red[1] | red[2] | ... | red[1023] |
// +---------------+---------------+---------------+-----------+---------------+ 2048
// | green[0] | green[1] | green[2] | ... | green[1023] |
// +---------------+---------------+---------------+-----------+---------------+ 4096
// | blue[0] | blue[1] | blue[2] | ... | blue[1023] |
// +---------------+---------------+---------------+-----------+---------------+ 6144
//
Method (PLGC, 3, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data offset
// Arg2 - Data size
// Based on the panel Id read the LGC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (TBUF, Buffer() {0x0} )
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg1, Sizeof(TBUF)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg1, Local1)
}
// Arg2 - Data size
// Ensure the size requested is less than 4k
If (LGreater(Arg2, 0x1000))
{
Store(0x1000, Local2)
}
else
{
Store(Arg2, Local2)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local1, Local2), Sizeof(TBUF)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(TBUF), Local1, Local2);
}
// Multiply offset and size by 8 to convert to bytes and create the RBUF
CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF)
// Return the packet data
Return(RBUF)
}
//
// HSIC method - HSIC settings
//
// Hue, Saturation, Intensity, Contrast levels, the first parameter enable/disable HSIC control,
// followed by HSIC level values, each level ranges from -100 to 100, represented by a 32-bit integer:
//
// +--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--+--4 bytes--++
// | Enable | Hue | Saturation| Intensity | Contrast |
// +-----------+-----------+-----------+-----------+-----------++
//
//
Method (HSIC, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the HSIC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// PGMT - panel gamut mapping table for HW which support 9x9x9 gamut mapping:
//
// This method returns the gamut mapping table for a panel.
//
// There are three components. Each component has 8 tables and a total of 729 entries.
// Each value is represented by a 16-bit integer:
//
// Table ID Entries
// 0 125
// 1 100
// 2 80
// 3 100
// 4 100
// 5 80
// 6 64
// 7 80
//
// +----- 16 bits -----+----- 16 bits ------+----- 16 bits -----+-----------+----- 16 bits -------+
// | red_comp[0][0] | red_comp[0][1] | red_comp[0][2] | ... | red_comp[7][79] |
// +-------------------+--------------------+-------------------+---------------------------------+
// | green_comp[0][0] | green_comp[0][1] | green_comp[0][2] | ... | green_comp[7][79] |
// +-------------------+--------------------+-------------------+---------------------------------+
// | blue_comp[0][0] | blue_comp[0][1] | blue_comp[0][2] | ... | blue_comp[7][79] |
// +-------------------+--------------------+-------------------+---------------------------------+
//
Method (PGMT, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the GMT buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (TBUF, Buffer() {0x0} )
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(TBUF)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Arg1 - Data size
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(TBUF), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBUF
CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
// Return the packet data
Return(RBUF)
}
//
// PWGM - panel gamut mapping data for HW which support 17x17x17 gamut mapping
//
// This data's header which has two fields:
// NumSamplesPerColorComponent: Number samples per color component in gamut mapping table.
// NumSegmentsPerColor : Number of segments per color component.
// NumSegmentsPerColor must equal 0 or NumSamplesPerColorComponent -1.
//
// This data also can have two tables, one is 3d table, one is segment table.
// Segment table is only required if NumSegmentsPerColor != 0.
//
// 3d table: There are three components. If number samples per component is N = NumSamplesPerColorComponent,
// total entries are NxNxN per component. Each value is represented by a 16-bit integer:
// Segment table: There are three components, table entries are uNumSegmentsPerColor per component,
// each entry is 32 bit value.
//
// Table data header:
// +--------- 32 bits ----------+------- 32 bits -----+
// | NumSamplesPerColorComponent| NumSegmentsPerColor |
// +----------------------------+---------------------+ 8 bytes
//
// 3d table:
// +---- 16 bits ----+---- 16 bits ----+---- 16 bits ----+-------------+------- 16 bits -----------+ 8
// | red_comp[0] | red_comp[1] | red_comp[2] | ... | red_comp[N x N x N - 1 ] |
// +-----------------+-----------------+-----------------+-------------+---------------------------+ NxNxNx2 + 8
// | green_comp[0] | green_comp[1] | green_comp[2] | ... | green_comp[N x N x N - 1] |
// +-----------------+-----------------+-----------------+-------------+---------------------------+ 2xNxNxNx2 + 8
// | blue_comp[0] | blue_comp[1] | blue_comp[2] | ... | blue_comp[N x N x N - 1] |
// +-----------------+-----------------+-----------------+-------------+---------------------------+ 3xNxNxNx2 + 8
//
// Segment table: ( if NumSegmentsPerColor = 0, there is no segment table).
// +----- 32 bits ------+----- 32 bits ------+------ 32 bits -----+-------------+-------- 32 bits -------+ 3xNxNxNx2 + 8
// | sg_red_comp[[0] | sg_red_comp[1] | sg_red_comp[2] | ... | sg_red_comp[N-2] |
// +--------------------+--------------------+--------------------+-------------+------------------------+ (N-1)x4 + 3xNxNxNx2 + 8
// | sg_green_comp[0] | sg_ green_comp[1] | sg_ green_comp[2] | ... | sg_green_comp[N-2] |
// +--------------------+--------------------+--------------------+-------------+------------------------+ 2x(N-1)x4 + 3xNxNxNx2 + 8
// | sg_ blue_comp[0] | sg_ blue_comp[1] | sg_ blue_comp[2] | ... | sg_ blue_comp[N-2] |
// +--------------------+--------------------+------------------- +-------------+------------------------+ 3x(N-1)x4 + 3xNxNxNx2 + 8
//
// Maximum size = 3 x(17 - 1) x 4 + 3 x 17 x 17 x 17 x 2 + 8 = 29678 bytes.
//
Method (PWGM, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the WGM buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (TBUF, Buffer() {0x0} )
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(TBUF)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Arg1 - Data size
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(TBUF), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBUF
CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
// Return the packet data
Return(RBUF)
}
//
// PGRT - panel gamma response table
//
// This method returns the Gamma response table for a panel.
// The table is given in 2 arrays, one representing the x axis or grayscale and other
// representing the y axis or luminance.
//
// The table is given in a 256 entries array, where the first entry value represents
// the luminance (Y) achieved when displaying black on the screen (shade value is 0
// for all R, G and B) and the last entry represents the luminance (Y) achieved when
// displaying white on the screen (shade value is 255 for all R, G and B).
//
// The array must be 256 entries.
//
// The range of each entry must be from 0 to 0xffff
//
// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and
// {0x02, 0x01} represents 0x0102
//
// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+
// | Y[0] | Y[1] | Y[2] | ... | Y[255] |
// +---------------+---------------+---------------+-----------+---------------+
Method (PGRT, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the GRT buffer and return the data
// If nothing specified return NULL
Name (RBUF, Buffer() {0x0})
// Return the packet data
Return(RBUF)
}
//
// PBRT - panel backlight response table
//
// This method returns the Backlight response table for a panel.
// The table is given in a 256 entries array, where the first entry value represents
// the backlight level (BL) to achieve 0 luminance and the last entry represents
// the highest backlight level to achieve the maximum desired luminance.
// In other words, this array serves as a map from luminance to backlight levels,
// where the index is the desired luminance level and the value (or output) is
// the backlight level to be sent to the hardware (backlight controller).
//
// The array must be 256 entries.
//
// The range of each entry must be from 0 to 0xffff
//
// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and
// {0x02, 0x01} represents 0x0102
//
// +--- 2 bytes ---+--- 2 bytes ---+--- 2 bytes ---+-----------+--- 2 bytes ---+
// | BL[0] | BL[1] | BL[2] | ... | BL[255] |
// +---------------+---------------+---------------+-----------+---------------+
Method (PBRT, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the BRT buffer and return the data
// If nothing specified return NULL
Name (RBUF, Buffer() {0x0})
// Return the packet data
Return(RBUF)
}
//
// PBRC - panel backlight response curve for CABL
//
// This method returns the Backlight response curve for a panel used specifically for CABL algorithm.
// The curve is represented in a maximum 1024 x 2 elements array, where the first entry in each row
// will be backlight level and next entry will be correponding luminance value. In other words,
// this array serves as a map from backlight to luminance levels.
// First row will be number of control points in the backlight curve. Maximum number of points allowed is 1024.
// Points on the backlight response curve has to be specified in increasing order i.e last control point will
// correspond for maximum backlight value and first control point will correspond for minimum backlight value.
// The buffer must be of 4*(2*x + 1) bytes. where x < 1024 is number of control points.
//
// The range of each backlight or luminance value must be from 0 to 0xffff. ( 2 bytes each )
//
// Values are least significant byte first. E.g. {0x01, 0x00} represents 0x1 and
// {0x02, 0x01} represents 0x0102.
// Below is an example of Backlight Response curve consisting of 5 control points.
// +----- 2 bytes -----------+----- 2 bytes ------+
// | table_length | |
// +-------------------------+--------------------+
// | BacklightLevel[0] | Luminance[0] |
// +-------------------------+--------------------+
// | BacklightLevel[1] | Luminance[1] |
// +-------------------------+--------------------+
// | BacklightLevel[2] | Luminance[2] |
// +-------------------------+--------------------+
// | BacklightLevel[3] | Luminance[3] |
// +-------------------------+--------------------+
// | BacklightLevel[4] | Luminance[4] |
// +-------------------------+--------------------+
Method (PBRC, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the BRC buffer and return the data
// If nothing specified return NULL
Name (RBUF, Buffer() {0x00,0x00})
// Return the packet data
Return(RBUF)
}
//
// DITH method - Dithering settings
//
// Dithering matrix could have following two formats:
//
// Format 1:
// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------+
// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] |
// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] |
// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] |
// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] |
// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) |
// +----------------+----------------+----------------+----------------+
// | Dithering mode (4 bytes) (0: not supported, 1:Spatial, 2:Temporal)|
// +----------------+----------------+----------------+----------------+
//
// There is dithering mode in Format 1.
//
// Format 2:
//
// +--1 byte--------+--1 byte--------+--1 byte--------+--1 byte--------++
// | Element[0,0] | Element[0,1] | Element[0,2] | Element[0,3] |
// | Element[1,0] | Element[1,1] | Element[1,2] | Element[1,3] |
// | Element[2,0] | Element[2,1] | Element[2,2] | Element[2,3] |
// | Element[3,0] | Element[3,1] | Element[3,2] | Element[3,3] |
// | Bit Depth C2 | Bit Depth C1 | Bit Depth C0 | Reserved(0x0) |
// +----------------+----------------+----------------+----------------+
//
// There is no dithering mode in Format 2. Default dither mode: spatial.
//
Method (DITH, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the DITH buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
// Include primary panel specific configuration for backlight control packets
//
Include("backlightcfg.asl")

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DSDT/polaris/display2.asl Normal file
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//
// This file contains the ACPI Extensions for Secondary Display Adapters
//
//
// ROM2 Method - Used to retrieve proprietary ROM data for secondary panel
//
Method (ROM2, 3, NotSerialized) {
// Include secondary panel specific ROM data
Include("panelcfg2.asl")
//======================================================================================
// Based on the panel Id(Arg2), store the buffer object into Local2
//
// IMPORTANT:
// PCFG is buffer name for all default panel configurations
// All other dynamically detected panel configurations must not use this name
//======================================================================================
While (One)
{
If (One)
{
Local2 = PCFG /* \_SB_.GPU0.ROM2.PCFG */
}
Break
}
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(Local2)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(Local2), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBuf
CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
Return(RBUF)
}
//
// IGC2 method - panel inverse gamma correction table.
//
// Secondary panel IGC2 configuration, format is same as IGCT of primary
// panel in display.asl
//
Method (IGC2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the IGC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// PCC2 method - panel color correction matrix
// Secondary panel PCC2 configuration, format is same as PPCC of primary
// panel in display.asl
//
Method (PCC2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the PCC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// GCT2 method - panel segment gamma correction table
// Secondary panel GCT2 configuration, format is same as PGCT of primary
// panel in display.asl
//
Method (GCT2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the GCT buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// LGC2 method - panel linear gamma correction table
// Secondary panel LGC2 configuration, format is same as PLGC of primary
// panel in display.asl
//
Method (LGC2, 3, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data offset
// Arg2 - Data size
// Based on the panel Id read the LGC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (TBUF, Buffer() {0x0} )
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg1, Sizeof(TBUF)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg1, Local1)
}
// Arg2 - Data size
// Ensure the size requested is less than 4k
If (LGreater(Arg2, 0x1000))
{
Store(0x1000, Local2)
}
else
{
Store(Arg2, Local2)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local1, Local2), Sizeof(TBUF)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(TBUF), Local1, Local2);
}
// Multiply offset and size by 8 to convert to bytes and create the RBUF
CreateField(TBUF, Multiply(0x8, Local1), Multiply(0x8, Local2), RBUF)
// Return the packet data
Return(RBUF)
}
//
// HSI2 method - HSIC settings
// Secondary panel HSI2 configuration, format is same as HSIC of primary
// panel in display.asl
//
Method (HSI2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the HSIC buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
//
// GMT2 - panel gamut mapping table for HW which support 9x9x9 gamut mapping:
// Secondary panel GMT2 configuration, format is same as PGMT of primary
// panel in display.asl
//
Method (GMT2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the GMT buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (TBUF, Buffer() {0x0} )
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(TBUF)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Arg1 - Data size
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(TBUF), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBUF
CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
// Return the packet data
Return(RBUF)
}
//
// WGM2 - panel gamut mapping data for HW which support 17x17x17 gamut mapping
// Secondary panel WGM2 configuration, format is same as PWGM of primary
// panel in display.asl
//
Method (WGM2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the WGM buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (TBUF, Buffer() {0x0} )
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(TBUF)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Arg1 - Data size
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(TBUF)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(TBUF), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBUF
CreateField(TBUF, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
// Return the packet data
Return(RBUF)
}
//
// GRT2 - panel gamma response table
// Secondary panel GRT2 configuration, format is same as PGRT of primary
// panel in display.asl
//
Method (GRT2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the GRT buffer and return the data
// If nothing specified return NULL
Name (RBUF, Buffer() {0x0})
// Return the packet data
Return(RBUF)
}
//
// BRT2 - panel backlight response table
// Secondary panel BRT2 configuration, format is same as PBRT of primary
// panel in display.asl
//
Method (BRT2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the BRT buffer and return the data
// If nothing specified return NULL
Name (RBUF, Buffer() {0x0})
// Return the packet data
Return(RBUF)
}
//
// DIT2 method - Dithering settings
// Secondary panel DIT2 configuration, format is same as DITH of primary
// panel in display.asl
//
Method (DIT2, 2, NotSerialized) {
// Arg0 - Panel ID
// Arg1 - Data size
// Based on the panel Id read the DITH buffer and return the data
// If nothing specified return NULL
// Create response buffer
Name (RBUF, Buffer() {0x0} )
// Return the packet data
Return(RBUF)
}
// Include secondary panel specific configuration for backlight control packets
//
Include("backlightcfg2.asl")

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//
// This file contains the ACPI Extensions for External Display Adapters
//
//
// ROE1 Method - Used to retrieve proprietary ROM data for External display
//
Method (ROE1, 3, NotSerialized) {
// Include external panel specific ROM data
Include("panelcfgext.asl")
// Store the panel configuration
Store (PCFG, Local2)
// Ensure offset does not exceed the buffer size
// otherwise return a Null terminated buffer
If (LGreaterEqual(Arg0, Sizeof(Local2)))
{
Return( Buffer(){0x0} )
}
Else
{
// Make a local copy of the offset
Store(Arg0, Local0)
}
// Ensure the size requested is less than 4k
If (LGreater(Arg1, 0x1000))
{
Store(0x1000, Local1)
}
else
{
Store(Arg1, Local1)
}
// Finaly ensure the total size does not exceed the size of the buffer
if (LGreater(Add(Local0, Local1), Sizeof(Local2)))
{
// Calculate the maximum size we can return
Subtract(Sizeof(Local2), Local0, Local1);
}
// Multiply offset and size by 8 to convert to bytes and create the RBuf
CreateField(Local2, Multiply(0x8, Local0), Multiply(0x8, Local1), RBUF)
Return(RBUF)
}

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// To enable SOC revision based run time differentiation, uncomment following line
// and uncomment SSID method in ABD device. The original string is artificailly set as
// 16 characters, so there is enough room to hold SOC revision string.
// To adjust the number, the MAX_SOCID_LEN macro as defined in ABD device.h should be
// adjusted at the same time.
Name (SOID, 348) // Holds the Chip Id
Name (SIDS, "SDM850") // Holds the Chip ID translated to a string
Name (SIDV, 0x00020001) // Holds the Chip Version as (major<<16)|(minor&0xffff)
Name (SVMJ, 2) // Holds the major Chip Version
Name (SVMI, 1) // Holds the minor Chip Version
Name (SDFE, 79) // Holds the Chip Family enum
Name (SFES, "899800000000000") // Holds the Chip Family translated to a string
Name (SIDM, 0x0000000FFFFF00FF) // Holds the Modem Support bit field
Name (SOSN, 0x000003F48D126594)
Name (RMTB, 0x85D00000)
Name (RMTX, 0x00200000)
Name (RFMB, 0x00000000)
Name (RFMS, 0x00000000)
Name (RFAB, 0x00000000)
Name (RFAS, 0x00000000)
// Who is in charge of this?
// Name (TPMA, 0x11111111) // Holds whether TPM is seperate app or combined with Winsecapp
// Name (TDTV, 0x6654504D) // Holds TPM type, by default it set to fTPM type
Name (TCMA, 0x8AB00000) // Holds TrEE Carveout Memory Address
Name (TCML, 0x01400000) // Holds TrEE Carveout Memory Length
// WTF?
// Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib
//Include("cust_dsdt_common.asl")
//Audio Drivers
Include("audio.asl")
//
// Storage - UFS/SD
//
Include("../common/ufs.asl")
// Include("../common/sdc.asl") // No SD slot
//
// ASL Bridge Device
//
Include("../common/abd.asl")
Name (ESNL, 20) // Exsoc name limit 20 characters
Name (DBFL, 23) // buffer Length, should be ESNL+3
//
// PMIC driver
//
Include("../common/pmic_core.asl")
//
// PMICTCC driver
//
Include("pmic_batt.asl")
Include("../common/pep_common.asl")
Include("cust_camera_resources.asl")
// Include("corebsp_wp_resources.asl")
// Include("nfc_resources.asl") // NFC
Include("cust_touch_resources.asl")
Include("../common/bam.asl")
Include("buses.asl")
// MPROC Drivers (PIL Driver and Subsystem Drivers)
Include("../common/win_mproc.asl")
Include("../common/syscache.asl")
Include("../common/HoyaSmmu.asl")
//Include("Ocmem.asl")
Include("graphics.asl")
//Include("OcmemTest.asl")
Include("../common/SCM.asl");
//
// SPMI driver
//
Include("../common/spmi.asl")
//
// TLMM controller.
//
Include("qcgpio.asl")
// Disbale PCIe
// Include("../common/pcie.asl")
Include("../common/cbsp_mproc.asl")
Include("../common/adsprpc.asl")
//
// RemoteFS
//
Include("../common/rfs.asl")
// Test Drivers
// Include("testdev.asl")
//
//
// Qualcomm IPA
Include("../common/ipa.asl")
Include("../common/gsi.asl")
//
//Qualcomm DIAG Service
//
Device (QDIG)
{
Name (_DEP, Package(0x1)
{
\_SB_.GLNK
})
Name (_HID, "QCOM0225")
Alias(\_SB.PSUB, _SUB)
}
Include("../common/qcdb.asl")
// Include("ssm.asl")
Include("../common/Pep_lpi.asl")
//
// QcRNG Driver (qcsecuremsm)
//
Device (QRNG)
{
Name (_DEP, Package(0x1) {
\_SB_.PEP0,
})
Name (_HID, "QCOM02FE")
Name (_UID, 0)
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// PRNG_CFG_EE2_EE2_PRNG_SUB register address space
Memory32Fixed (ReadWrite, 0x00793000, 0x00001000)
})
Return (RBUF)
}
}
//
// QCOM GPS
//
Include("../common/gps.asl")
// QDSS driver
Include("../common/Qdss.asl")
// QUPV3 GPI device node and resources
//
Include("../common/qgpi.asl")
Include("../common/qwpp.asl")
//Include("nfc.asl")
// Disabling QCSP Changes
//Include("qcsp.asl")
Include("../common/sar_manager.asl")

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//
// This file contains the Panel configuration for secondary display
//
// Panel configuration format is similar to primary panel in panelcfg.asl
//
Name (PCFG, Buffer() {0x0} )

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//
// This file contains the Panel configuration for external display
//
// Panel configuration format is similar to primary panel in panelcfg.asl
//
Name (PCFG, Buffer() {0x0} )

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//===========================================================================
// <pep_defaults.asl>
// DESCRIPTION
// This file contains default resource information. These are applied at either
// PEP boot time, on the ScreenOn event or on demand by the PEP driver.
//
//===========================================================================
Scope(\_SB.PEP0)
{
Method(LDRS){
return(NDRS)
}
Name( NDRS,
/**
* The default resources package is used by PEP to handle system default resources.
* Rather than having to declare them all in the SDF declaration, you define resources
* separately and annotate them by functionality. At runtime, the parsed resources
* will be placed into separate components within the SDF device node.
*
* The expected hiearchy of this package:
* DEFAULT_RESOURCES
* (WORKAROUND|OPTIMIZATION)
* String = Name
* For debugging and querying -- keep it short
* String = "BOOT", "SCREENON", "DEMAND"
* When to activate these resources
* RESOURCES
* The list of resources to activate for this set workaround / optimization
*
*/
package(){
"DEFAULT_RESOURCES",
package()
{
"OPTIMIZATION",
"CPU_CNOC_VOTE",
"BOOT",
package()
{
"RESOURCES",
package() {"BUSARB", package() {3, "ICBID_MASTER_APPSS_PROC", "ICBID_SLAVE_CLK_CTL", 1, 1, "SUPPRESSIBLE" }},
package()
{
"PMICVREGVOTE", // PMIC VREG resource
package()
{
"PPP_RESOURCE_ID_BUCK_BOOST1_B",
12, // Voltage Regulator type 12 = BOB
0, // Voltage = 0V
0, // SW Enable = Disable
2, // BOB Mode = Auto
"HLOS_DRV", // Optional: DRV Id (HLOS_DRV / DISPLAY_DRV)
"SUPPRESSIBLE", // Optional: Set Type (REQUIRED / SUPPRESSIBLE)
}
},
// TZ requirement for HW DRM
Package(){"CLOCK", Package(){"gcc_disp_ahb_clk", 1}},// enable clock
Package(){"CLOCK", Package(){"gcc_disp_ahb_clk", 9,8}},// mark suppressible
Package(){"CLOCK", Package(){"gcc_disp_ahb_clk", 9,12}},// always ON
},
},
})
}

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Scope(\_SB.PEP0)
{
Method(CTSN)
{
return (THSD)
}
Method(PEPH)
{
Return(Package()
{
"ACPI\\VEN_QCOM&DEV_0237",
})
}
Method(BCLH)
{
Return(Package()
{
"ACPI\\VEN_QCOM&DEV_0294",
})
}
// Thermal sensors PL specific configurations
Name(THSD,
Package()
{
// Below package contains a list of all the identified physical thermal sensors mapped to unique HIDs
//
Package()
{
21, //Total number of thermal physical sensors
// sensor HID, sensor number associated to HID
Package() {"ACPI\\VEN_QCOM&DEV_027F", 0},
Package() {"ACPI\\VEN_QCOM&DEV_0280", 1},
Package() {"ACPI\\VEN_QCOM&DEV_0281", 2},
Package() {"ACPI\\VEN_QCOM&DEV_0282", 3},
Package() {"ACPI\\VEN_QCOM&DEV_0283", 4},
Package() {"ACPI\\VEN_QCOM&DEV_0284", 5},
Package() {"ACPI\\VEN_QCOM&DEV_0285", 6},
Package() {"ACPI\\VEN_QCOM&DEV_0286", 7},
Package() {"ACPI\\VEN_QCOM&DEV_0287", 8},
Package() {"ACPI\\VEN_QCOM&DEV_0288", 9},
Package() {"ACPI\\VEN_QCOM&DEV_0289", 10},
Package() {"ACPI\\VEN_QCOM&DEV_02AB", 11},
Package() {"ACPI\\VEN_QCOM&DEV_02AC", 12},
Package() {"ACPI\\VEN_QCOM&DEV_02AD", 13},
package() {"ACPI\\VEN_QCOM&DEV_02AE", 14},
Package() {"ACPI\\VEN_QCOM&DEV_02AF", 15},
Package() {"ACPI\\VEN_QCOM&DEV_02C8", 16},
Package() {"ACPI\\VEN_QCOM&DEV_02C9", 17},
Package() {"ACPI\\VEN_QCOM&DEV_02CA", 18},
Package() {"ACPI\\VEN_QCOM&DEV_02CB", 19},
Package() {"ACPI\\VEN_QCOM&DEV_02CC", 20},
},
// TSENSLIST Package
// This package contains "lists" of thermal sensors
// each list maps to a virtual thermal sensor
// Always the first package should be BIG CPU, second one is LITTLE CPU and third one is ALL CPU SENSOR lists.
// Do not interchage inside packages. Always add new sensor list package at the end.
Package()
{
3, //Number of virtual sensors.
Package() // sensors associated with Little CPU
{
"ACPI\\VEN_QCOM&DEV_02B0",
21, // virtual sensor ID
5, //Little cpu sensors
Package () {1, 2, 3, 4, 5},
},
Package() // sensors associated with Big CPU
{
"ACPI\\VEN_QCOM&DEV_02B1",
22, // virtual sensor ID
5, //Big cpu sensors
Package () {6, 7, 8, 9, 10}, // as per thermal floor plan
},
Package() // All MSM sensors
{
"ACPI\\VEN_QCOM&DEV_02B2",
23, // virtual sensor ID
21, //It should be total number of sensors.
Package () {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20},
},
},
// Sensor HID to Vadc thermistor mapping package
// INX and this needs to be in sync
// channel list/names need to obtained from tsens team
Package ()
{
10, //Number of VADC channels
// channels name sensor HID, Sensor number ADC type
Package() {"SYS_THERM1", "ACPI\\VEN_QCOM&DEV_0299", 0, 0}, //vadc = 0, rradc = 1
Package() {"SYS_THERM2", "ACPI\\VEN_QCOM&DEV_029A", 1, 0 },
Package() {"PA_THERM", "ACPI\\VEN_QCOM&DEV_029B", 2, 0 },
Package() {"PA_THERM1", "ACPI\\VEN_QCOM&DEV_029C", 3, 0 },
Package() {"SYS_THERM3", "ACPI\\VEN_QCOM&DEV_029D", 4, 0 },
Package() {"PMIC_THERM", "ACPI\\VEN_QCOM&DEV_029E", 5, 0 },
Package() {"SKIN_THERM", "ACPI\\VEN_QCOM&DEV_029F", 6, 1 },
Package() {"PMIC_TEMP2", "ACPI\\VEN_QCOM&DEV_02A0", 7, 1 },
Package() {"CHG_TEMP", "ACPI\\VEN_QCOM&DEV_02EE", 8, 1 },
Package() {"BATT_THERM", "ACPI\\VEN_QCOM&DEV_02EF", 9, 1 },
},
// Thermal Restriction data package
// high/low trigger point for each thermal restriction
// ID has to match to one of below enum from PEP_Themal_common.h
//typedef enum _INT_RESTR_ID
//{
// FAST_THERMAL_MTG_RESTR_B_ID = 0x01, //Throttle just the big cluster to NOM
// LOW_TEMP_VOLTAGE_RESTR_ID = 0x02, //Vdd restriction at < 5C
// HIGH_TEMP_BOOST_RESTR_ID = 0x03, //Unused- Turn off Correlation
// NORMAL_TEMP_CL_RESTR_ID = 0x04, //8909 - Current Limiting - Disabled
// HIGH_TEMP_CL_RESTR_ID = 0x05, //8909 - Current Limiting - Disabled
// VERY_HIGH_TEMP_CL_RESTR_ID = 0x06, //8909 - Current Limiting - Disabled
// MAX_PERF_LIMITING_RESTR_ID = 0x7, //8994 - Num cores based perf limiting
// FAST_THERMAL_MTG_RESTR_L_ID = 0x8, //Throttle Little clusters to NOM
// INVALID_RESTR_ID = 0xffffffff,
//} INT_RESTR_ID, *PINT_RESTR_ID;
//
Package ()
{
1, // number of Thermal Restrictions
Package ()
{
2, // tsensList. 2 indicates third package in TSENSLIST Package. In this case its All CPU sensors list
2780, // Restriction ON temperature. ACPI uses 10s of K as temperatures, so 0C = 2730 ACPI UNITS. 2730+50=2780.
2830, // Restriction OFF temperature. 100 + 2730 = 2830.
2, // 2 - LOW_TEMP_VOLTAGE_RESTR_ID, Vdd restriction at < 5C
1, // Restriction enabled = 1, disabled = 0.
},
},
//QMI clients
Package ()
{
4, // Number Of QMI Clients.
Package ()
{
"cpuv_restriction_cold", //mitigation device name
1, //restriction ON = 1 and RESTRICTN OFF = 0
0, //MODEM QMI INSTANCE ID = 0
},
Package ()
{
"cpuv_restriction_cold", //mitigation device name
1, //restriction ON = 1 and RESTRICTN OFF = 0
1, //ADSP QMI INSTANCE ID = 1
},
Package ()
{
"cpuv_restriction_cold", //mitigation device name
1, //restriction ON = 1 and RESTRICTN OFF = 0
0x43, //CDSP QMI INSTANCE ID = 0x43
},
Package ()
{
"cpuv_restriction_cold", //mitigation device name
1, //restriction ON = 1 and RESTRICTN OFF = 0
0x53, //SLPI QMI INSTANCE ID = 0x53
},
},
// PPP PMIC VREG clients: ACPI is being parsed in the order defined in PEP_Thermal_Common.h
// Client info will be parsed incorrectly, if this package is removed.
Package ()
{
0,
},
// LTVR Package having 3 sub-packages:
// 1) Rail type from enum RAIL_TYPE in PEP_Thermal_Common.h
// 2) Voting type - available options are EnableKraitVFC(0), VoteViaPPP(1), VoteViaQMI(2), VoteViaAOP(3) and VoteViaCallBackObj(4)
// 3) Client subpackage number for Voting type clients package
// VoteViaAOP
// AOP does not require rail type to vote during LTVR.
// It just needs an event with value on or off and it places NOM vote on cx, mx & ebi.
// Only cx is added to get callback in LTVR.
// VoteViaCallBackObj
// LTVR callback notifies to all the registered clients. it is independent of rail type and voting type.
//
Package () // LTVR VFC vote table
{
7, // Available Rails
Package() { 0, //KRAIT = 0,
0, //EnableKraitVFC = 0
0, // NULL
},
Package() { 1, //CX = 1,
3, //VoteViaAOP = 3
0, // NULL : Client data is not required;
},
Package() { 3, //MSS = 3,
2, //VoteViaQMI = 2
0, // 0 represents first package in QMI clients list
},
Package() { 4, //ADSP = 4,
2, //VoteViaQMI = 2
1, // 1 represents second package in QMI clients list
},
Package() { 6, //CDSP = 6,
2, //VoteViaQMI = 2
2, // 2 represents third package in QMI clients
},
Package() { 8, //SLPI = 8,
2, //VoteViaQMI = 2
3, // 3 represents forth package in QMI clients
},
Package() { 2, //GFX = 2, NOP because call backs will be notified for all the registered clients.
// No need for separate rail entry for each of the rails which are relying on call backs.
4, //VoteViaCallBackObj = 4.
0, // NOP.
},
}
}
)
}

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//
// This file contains the Power Management IC (PMIC)
// ACPI device definitions, configuration and look-up tables.
//
Include("cust_pmic_batt.asl")
// PMIC EIC (Might be external charging chip on i2c)
//Device (PEIC)
//{
// Name (_HID, "QCOM02D3")
// Alias(\_SB.PSUB, _SUB)
// Method (_CRS, 0x0, NotSerialized) {
// Name (RBUF, ResourceTemplate () {
// // SMB1380
// I2CSerialBus( 0x08, , 400000,AddressingMode7Bit, "\\_SB.IC11",,,,)
// })
// Return (RBUF)
// }
// Method (PMCF) {
// Name (CFG0,
// Package(){
// //Charger Info
// 0, // I2c Index - Resource Index
// 2, // Charger IC Type - PLAT_CONFIG_CHG_IC_SMB1380
// })
// Return (CFG0)
// }
//
// Method (_STA) {
// Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
// }
//}
//
// PMIC Battery Manger Driver
//
Device (PMBT) {
Name (_HID, "QCOM0264")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x2) {
\_SB_.PMIC,
\_SB_.ADC1,
//\_SB_.PEIC
})
Method (_STA) {
Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
}
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
//GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {208} // 0x80 - PM_INT__SCHG_CHGR__CHGR_ERROR_RT_STS - Charger Error Interrupt
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - IBAT greater than threshold Interrupt.
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - VBatt less than threshold Interrupt
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {352} // 0x220 - PM_INT__FG_MEM_IF__IMA_RDY - MEMIF access Interrupt
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {215} // 0x87 - PM_INT__SCHG_CHGR__CHGR_7 - Termination Current Interrupt
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {209} // 0x81 - PM_INT__SCHG_CHGR__CHARGING_STATE_CHANGE - Charger Inhibit Interrupt
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {329} // 0x209 - PM_INT__FG_BATT_INFO__VBT_LOW - VBAT_LOW Interrupt
//GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,) {240} // 0xA0 - PM_INT__SCHG_DC__DCIN_COLLAPSE - Qi Wireless Charger Interrupt
GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {331} // 0x20B - PM_INT__FG_BATT_INFO__BT_MISS - BATT_MISSING Interrupt
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {237} // 0x9D - PM_INT__SCHG_USB__USBIN_SOURCE_CHANGE - AICL_DONE IRQ (Rising Only)
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {232} // 0x98 - PM_INT__SCHG_USB__USBIN_COLLAPSE - USB_UV IRQ (Rising Only)
//GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {322} // 0x202 - PM_INT__FG_BATT_SOC__BSOC_DELTA - FULL_SOC Interrupt
//GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {323} // 0x203 - PM_INT__FG_BATT_SOC__MSOC_DELTA - EMPTY_SOC Interrupt
// GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {213} // 0x85 - PM_INT__SCHG_CHGR__FG_FVCAL_QUALIFIED - FVCAL_QUALIFIED IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {224} // 0x90 - PM_INT__SCHG_BATIF__BAT_TEMP - Jeita limit interrupt
})
Return (RBUF)
}
//ACPI methods for Battery Manager Device
Method (BMNR) {
Name (CFG0,
Package(){
1, //* 0: Select Platform: 0- No HW, 1- SMChg+FGGge, 2- SMB3pChg+SMB3pGge, 3- LBChg+VMBMS
0, //* 1: Error State Handling: 0- Don<6F>t Shutdown, 1- Shutdown
1, //* 2: Listen to BatteryClass: 0- No 1- Yes
0, //* 3: Test Mode Power Flag: 0- Discharging, 1- PowerOnline+Charging
"CUST_PMIC" //* 4: cust_pmic config identifier
})
Store(CUST, Index(CFG0, 4))
Return (CFG0)
}
//ACPI methods for Timer
Method (BTIM) {
Name (CFG0,
Package(){
30000, // Charging Heartbeat Timer
10000, // Charging Tolerable Delay
300000, // Discharging Heartbeat Timer
120000, // Discharging Tolerable Delay
0, // Poll Timer , 0=Timer not used.
0, // Poll Tolerable Delay
28080000, // Charging Timeout (TDone) Timer
0, // Charging Timeout(TDone) Tolerable Delay
})
Return (CFG0)
}
//ACPI methods for Battery Info
Method (BBAT) {
Name (CFG0,
Package(){
1, //* 0: Battery Technology
0x4C494F4E, //* 1: Battery Chemistry: hex(LION)
0xFFFFFFFF, //* 2: BFCC: (mWh), Design Capacity
0xFFFFFFFF, //* 3: BFCC: (mWh), Full Charge Capacity
0xFFFFFFFF, //* 4: PCT1: (% of FCC), Default Alert 1
0xFFFFFFFF, //* 5: PCT2: (% of FCC), Default Alert 2
"QCOMBATT01", //* 6: Device Name
"Qualcomm", //* 7: Manufacture Name
"QCOMBAT01_07012011", //* 8: Battery Unique ID
"07012011", //* 9: Battery Serial Number
19, //* 10: Battery Manufacture Date
04, //* 11: Battery Manufacture Month
2014 //* 12: Battery Manufacture Year
})
//Local2 = Default Alert1 = PCT1 * BFCC / 100
Multiply(PCT1,BFCC,Local0)
Divide(Local0, 100, Local1, Local2)
//Local3 = Default Alert2 = PCT2 * BFCC / 100
Multiply(PCT2,BFCC,Local0)
Divide(Local0, 100, Local1, Local3)
Store(BFCC, Index(CFG0, 2))
Store(BFCC, Index(CFG0, 3))
Store(Local2, Index(CFG0, 4))
Store(Local3, Index(CFG0, 5))
Return (CFG0)
}
//ACPI methods for Proprietary chargers
Method (BPCH) {
Name (CFG0,
Package(){
3000, // QC2.0 charger current = 3000mA
3000, // QC3.0 charger current = 3000mA
1500 // Invalid Wall charger current = 1500mA
})
Return (CFG0)
}
//ACPI methods for foldback chargers
Method (BFCH) {
Name (CFG0,
Package(){
1, // Feature enable/disable
5, // No of consecutive times charger attach/detach
5000, // msecs, Time elapsed between attach/detach
900, // mA, Current setting for foldback charger
})
Return (CFG0)
}
//ACPI methods for coin cell charger
Method (BCCC) {
Name (CFG0,
Package(){
1, //Enable coin cell charger; 1 = enable, 0 = disable
0, // RSET, 0=2K1, 1=1K7, 2=1K2, 3 = 0K8
0 // VSET, 0=2V5, 1=3V2, 2=3V1, 3=3V0
})
Return (CFG0)
}
//ACPI methods for Recharge/Maintenance Mode
Method (BRCH) {
Name (CFG0,
Package(){
100, // Delta V Recharge threshold = 100mV
0 // Delta V Recharge Reduction below Normal= 0mV
})
Return (CFG0)
}
//ACPI methods for Qi Charging
Method (_BQI) {
Name (CFG0,
Package(){
0,
})
Return (CFG0)
}
//ACPI methods for Interrupt Name
Method (BIRQ) {
Name (CFG0,
Package(){
//"ChgError", // Charger Error
//"BclIrq1", // IBAT greater than threshold IRQ
//"BclIrq2", // VBAT less than threshold IRQ
//"MEMIFaccess", // MEMIF access granted IRQ
//"TccReached", // Termination Current IRQ
//"ChargerInhibit" // Charger Inhibit IRQ
"VbatLow", // VBAT LOW IRQ
//"QiWlcDet", // Qi charging
"BattMissing", // BATT_MISSING IRQ
"AiclDone", // AICL Done
//"UsbUv", // USB UV
//"SOCFull", // SOC Full IRQ
//"SOCEmpty", // SOC Empty IRQ
//"FvCal", // FVCAl IRQ
"JeitaLimit" // JEITA limit IRQ
})
Return (CFG0)
}
//ACPI methods for Platform File
Method (BPLT) {
Name (CFG0,
Package(){
1024, //* 0: ACPI Version
0xFFFFFFFF, //* 1: VNOM: (mV), Nominal Battery Voltage
0xFFFFFFFF, //* 2: VLOW: (mV), Low Battery Voltage
0xFFFFFFFF, //* 3: EMPT: (mV), VcutOff
0xFFFFFFFF, //* 4: DCMA: (mA), DC Current
1, //* 5: ChargePath Priority: Select 0 for DC, 1 for USB
50, //* 6: RSLOW for maxFlashCurrentPrediction
50, //* 7: RPARA for maxFlashCurrentPrediction
5000, //* 8: VINFLASH for maxFlashCurrentPrediction
8, //* 9: FlashParam for maxFlashCurrentPrediction
1, //* 10: AFP Mode Supported
80, //* 11: AFP Trigger Max Battery Temp (+80 deg C)
0xFFFFFFEC, //* 12: AFP Trigger Min Battery Temp (-20 deg C)
72, //* 13: Watchdog timer in secs
100, //* 14: Charger iterm 100 mA for now
30, //* 15: SRAM logging timer
5, //* 16: VBATT average Window Size
6, //* 17: Emergency Shutdown Initial SOC
500, //* 18: SoC convergent point
126, //* 19: LM_Threshold
400, //* 20: MH_Threshold
0xFFFFFFFF, //* 21: BOCP: (mA), OCP current used in BCL
750, //* 22: soc (75%) below which no soc linearization even in CV charging
1, //* 23: BMD - Battery Missing Detection Source when source is attached: BATT_ID (1=BATT_ID, 4=HW Misssing Algorithm)
2, //* 24: ibat src sensing : 0 for batfet and 1 for external sensing
50, //* 25: IFGD: (mA), FG Iterm delta; (iterm + this value) determines when FG report 100%
10, //* 26: VFGD: (mV), CC to CV Vdelta; (Vfloat - this value) determine when FG report 100%
1, //* 27: 0 - disable SOC linearization; 1 (nonzero): enable SOC linearization
0xFFFFFFEC, //* 28: (Celcius), Temperature threshold do have different SOC slope limiter
10, //* 29: (milli%) - SOC slope limiter when charging and at lower temperature than threshold
10, //* 30: (milli%) - SOC slope limiter when charging and at higher temperature than threshold
10, //* 31: (milli%) - SOC slope limiter when discharging and at lower temperature than threshold
10, //* 32: (milli%) - SOC slope limiter when discharging and at higher temperature than threshold
1, //* 33: 0 - disable FCC learning; 1 (nonzero): enable FCC leearning
150, //* 34: maximum starting SOC (in tenth percent)at which FCC learning would be turned on during charging
100, //* 35: maximum allowable decrement (in tenth percent) of battery capacity in FCC learning
5, //* 36: maximum allowable increment (in tenth percent) of battery capacity in FCC learning
10, //* 37: battery temperature in degree C below which switch to low temp ESR update steps
0x02, //* 38: ESR update step tight, (2 * 0.001953 = 0.0039 = 0.4% max change each update)
0x33, //* 39: ESR update step broad, (51* 0.001953 = 0.099603 = 10% max change each update)
0x02, //* 40: ESR update step tight at low temp (below 10 degree, 0.4% max change each update)
0x0A, //* 41: ESR update step broad at low temp (below 10 degree, 2% max change each update)
0, //* 42: mOhm, RConn
0, //* 43: Type C Thermal Mitigation Enable
70, //* 44: Temperature to arm mitigation (degree C)
50, //* 45: ICL adjustment (percent)
60 //* 46: Temperature to disarm mitigation (degree C)
})
Store(VNOM, Index(CFG0, 1))
Store(VLOW, Index(CFG0, 2))
Store(EMPT, Index(CFG0, 3))
Store(DCMA, Index(CFG0, 4))
Store(BOCP, Index(CFG0, 21))
Store(IFGD, Index(CFG0, 25))
Store(VFGD, Index(CFG0, 26))
Return (CFG0)
}
//ACPI methods for Platform File
Method (BPTM) {
Name (CFG0,
Package(){
15000, // Emergency Timer
0, // Emergency Tolerable Delay
})
Return (CFG0)
}
//*****************************************************
// Battery Charge Table 1 (BCT1)
// Notes: used in Method(BJTA) & Method (BAT1)
//*****************************************************
Name (BCT1, Package(){
4350, //* 0: VDD1: (mV), Float Voltage (FV)
2100, //* 1: FCC1: (mA), Full Charge Current (FCC)
0, //* 2: HCLI: (C) hard cold limit - at which temperature charging will be disabled
10, //* 3: SCLI: (C) soft cold limit - at which temperature charge current/float voltage will be reduced to JEITA compensated value
45, //* 4: SHLI: (C) soft hot limit - at which temperature float voltage/charge current will be reduced to JEITA compensated value
55, //* 5: HHLI: (C) hard hot limit - at which temperature charging will be disabled
105, //* 6: FVC1: (mV) Float Voltage compensation (amount of FV reduction) when in battery hot-soft limit
0, //* 7: (mV) Float Voltage compensation (amount of FV reduction) when in battery cold-soft limit
//* notes: put 0 value to disable
//* These values (10 vs 11) should be the same when HW JEITA is enabled
0, //* 8: (mA) Charge Current compensation (amount of CC reduction) when in battery hot-soft limit
1000, //* 9: CCC1: (mA) Charge Current compensation (amount of CC reduction) when in battery cold-soft limit
//* notes: put 0 value to disable
//* These values (12 vs 13) should be the same when HW JEITA is enabled
})
//ACPI methods for JEITA
Method (BJTA) {
Name (CFG0,
Package(){
2, //* 0: Select JEITA Configuration: 0- No JEITA, 1- SW JEITA, 2- HW JEITA
2, //* 1: Temperature Hysteresis (in deg C)
Package(0xa){0,0,0,0,0,0,0,0,0,0}
//* 2: Structure for default charge table
})
Store(VDD1, Index(\_SB_.PMBT.BCT1, 0))
Store(FCC1, Index(\_SB_.PMBT.BCT1, 1))
Store(HCLI, Index(\_SB_.PMBT.BCT1, 2))
Store(SCLI, Index(\_SB_.PMBT.BCT1, 3))
Store(SHLI, Index(\_SB_.PMBT.BCT1, 4))
Store(HHLI, Index(\_SB_.PMBT.BCT1, 5))
Store(FVC1, Index(\_SB_.PMBT.BCT1, 6))
Store(CCC1, Index(\_SB_.PMBT.BCT1, 9))
//Use BCT1 as the Default Charge Table
Store(\_SB_.PMBT.BCT1, Index(CFG0, 2))
Return (CFG0)
}
//ACPI methods for Battery-1 (Ascent 860-82209-0000 3450mAh)
Method (BAT1)
{
Name (CFG0,
Package(){
0, //* 0: Battery Category: 0-NORMAL, 1-SMART
0xFFFFFFEC, //* 1: min operating battery temp (-20 deg C)
65, //* 2: max operating battery temp (+65 deg C)
Package(4){0,0,0,0}, //* 3: 128-bit battery info for future expansion
Package(0xa){0,0,0,0,0,0,0,0,0,0}
//* 4: Structure for charge table
})
//assign Charge Table to BCT1
//Notes: 1) If the default charge table and desire charge table are different,
// Create another table (ex: BCT2) with the same structure as BCT1 and modify BCT1 below with the new table name
// 2) Method(BJTA) is parsed before this(BAT1) method in Battmngr module
// Method(BJTA) may be updating BCT1 parameters using configuration from cust_pmic_batt.asl (refer to BJTA method details)
// If BAT1 desires different value to be used (than what used in BJTA), pls change/update relevant parameter(s) here.
Store(\_SB_.PMBT.BCT1, Index(CFG0, 4))
Return (CFG0)
}
//ACPI methods for Battery Error Handling
Method (BEHC)
{
//Actions for Battery Error Handling
// 0x0 - Do Nothing
// 0x1 - Reload Charge Table
// 0x2 - Error Shutdown
// 0x4 - Emergency Shutdown
// 0x8 - Enter Test Mode
Name (CFG0,
Package(){
1, // 1-Feature Enable, 0-Feature Disable
0x8, //Action(s) for DEBUG state -> Enter Test Mode
0x1, //Action(s) for NORMAL state -> Reload Charge Table
0x0, //Action(s) for SMART_AUTHENTICATED state -> Do nothing
0x0, //Action(s) for UNKNOWN state -> Do nothing
0x2, //Action(s) for NOT_PRESENT state -> Error Shutdown
0x2, //Action(s) for INVALID state -> Error Shutdown
0x4 //Action(s) for OUT_OP_RANGE state -> AFP for out of operational range
})
Return (CFG0)
}
//ACPI methods for Charge Table Management Configuration
Method (CTMC)
{
Name (CFG0,
Package(){
2000, //* 0: min RID for DEBUG category: 2K
14000, //* 1: max RID for DEBUG category: 14K
0xFFFFFFFF, //* 2: RID2: min RID for NORMAL category: 15K
0xFFFFFFFF, //* 3: RID3: max RID for NORMAL category: 140K
240000, //* 4: min RID for SMART category: 240K
450000, //* 5: max RID for SMART category: 450K
1, //* 6: Number of charging table
})
Store(RID2, Index(CFG0, 2))
Store(RID3, Index(CFG0, 3))
Return (CFG0)
}
//ACPI methods for Parallel Charging
Method (BMPC) {
Name (CFG0,
Package(){
0, //* 0: Feaature Enable. 1: Enabled, 0: Disable
1, //* 1: Input Power Disctribution (HW) configuration: 0: MID-MID, 1: USBIN-USBIN
7000, //* 2: (mW) Input Power Threshold to decide if parallel charging to be enabled or not
//* Note: Not applicable for MID-MID configuration
1000, //* 3: (mA) Charge Current Threshold to decide if parallel charging to be enabled or not
50, //* 4: (%) Slave Charger Initial Power Distribution
60, //* 5: (mV) Slave Charger Float Voltage Headroom
500, //* 6: (mA) Slave Charger Charge Current Done Threshold
90, //* 7: Slave Charger Minimum Efficiency
0, //* 8: Slave Charger HW ID. 0: SMB1380/1
70, //* 9: (%)Slave Charger Max Power Distribution: 70%
0, //* 10: (%)Slave Charger Min Power Distribution: 0%
Package(0x4)//* 11: Thermal Balancing Configuration
{
5, //11.1: (C)Temperature Difference to trigger thermal balancing. 0 to disable the feature
5, //11.2: (%)Step to redistrubute the power
120, //11.3: (Sec)Minimum Wait Time for each redistribution attempt
5, //11.4: (C)Temperature Margin for Master Charger
}
})
Return (CFG0)
}
}
//
// PMIC Battery Miniclass Driver
//
Device (PMBM) {
Name (_HID, "QCOM0263")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1)
{
\_SB_.PMBT
})
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate () {
})
Return (RBUF)
}
Method (_STA) {
Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
}
}
//
//FGBCL Driver
//
Device (BCL1) {
Name (_HID, "QCOM02D6")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1)
{
\_SB_.PMIC
})
Method (_STA) {
Return (0xB) // Device is installable, functional & should not be visible in OSPM/Device Manager
}
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate () {
GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {64} // 0x1E8 - PM_INT__BCL_COMP__VCOMP_LOW0 - VCOMP_LOW0 IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {65} // 0x1E9 - PM_INT__BCL_COMP__VCOMP_LOW1 - VCOMP_LOW1 IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {66} // 0x1EA - PM_INT__BCL_COMP__VCOMP_LOW2 - VCOMP_LOW2 IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {67} // 0x1EB - PM_INT__BCL_COMP__VCOMP_HI - VCOMP_HI IRQ
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {68} // 0x1EC - PM_INT__BCL_COMP__SYS_OK - SYS_OK IRQ
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {72} // 0x1F0 - PM_INT__BCL_PLM__VCOMP_LVL0_PLM - LVL0_PLM IRQ
//GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {74} // 0x1F2 -PM_INT__BCL_PLM__VCOMP_LVL2_PLM - LVL2_PLM IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {75} // 0x1F3 - PM_INT__BCL_PLM__VCOMP_BA - BAN alarm IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {336} // 0x210 - PM_INT__FG_BCL__IBT_HI - ibatt high IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {337} // 0x211 - PM_INT__FG_BCL__IBT_THI - ibatt too high IRQ
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {339} // 0x213 - PM_INT__FG_BCL__VBT_LO_CMP - vbatt low irq
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {340} // 0x214 - PM_INT__FG_BCL__VBT_TLO_CMP - vbatt too low irq
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {324} // 0x204 - PM_INT__FG_BATT_SOC__MSOC_LOW - MSOC_Low Interrupt
GpioInt(Edge, ActiveHigh, Shared, PullUp, 0, "\\_SB.PM01",,,,) {326} // 0x206 - PM_INT__FG_BATT_SOC__MSOC_HIGH - MSOC_HI Interrupt
GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {344} // 0x218 - PM_INT__FG_LMH__LMH_LVL0 - LMH_LVL0 IRQ
GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {345} // 0x219 - PM_INT__FG_LMH__LMH_LVL1 - LMH_LVL1 IRQ
GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.PM01",,,,RawDataBuffer(){0x08}) {346} // 0x21A - PM_INT__FG_LMH__LMH_LVL2 - LMH_LVL2 IRQ
})
Return (RBUF)
}
//ACPI methods for FGBCL device
Method (BCLS) {
Name (CFG0,
Package(){
3, //* FGBCL ACPI revision
7, //* 0: BCL disabled, 1: vph_pwr bcl enabled, 2: fg vbatt enabled, 4: fg ibatt enabled
5000, //* battery ocp current
80, //* ibatt high threshold is set to 80 for 80% of OCP
90, //* ibatt too high is set to 90 for 90% of OCP
2800, //* vbatt low is set to 2800 mV
2600, //* vbatt too low is set to 2600 mV
3200, //* vcomp_low0 threshold is 3200 mv
2750, //* vcomp_low1 threshold is 2750 mv
2500, //* vcomp_low2 threshold is 2500 mV
10, //* poll timer for battery soc polling.
1, //* 1- enable battery percent notification. 0-disable battery percent notification
2000, //* debug board Min battery ID in Ohm
14000 //* debug board Max battery ID in Ohm
})
Return (CFG0)
}
//ACPI methods for Interrupt Name
Method (BCLQ) {
Name (CFG0,
Package(){
"VCOMP_LOW0", // vcomp_low0 IRQ
"VCOMP_LOW1", // vcomp_low1 IRQ
"VCOMP_LOW2", // vcomp_low2 IRQ
"VCOMP_HI", // vcomp_hi IRQ
//"SYS_OK", // sys_ok irq
//"LVL0_PLM", // LVL0_PLM IRQ
//"LVL1_PLM" // LVL1_PLM IRQ
//"LVL2_PLM", // LVL2_PLM IRQ
"BAN_ALARM", // BAN_ALARM IRQ
"IBATT_HI", // IBATT HIGH IRQ
"IBATT_THI", // IBATT TOO HIGH IRQ
"VBATT_LOW", // VBATT_LOW IRQ
"VBATT_TLOW", // VBATT TOO LOW IRQ
"MSOC_LOW", // monotonic soc low IRQ
"MSOC_HI", // monotonic soc high IRQ
"LMH_LVL0", // LMH_LVL0 IRQ
"LMH_LVL1", // LMH_LVL1 IRQ
"LMH_LVL2", // LMH_LVL2 IRQ
})
Return (CFG0)
}
}
//
//PMIC Type-C Controler Driver (PMICTCC) Driver
//
Device(PTCC)
{
Name (_HID, "QCOM02E6")
Alias(\_SB.PSUB, _SUB)
Name (_DEP, Package(0x1) {\_SB_.PMIC})
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate () {
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {239} // 0x9F - PM_INT__SCHG_USB__TYPE_C_OR_RID_DETECTION_CHANGE - CC State Changed IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {270} // 0xBE - PM_INT__USB_PD__MESSAGE_RX_DISCARDED - Message RX Discarded IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {269} // 0xBD - PM_INT__USB_PD__MESSAGE_TX_DISCARDED - Message TX Discarded IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {268} // 0xBC - PM_INT__USB_PD__MESSAGE_TX_FAILED - Message TX Failed IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {267} // 0xBB - PM_INT__USB_PD__MESSAGE_RECEIVED - Message Received IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {266} // 0xBA - PM_INT__USB_PD__MESSAGE_SENT - Message Sent IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {265} // 0xB9 - PM_INT__USB_PD__SIGNAL_RECEIVED - Singal Received IRQ
GpioInt(Edge, ActiveHigh, SharedAndWake, PullNone, 0, "\\_SB.PM01",,,,) {264} // 0xB8 - PM_INT__USB_PD__SIGNAL_SENT - Signal Sent IRQ
GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {217} // 0x89 - PM_INT__SCHG_OTG__OTG_OVERCURRENT - OTG_OC_IRQ
GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {263} // 0xB7 - PM_INT__SCHG_MISC__SWITCHER_POWER_OK - SWITCHER_POWER_OK (CHG_MISC)
GpioInt(Edge, ActiveHigh, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {235} // 0x9B - PM_INT__SCHG_USB__USBIN_OV - USBIN_OV (CHG_USB)
// GpioIo (Exclusive, PullUp, 0, 0, , "\\_SB.PM01", , , , ) {493} // 0x668 - PM_INT__PM2_GPIO14__GPIO_IN_STS - GPIO14B <20> For Type-C Debug Accessory Mode
})
Return (RBUF)
}
}

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//
// TLMM controller.
//
Device (GIO0)
{
Name (_HID, "QCOM0217")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Method (_CRS, 0x0, NotSerialized) {
Name (RBUF, ResourceTemplate ()
{
// TLMM register address space
Memory32Fixed (ReadWrite, 0x03400000, 0x00C00000)
// Summary Interrupt shared by all banks
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240}
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240}
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240}
Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {648} // For PDC Wake up ::TLMM GPIo 126 SD Card Detection
Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {568} // For PDC Wake up ::TLMM GPIo 54
Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {646} // For PDC Wake up ::TLMM GPIo 124, Hall sensor used for lid
})
Return (RBUF)
}
// ACPI method to return Num pins
Method(OFNI, 0x0, NotSerialized) {
Name(RBUF, Buffer()
{
0x96, // 0: TOTAL_GPIO_PINS
0x00 // 1: TOTAL_GPIO_PINS
})
Return (RBUF)
}
Name(GABL, Zero)
Method(_REG, 0x2, NotSerialized)
{
If(LEqual(Arg0, 0x8))
{
Store(Arg1, GABL)
}
}
}

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Name(QUFN, 0x0 ) //enable flag for QcUsbFN driver stack
//Holds the DPDM Polarity
//USB_DPDM_INVALID_INVALID = 0
//USB_DPDM_INVALID_FALLING = 1
//USB_DPDM_INVALID_RISING = 2
//USB_DPDM_FALLING_INVALID = 3
//USB_DPDM_RISING_INVALID = 4
//USB_DPDM_FALLING_FALLING = 5
//USB_DPDM_FALLING_RISING = 6
//USB_DPDM_RISING_FALLING = 7
//USB_DPDM_RISING_RISING = 8
Name(DPP0, Buffer(){0x0})
//
// USB Role Switch
//
Device(URS0)
{
//select HID based on flag for QcUsbFN driver stack
Method (URSI) {
If(Lequal(\_SB.QUFN, 0x0)) {
return("QCOM0304")
}
Else{
return ("QCOM0305")
}
}
Alias(URSI, _HID)
Name(_CID, "PNP0CA1")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 0)
Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency
Name(_DEP, Package(0x1)
{
\_SB_.PEP0
})
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x0A600000, 0x000FFFFF)
})
// Dynamically enumerated device (host mode stack) on logical USB bus
Device(USB0)
{
Name(_ADR, 0)
Name(_S0W, 3) // Enable power management for SDM850 BU
// _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
// derive a unique "Connector ID". The other fields are not really important.
Name(_PLD, Package()
{
Buffer()
{
0x82, // Revision 2, ignore color.
0x00,0x00,0x00, // Color (ignored).
0x00,0x00,0x00,0x00, // Width and height.
0x69, // User visible; Back panel; VerticalPos:Center.
0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1.
0x00,0x00,0x00,0x00, // Not ejectable.
0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
}
})
// _UPC as defined in the ACPI spec.
Name(_UPC, Package()
{
0x01, // Port is connectable.
0x09, // Connector type: Type C connector - USB2 and SS with switch.
0x00000000, // Reserved0 - must be zero.
0x00000000 // Reserved1 - must be zero.
})
Name(_CRS, ResourceTemplate() {
// usb30_ctrl_irq[0]
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5}
// Qusb2Phy_intr
Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x17A}
// qmp_usb3_lfps_rxterm_irq
Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x206}
// eud_p0_dmse_int_mx - Rising Edge
Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x208}
// eud_p0_dpse_int_mx - Rising Edge
Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x209}
})
Method(_STA)
{
Return (0xf)
}
//Method to set DPDM Polarity for Pep Driver
Method(DPM0, 0x1, NotSerialized) {
// ARG 0 <20> DPDM polarity
Store(Arg0, \_SB.DPP0) //DPDM Polarity
Notify(\_SB.PEP0, 0xA0)
}
// Returns CC Out
Method(CCVL) {
// Return CC OUT
Return(\_SB.CCST)
}
//Returns High Speed Enumeration Flag
Method(HSEN) {
// Return High Speed Enumeration Flag
Return(\_SB.HSFL)
}
/* HS enumeration fix
//HSEI: High Speed pullup gpio
Name (HSEI, ResourceTemplate ()
{
GpioIo (Exclusive,PullNone,0,0, ,"\\_SB.GIO0", ,) {8}
})
//define 1 byte long operation region HLEN w/ base address == 0 under GPIO0 devnode namespace
Scope(\_SB.GIO0) {
OperationRegion(HLEN, GeneralPurposeIO, 0, 1) // Note: Region is less than 8 pins long
}
//now connect HLEN field in op region w/ HSEI resource
Field(\_SB.GIO0.HLEN, ByteAcc, NoLock, Preserve)
{
//Connect field to HSEI physical object
Connection (\_SB.URS0.USB0.HSEI), // Following fields will be accessed atomically
MOD1, 1 //MOD1 - variable name, 1 == 1bit wide
}
*/
// Device Specific Method takes 4 args:
// Arg0 : Buffer containing a UUID [16 bytes]
// Arg1 : Integer containing the Revision ID
// Arg2 : Integer containing the Function Index
// Arg3 : Empty Package (Not used)
Method (_DSM, 0x4, NotSerialized)
{
// UUID selector
switch(ToBuffer(Arg0)) {
// UFX interface identifier
case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {0,2,3,4} supported
case(0) { Return(Buffer(){0x1D}); Break; }
// Function 0 only supported for invalid revision
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function 2: Port type identification
// 0x00 <20> Regular USB
// 0x01 <20> HSIC
// 0x02 <20> SSIC
// 0x03 <20> 0xff reserved
case(2) { Return(0x0); Break; }
// Function 3: Query Controller Capabilities
// bit 0 represents the support for software assisted USB endpoint offloading feature
// 1 - Offloading endpoint supported
case(3) { Return(0x1); Break; }
// Function 4: Interrupter Number
case(4) { Return(0x2); Break; }
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {CE2EE385-00E6-48CB-9F05-2EDB927C4899}
default { Return (Buffer(){0x00}); Break; }
} // UUID
} // _DSM
//
// The following values of PHY will be configured if OEMs do not
// overwrite the values.
//
// For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
// For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
// and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
//
// AccessMethod:
// 0 - DirectAccess: The register address is accessed directly from the mapped memory.
//
Method(PHYC, 0x0, NotSerialized) {
Name (CFG0, Package()
{
// AccessMethod, REG ADDR, Value
// -------------------------------
//Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
//Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
//Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
})
Return (CFG0)
}
/*
Device(RHUB)
{
Name(_ADR, 0) // Value zero reserved for Root Hub
// Device Specific Method takes 4 args:
// Arg0 : Buffer containing a UUID [16 bytes]
// Arg1 : Integer containing the Revision ID
// Arg2 : Integer containing the Function Index
// Arg3 : Empty Package (Not used)
Method (_DSM, 0x4, NotSerialized)
{
// UUID selector
switch(ToBuffer(Arg0)) {
// HS enumeration fix
case(ToUUID("A9A82A56-95A1-4B4A-B014-3BE47DF1B7D5"))
{
// Version selector
switch(ToInteger(Arg1))
{
case(1) //DSM_SDM845_HS_RH_PORT_RESET_REVISION_1
{
switch(ToInteger(Arg2)) //DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_
{
//DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_PRE_RESET_ON - set GPIO high
case(1)
{
Store (0x01, \_SB.URS0.USB0.MOD1)
Return (Buffer(){0x01}) //return success
}
//DSM_SDM845_HS_RH_PORT_RESET_FUNCTION_POST_RESET_OFF - set GPIO low
case(0)
{
Store (0x00, \_SB.URS0.USB0.MOD1)
Return (Buffer(){0x01}) //return success
}
default { Return (Buffer(){0x00})}
}
}
default { Return (Buffer(){0x00}) }
}
}//end (A9A82A56-95A1-4B4A-B014-3BE47DF1B7D5)
default { Return (Buffer(){0x00}); Break; }
} // UUID
} // _DSM
} // Root Hub
*/
} // USB0
// Dynamically enumerated device (peripheral mode stack) on logical USB bus
Device(UFN0)
{
Name(_ADR, 1)
Name(_S0W, 3) // Enable power management for Napali BU
// _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
// derive a unique "Connector ID". The other fields are not really important.
Name(_PLD, Package()
{
Buffer()
{
0x82, // Revision 2, ignore color.
0x00,0x00,0x00, // Color (ignored).
0x00,0x00,0x00,0x00, // Width and height.
0x69, // User visible; Back panel; VerticalPos:Center.
0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1.
0x00,0x00,0x00,0x00, // Not ejectable.
0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
}
})
// _UPC as defined in the ACPI spec.
Name(_UPC, Package()
{
0x01, // Port is connectable.
0x09, // Connector type: Type C connector - USB2 and SS with switch.
0x00000000, // Reserved0 - must be zero.
0x00000000 // Reserved1 - must be zero.
})
Name(_CRS, ResourceTemplate() {
// usb30_ctrl_irq[0]
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xA5}
//usb30_power_event_irq
Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA2}
})
// Returns CC Out
Method(CCVL) {
// Return CC OUT
Return(\_SB.CCST)
}
// Device Specific Method takes 4 args:
// Arg0 : Buffer containing a UUID [16 bytes]
// Arg1 : Integer containing the Revision ID
// Arg2 : Integer containing the Function Index
// Arg3 : Package that contains function-specific arguments
Method (_DSM, 0x4, NotSerialized)
{
// UUID selector
switch(ToBuffer(Arg0)) {
// UFX interface identifier
case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {1} supported
case(0) { Return(Buffer(){0x03}); Break; }
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function 1: Return number of supported USB PHYSICAL endpoints
// Synopsys core configured to support 16 IN/16 OUT EPs, including EP0
case(1) { Return(32); Break; }
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2}
// QCOM specific interface identifier
case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {1} supported
case(0) { Return(Buffer(){0x03}); Break; }
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function 1: Return device capabilities bitmap
// Bit Description
// --- -------------------------------
// 0 Superspeed Gen1 supported
// 1 PMIC VBUS detection supported
// 2 USB PHY interrupt supported
// 3 Type-C supported
// 4 Delay USB initialization
// 5 HW based charger detection
case(1) { Return(0x39); Break; }
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {18DE299F-9476-4FC9-B43B-8AEB713ED751}
default { Return (Buffer(){0x00}); Break; }
} // UUID
} // _DSM
//
// The following values of PHY will be configured if OEMs do not
// overwrite the values.
//
// For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
// For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
// and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
//
// AccessMethod:
// 0 - DirectAccess: The register address is accessed directly from the mapped memory.
//
Method(PHYC, 0x0, NotSerialized) {
Name (CFG0, Package()
{
// AccessMethod, REG ADDR, Value
// -------------------------------
//Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
//Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
//Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
})
Return (CFG0)
}
} // UFN0
} // URS0
// HPD Notification Event in Display Driver
// HPD_STATUS_LOW_NOTIFY_EVENT - 0x92
// HPD_STATUS_HIGH_NOTIFY_EVENT - 0x93
// All other valus are invalid
Name(HPDB, 0x00000000)
// DP Pin Assignment
// TYPEC_DISPLAYPORT_PINASSIGNMENTINVALID = 0x0
// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTA = 0x01
// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTB = 0x02
// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTC = 0x03
// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTD = 0x04
// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTE = 0x05
// TYPEC_DISPLAYPORT_DFPDPINASSIGNMENTF = 0x06
// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTA = 0x07
// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTB = 0x08
// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTC = 0x09
// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTD = 0x0A
// TYPEC_DISPLAYPORT_UFPDPINASSIGNMENTE = 0x0B
Name(PINA, 0x00000000)
// Holds the CC OUT Status
// 0 -> CC1
// 1 -> CC2
// 2 -> CC Open
Name(CCST, Buffer(){0x02})
// Holds the HS Only enumeration Flag for display alternate mode
// 0 -> Super Speed Controller Enumeration support
// 1 -> High Speed Controller Enumeration support
// 2 -> Invalid
Name(HSFL, Buffer(){0x00})
// USB Capabilities bitmap
// Indicates the platform's USB capabilities, extend as required.
// Bit Description
// --- ---------------------------------------------------
// 0 Super Speed Gen1 supported (Synopsys IP)
// 1 PMIC VBUS detection supported
// 2 USB PHY interrupt supported (seperate from ULPI)
// 3 TypeC supported
Name(USBC, Buffer(){0x0B})
//
// USB Type-C/PD Switch
//
Device(UCP0)
{
Name(_HID, "QCOM02D0") // QCOM24D3
Name(_DEP, Package(0x3)
{
\_SB_.PEP0,
\_SB_.PTCC,
\_SB_.URS0
})
Device(CON0)
{
// These devices are not meant to be enumerated by ACPI, hence you should not assign
// HWIDs to them. Instead, use _ADR to assign unique addresses to them.
// The addresses are required to be a 0-based index of the connector. First connector
// should have "0", second one "1", etc.
Name(_ADR, 0x00000000)
// _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
// derive a unique "Connector ID". The other fields are not really important.
Name(_PLD, Package()
{
Buffer()
{
0x82, // Revision 2, ignore color.
0x00,0x00,0x00, // Color (ignored).
0x00,0x00,0x00,0x00, // Width and height.
0x69, // User visible; Back panel; VerticalPos:Center.
0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
0x80,0x00, // Group Token:0; Group Position:1; So Connector ID is 1.
0x00,0x00,0x00,0x00, // Not ejectable.
0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
}
})
// _UPC as defined in the ACPI spec.
Name(_UPC, Package()
{
0x01, // Port is connectable.
0x09, // Connector type: Type C connector - USB2 and SS with switch.
0x00000000, // Reserved0 - must be zero.
0x00000000 // Reserved1 - must be zero.
})
Name(_DSD, Package()
{
// The UUID for Type-C connector capabilities.
ToUUID("6b856e62-40f4-4688-bd46-5e888a2260de"),
// The data structure which contains the connector capabilities. Each package
// element contains two elements: the capability type ID, and the capability data
// (which depends on the capability type). Note that any information defined here
// will override similar information described by the driver itself. For example, if
// the driver claims the port controller is DRP-capable, but ACPI says it is UFP-only
// ACPI will take precedence.
Package()
{
Package() {1, 4}, // Supported operating modes (DRP).
Package() {2, 3}, // Supported Type-C sourcing capabilities (DefaultUSB & 1500mA).
Package() {3, 0}, // Audio accessory capable (False).
Package() {4, 1}, // Is PD supported (True).
Package() {5, 3}, // Supported power roles (Sink and Source).
Package()
{
6, // Capability type ID of PD Source Capabilities.
Package()
{
0x00019096 // Source PDO #0: Fixed:5V, 1.5A. No need to describe fixed bits.
}
},
Package()
{
7, // Capability type ID of PD Sink Capabilities.
Package ()
{
0x0001912C, // Sink PDO #0: Fixed:5V, 3.0A. No need to describe fixed bits.
0x0002D0C8, // Sink PDO #1: Fixed:9V, 2.0A. No need to describe fixed bits.
0x0003C096, // Sink PDO #2: Fixed:12V, 1.5A. No need to describe fixed bits.
}
},
Package()
{
8, // Capability type ID of supported PD Alternate Modes.
Package()
{
0xFF01, 0x3C86 // DFP_D capable (B0:1); DFP v1.3 signalling (B2:5); DP on Type-C plug (B6);
// usb r2.0 signalling not required (B7); Pin Assignment Supported - C,D,E,F (B8:15)
}
},
Package()
{
9, // Add Delay in loading of host stack
1
},
Package() // Hardware CC debounce is supported
{
0xA,
1
}
}
})
} // Device(CON0)
// Device Specific Method takes 4 args:
// Arg0 : Buffer containing a UUID [16 bytes]
// Arg1 : Integer containing the Revision ID
// Arg2 : Integer containing the Function Index
// Arg3 : Package that contains function-specific arguments
Method (_DSM, 0x4, NotSerialized)
{
// UUID selector
switch(ToBuffer(Arg0)) {
// QCOM specific interface identifier
case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {0,1} supported
case(0) { Return(Buffer(){0x01}); Break; } // TypeC support only, No PD
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function1: Return Capabilities Data Objects
case(1) {
switch(ToInteger(Arg3)) {
// Source Power PDO
case (0) { Return(Package(){0x36019050}); Break; }
// Sink Power PDO
case (1) { Return(Package(){0x3601912C}); Break; }
//default
default { Return (Package(){0x00}); Break; }
}
}
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {18DE299F-9476-4FC9-B43B-8AEB713ED751}
default { Return (Buffer(){0x00}); Break; }
} // UUID
} // _DSM
// Method for updating the CC Out status and HS Mode Flag
// Arg 0 - CC Out value (CC1/CC2/CC Open)
// Arg 1 - HS Mode Flag (SS/HS/Invalid)
Method(CCOT, 0x2, NotSerialized) {
// ARG 0 - CC_OUT
Store(Arg0, \_SB.CCST)
Store(Arg1, \_SB.HSFL)
}
// Method for reading CC Out Value from Type-C client driver
// Only for sanity testing
Method(CCVL) {
// Return CC OUT
Return(\_SB.CCST)
}
Method(HPDS, 0x0, NotSerialized) {
// Notify event ID - 0x92 to GFX driver on a hot plug-in event
Notify(\_SB.GPU0, 0x94)
}
Method(HPDF, 0x2, NotSerialized) {
// ARG 0 - HPD Status
Store(Arg0, \_SB.HPDB)
// Arg 1 - Pin Assignment
Store(Arg1, \_SB.PINA)
// Invoke Display Driver HPD event
Notify(\_SB.GPU0, \_SB.HPDB)
}
// Method for reading CC Out Value from Type-C client driver
// Only for sanity testing
Method(HPDV) {
// Return HPD
Return(\_SB.HPDB)
}
// Method for reading HPD and Pin Assignment values from Type-C client driver
// Only for sanity testing
Method(PINV) {
// Return Pin Assignment
Return(\_SB.PINA)
}
} // UCP0
//Dummy device to allow KDNET on 2ndary port debugger registration
Device (USB1)
{
Name (_DEP, Package(0x1)
{
\_SB_.PEP0
})
Name (_HID, "QCOM02BA") // QCOM02BA
Name (_UID, 1)
//set device status as not present, disabled, not shown in UI, not functioning properly
Name(STVL, 0x0)
Method (_STA) {
Return (STVL) // return the current device status
}
} // USB1
//
// USB Type-C Audio Driver
//
Device (USBA)
{
Name (_DEP, Package(0x1)
{
\_SB_.IMM0
})
Name (_HID, "QCOM0300")
Alias(\_SB.PSUB, _SUB)
}
Name(DPP1, Buffer(){0x0})
//URS1 specific
/*
//Holds the DPDM Polarity
//USB_DPDM_INVALID_INVALID = 0
//USB_DPDM_INVALID_FALLING = 1
//USB_DPDM_INVALID_RISING = 2
//USB_DPDM_FALLING_INVALID = 3
//USB_DPDM_RISING_INVALID = 4
//USB_DPDM_FALLING_FALLING = 5
//USB_DPDM_FALLING_RISING = 6
//USB_DPDM_RISING_FALLING = 7
//USB_DPDM_RISING_RISING = 8
Name(DPP1, Buffer(){0x0})
//USB Role Switch For Secondary Port
Device(URS1)
{
Name(_HID, "QCOM0304")
Name(_CID, "PNP0CA1")
Alias(\_SB.PSUB, _SUB)
Name (_UID, 1)
Name(_CCA, Zero) // Cache-incoherent bus-master, Hardware does not manage cache coherency
Name(_DEP, Package(0x1)
{
\_SB_.PEP0
})
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0x0A800000, 0x000FFFFF)
//USBID pin Interrupt [USB_ID]
GpioInt(Edge, ActiveBoth, Exclusive, PullUp, 0, "\\_SB.PM01",,,,) {488}
})
// Dynamically enumerated device (host mode stack) on logical USB bus
Device(USB1)
{
Name(_ADR, 0)
Name(_S0W, 3) // Enable power management
// _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
// derive a unique "Connector ID". The other fields are not really important.
Name(_PLD, Package()
{
Buffer()
{
0x82, // Revision 2, ignore color.
0x00,0x00,0x00, // Color (ignored).
0x00,0x00,0x00,0x00, // Width and height.
0x69, // User visible; Back panel; VerticalPos:Center.
0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
0x80,0x01, // Group Token:0; Group Position:1; So Connector ID is 1.
0x00,0x00,0x00,0x00, // Not ejectable.
0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
}
})
// _UPC as defined in the ACPI spec.
Name(_UPC, Package()
{
0x01, // Port is connectable.
0x06, // Connector type: uAB
0x00000000, // Reserved0 - must be zero.
0x00000000 // Reserved1 - must be zero.
})
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
//usb30_sec_ctrl_irq[0]
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA}
})
Store(RBUF, Local0)
ConcatenateResTemplate(Local0, ResourceTemplate()
{
//Qusb2Phy_sec_intr
Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x17B}
// qmp_usb3_lfps_rxterm_irq
Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0x207}
// eud_p1_dmse_int_mx - Rising Edge
Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20A}
// eud_p1_dpse_int_mx - Rising Edge
Interrupt(ResourceConsumer, Edge, ActiveHigh, SharedAndWake, , , ) {0x20B}
}, Local1)
Return(Local1)
}
Method(_STA)
{
Return (0xf)
}
//Method to set DPDM Polarity for Pep Driver
Method(DPM1, 0x1, NotSerialized) {
// ARG 0 <20> DPDM polarity
Store(Arg0, \_SB.DPP1) //DPDM Polarity
Notify(\_SB.PEP0, 0xA1)
}
// Device Specific Method takes 4 args:
// Arg0 : Buffer containing a UUID [16 bytes]
// Arg1 : Integer containing the Revision ID
// Arg2 : Integer containing the Function Index
// Arg3 : Empty Package (Not used)
Method (_DSM, 0x4, NotSerialized)
{
// UUID selector
switch(ToBuffer(Arg0)) {
// UFX interface identifier
case(ToUUID("CE2EE385-00E6-48CB-9F05-2EDB927C4899")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {0,2,3} supported
case(0) { Return(Buffer(){0x0D}); Break; }
// Function 0 only supported for invalid revision
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function 2: Port type identification
// 0x00 <20> Regular USB
// 0x01 <20> HSIC
// 0x02 <20> SSIC
// 0x03 <20> 0xff reserved
case(2) { Return(0x0); Break; }
// Function 3: Query Controller Capabilities
// bit 0 represents the support for software assisted USB endpoint offloading feature
// 1 - Offloading endpoint supported
case(3) { Return(0x1); Break; }
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {CE2EE385-00E6-48CB-9F05-2EDB927C4899}
default { Return (Buffer(){0x00}); Break; }
} // UUID
} // _DSM
//
// The following values of PHY will be configured if OEMs do not
// overwrite the values.
//
// For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
// For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
// and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
//
// AccessMethod:
// 0 - DirectAccess: The register address is accessed directly from the mapped memory.
//
Method(PHYC, 0x0, NotSerialized) {
Name (CFG0, Package()
{
// AccessMethod, REG ADDR, Value
// -------------------------------
//Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
//Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
//Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
})
Return (CFG0)
}
} // USB1
// Dynamically enumerated device (peripheral mode stack) on logical USB bus
Device(UFN1)
{
Name(_ADR, 1)
Name(_S0W, 3) // Enable power management
// _PLD as defined in the ACPI spec. The GroupToken and GroupPosition are used to
// derive a unique "Connector ID". The other fields are not really important.
Name(_PLD, Package()
{
Buffer()
{
0x82, // Revision 2, ignore color.
0x00,0x00,0x00, // Color (ignored).
0x00,0x00,0x00,0x00, // Width and height.
0x69, // User visible; Back panel; VerticalPos:Center.
0x0c, // HorizontalPos:0; Shape:Vertical Rectangle; GroupOrientation:0.
0x80,0x01, // Group Token:0; Group Position:1; So Connector ID is 1.
0x00,0x00,0x00,0x00, // Not ejectable.
0xFF,0xFF,0xFF,0xFF // Vert. and horiz. offsets not supplied.
}
})
// _UPC as defined in the ACPI spec.
Name(_UPC, Package()
{
0x01, // Port is connectable.
0x09, // Connector type: Type C connector - USB2 and SS with switch.
0x00000000, // Reserved0 - must be zero.
0x00000000 // Reserved1 - must be zero.
})
Name(_CRS, ResourceTemplate() {
// usb30_sec_ctrl_irq[0]
Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {0xAA}
//usb30_sec_power_event_irq
Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake, , , ) {0xA7}
//Attach,Detach Interrupt [USB2_VUSB_DET]
GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0, "\\_SB.PM01",,,,RawDataBuffer() {0x00, 0x00, 0x00, 0x00}) {487}
})
// Device Specific Method takes 4 args:
// Arg0 : Buffer containing a UUID [16 bytes]
// Arg1 : Integer containing the Revision ID
// Arg2 : Integer containing the Function Index
// Arg3 : Package that contains function-specific arguments
Method (_DSM, 0x4, NotSerialized)
{
// UUID selector
switch(ToBuffer(Arg0)) {
// UFX interface identifier
case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {1} supported
case(0) { Return(Buffer(){0x03}); Break; }
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function 1: Return number of supported USB PHYSICAL endpoints
// Synopsys core configured to support 16 IN/16 OUT EPs, including EP0
case(1) { Return(32); Break; }
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {FE56CFEB-49D5-4378-A8A2-2978DBE54AD2}
// QCOM specific interface identifier
case(ToUUID("18DE299F-9476-4FC9-B43B-8AEB713ED751")) {
// Function selector
switch(ToInteger(Arg2)) {
// Function 0: Return supported functions, based on revision
case(0) {
// Version selector
switch(ToInteger(Arg1)) {
// Revision0: functions {1} supported
case(0) { Return(Buffer(){0x03}); Break; }
default { Return(Buffer(){0x01}); Break; }
}
// default
Return (Buffer(){0x00}); Break;
}
// Function 1: Return device capabilities bitmap
// Bit Description
// --- -------------------------------
// 0 Superspeed Gen1 supported
// 1 PMIC VBUS detection supported
// 2 USB PHY interrupt supported
// 3 Type-C supported
// 4 Delay USB initialization
// 5 HW based charger detection
case(1) { Return(0x33); Break; }
default { Return (Buffer(){0x00}); Break; }
} // Function
} // {18DE299F-9476-4FC9-B43B-8AEB713ED751}
default { Return (Buffer(){0x00}); Break; }
} // UUID
} // _DSM
//
// The following values of PHY will be configured if OEMs do not
// overwrite the values.
//
// For SNPS core, PARAMETER_OVERRIDE_X is used to configure HS PHY.
// For SS PHY, PERIPH_SS_USB3PHY_QSERDES_TX_TX_DRV_LVL is used to tune swing
// and PERIPH_SS_USB3PHY_QSERDES_TX_TX_EMP_POST1_LVL for de_emphasis.
//
// AccessMethod:
// 0 - DirectAccess: The register address is accessed directly from the mapped memory.
//
Method(PHYC, 0x0, NotSerialized) {
Name (CFG0, Package()
{
// AccessMethod, REG ADDR, Value
// -------------------------------
//Package() {0x0, 0x06AF8814, 0xD191A4}, // DirectAccess, HS PARAMETER_OVERRIDE_X_ADDR
//Package() {0x0, 0x06A3820C, 0x11}, // DirectAccess, SS QMP PHY TX Swing
//Package() {0x0, 0x06A38208, 0x21}, // DirectAccess, SS QMP PHY TX DE-Emphasis
})
Return (CFG0)
}
} // UFN1
} // URS1
*/

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//
// iHelium WLAN
//
Device (QWLN)
{
Name(_ADR, 0)
Name(_DEP, Package(2)
{
\_SB.PEP0,
\_SB.MMU0
})
Name(_PRW, Package() {0,0}) // wakeable from S0
Name(_S0W, 2) // S0 should put device in D2 for wake
Name(_S4W, 2) // all other Sx (just in case) should also wake from D2
Name(_PRR, Package(0x1) { \_SB.AMSS.QWLN.WRST }) // Power resource reference for device reset and recovery.
Method (_CRS, 0x0, NotSerialized)
{
Name (RBUF, ResourceTemplate ()
{
// Shared memory
Memory32Fixed (ReadWrite, 0x18800000, 0x800000) //CE registers
Memory32Fixed (ReadWrite, 0xC250000, 0x10) //WCSSAON registers
Memory32Fixed (ReadWrite, 0x8C400000, 0x100000) //MSA image address
// CE interrupts
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {446} //CE0 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {447} //CE1 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake, , , ) {448} //CE2 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {449} //CE3 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {450} //CE4 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {451} //CE5 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {452} //CE6 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {453} //CE7 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {454} //CE8 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {455} //CE9 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {456} //CE10 interrupt
Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive , , , ) {457} //CE11 interrupt
})
Return (RBUF)
}
// wlan msa memory size
Method (WMSA)
{
Return(Package ()
{
0x100000
})
}
PowerResource(WRST, 0x5, 0x0)
{
//
// Dummy _ON, _OFF, and _STA methods. All power resources must have these
// three defined.
//
Method(_ON, 0x0, NotSerialized)
{
}
Method(_OFF, 0x0, NotSerialized)
{
}
Method(_STA, 0x0, NotSerialized)
{
Return(0xf)
}
Method(_RST, 0x0, NotSerialized)
{
}
}
}
//agent driver of wlan for supporting windows thermal framework
Scope(\_SB)
{
Device (COEX)
{
Name (_HID, "QCOM0295")
Alias(\_SB.PSUB, _SUB)
}
}

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