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dbcc357166
After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
563 lines
19 KiB
C
563 lines
19 KiB
C
/*----------------------------------------------------------------------------+
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| This source code is dual-licensed. You may use it under the terms of the
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| GNU General Public License version 2, or under the license below.
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| File Name: enetemac.h
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| Function: Header file for the EMAC3 macro on the 405GP.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 29-Apr-99 Created MKW
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+----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------+
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| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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| ported to handle 440GP and 440GX multiple EMACs
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+----------------------------------------------------------------------------*/
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#ifndef _PPC4XX_ENET_H_
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#define _PPC4XX_ENET_H_
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#include <net.h>
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#include "405_mal.h"
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/*-----------------------------------------------------------------------------+
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| General enternet defines. 802 frames are not supported.
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+-----------------------------------------------------------------------------*/
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#define ENET_ADDR_LENGTH 6
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#define ENET_ARPTYPE 0x806
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#define ARP_REQUEST 1
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#define ARP_REPLY 2
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#define ENET_IPTYPE 0x800
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#define ARP_CACHE_SIZE 5
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#define NUM_TX_BUFF 1
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#define NUM_RX_BUFF PKTBUFSRX
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struct enet_frame {
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unsigned char dest_addr[ENET_ADDR_LENGTH];
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unsigned char source_addr[ENET_ADDR_LENGTH];
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unsigned short type;
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unsigned char enet_data[1];
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};
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struct arp_entry {
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unsigned long inet_address;
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unsigned char mac_address[ENET_ADDR_LENGTH];
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unsigned long valid;
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unsigned long sec;
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unsigned long nsec;
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};
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/* Statistic Areas */
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#define MAX_ERR_LOG 10
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typedef struct emac_stats_st{ /* Statistic Block */
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int data_len_err;
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int rx_frames;
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int rx;
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int rx_prot_err;
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int int_err;
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int pkts_tx;
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int pkts_rx;
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int pkts_handled;
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short tx_err_log[MAX_ERR_LOG];
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short rx_err_log[MAX_ERR_LOG];
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} EMAC_STATS_ST, *EMAC_STATS_PST;
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/* Structure containing variables used by the shared code (4xx_enet.c) */
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typedef struct emac_4xx_hw_st {
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uint32_t hw_addr; /* EMAC offset */
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uint32_t tah_addr; /* TAH offset */
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uint32_t phy_id;
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uint32_t phy_addr;
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uint32_t original_fc;
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uint32_t txcw;
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uint32_t autoneg_failed;
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uint32_t emac_ier;
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volatile mal_desc_t *tx;
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volatile mal_desc_t *rx;
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u32 tx_phys;
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u32 rx_phys;
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bd_t *bis; /* for eth_init upon mal error */
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mal_desc_t *alloc_tx_buf;
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mal_desc_t *alloc_rx_buf;
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char *txbuf_ptr;
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uint16_t devnum;
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int get_link_status;
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int tbi_compatibility_en;
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int tbi_compatibility_on;
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int fc_send_xon;
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int report_tx_early;
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int first_init;
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int tx_err_index;
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int rx_err_index;
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int rx_slot; /* MAL Receive Slot */
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int rx_i_index; /* Receive Interrupt Queue Index */
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int rx_u_index; /* Receive User Queue Index */
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int tx_slot; /* MAL Transmit Slot */
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int tx_i_index; /* Transmit Interrupt Queue Index */
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int tx_u_index; /* Transmit User Queue Index */
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int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
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int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
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int is_receiving; /* sync with eth interrupt */
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int print_speed; /* print speed message upon start */
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EMAC_STATS_ST stats;
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} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
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#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
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#define EMAC_NUM_DEV 4
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#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
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defined(CONFIG_NET_MULTI) && \
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!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
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#define EMAC_NUM_DEV 2
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#else
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#define EMAC_NUM_DEV 1
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#endif
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#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
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#define EMAC_STACR_OC_MASK (0x00008000)
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#else
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#define EMAC_STACR_OC_MASK (0x00000000)
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#endif
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#define SDR0_PFC1_EM_1000 (0x00200000)
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#endif
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/*
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* XMII bridge configurations for those systems (e.g. 405EX(r)) that do
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* not have a pin function control (PFC) register to otherwise determine
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* the bridge configuration.
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*/
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#define EMAC_PHY_MODE_NONE 0
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#define EMAC_PHY_MODE_NONE_RGMII 1
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#define EMAC_PHY_MODE_RGMII_NONE 2
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#define EMAC_PHY_MODE_RGMII_RGMII 3
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#define EMAC_PHY_MODE_NONE_GMII 4
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#define EMAC_PHY_MODE_GMII_NONE 5
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#define EMAC_PHY_MODE_NONE_MII 6
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#define EMAC_PHY_MODE_MII_NONE 7
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/* ZMII Bridge Register addresses */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
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#else
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#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
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#endif
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#define ZMII0_FER (ZMII0_BASE)
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#define ZMII0_SSR (ZMII0_BASE + 4)
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#define ZMII0_SMIISR (ZMII0_BASE + 8)
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/* ZMII FER Register Bit Definitions */
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#define ZMII_FER_DIS (0x0)
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#define ZMII_FER_MDI (0x8)
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#define ZMII_FER_SMII (0x4)
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#define ZMII_FER_RMII (0x2)
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#define ZMII_FER_MII (0x1)
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#define ZMII_FER_RSVD11 (0x00200000)
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#define ZMII_FER_RSVD10 (0x00100000)
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#define ZMII_FER_RSVD14_31 (0x0003FFFF)
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#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
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/* ZMII Speed Selection Register Bit Definitions */
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#define ZMII0_SSR_SCI (0x4)
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#define ZMII0_SSR_FSS (0x2)
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#define ZMII0_SSR_SP (0x1)
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#define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
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#define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
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/* ZMII SMII Status Register Bit Definitions */
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#define ZMII0_SMIISR_E1 (0x80)
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#define ZMII0_SMIISR_EC (0x40)
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#define ZMII0_SMIISR_EN (0x20)
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#define ZMII0_SMIISR_EJ (0x10)
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#define ZMII0_SMIISR_EL (0x08)
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#define ZMII0_SMIISR_ED (0x04)
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#define ZMII0_SMIISR_ES (0x02)
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#define ZMII0_SMIISR_EF (0x01)
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#define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
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/* RGMII Register Addresses */
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
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#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
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#elif defined(CONFIG_405EX)
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#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
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#else
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#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
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#endif
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#define RGMII_FER (RGMII_BASE + 0x00)
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#define RGMII_SSR (RGMII_BASE + 0x04)
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#if defined(CONFIG_460GT)
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#define RGMII1_BASE_OFFSET 0x100
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#endif
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/* RGMII Function Enable (FER) Register Bit Definitions */
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#define RGMII_FER_DIS (0x00)
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#define RGMII_FER_RTBI (0x04)
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#define RGMII_FER_RGMII (0x05)
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#define RGMII_FER_TBI (0x06)
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#define RGMII_FER_GMII (0x07)
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#define RGMII_FER_MII (RGMII_FER_GMII)
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#define RGMII_FER_V(__x) ((__x - 2) * 4)
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#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
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/* RGMII Speed Selection Register Bit Definitions */
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#define RGMII_SSR_SP_10MBPS (0x00)
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#define RGMII_SSR_SP_100MBPS (0x02)
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#define RGMII_SSR_SP_1000MBPS (0x04)
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX)
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#define RGMII_SSR_V(__x) ((__x) * 8)
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#else
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#define RGMII_SSR_V(__x) ((__x -2) * 8)
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#endif
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/*---------------------------------------------------------------------------+
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| TCP/IP Acceleration Hardware (TAH) 440GX Only
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+---------------------------------------------------------------------------*/
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#if defined(CONFIG_440GX)
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#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
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#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
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#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
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#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
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#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
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#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
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#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
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#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
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#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
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#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
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/* TAH Revision */
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#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
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#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
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#define TAH_REV_RN_V (8)
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#define TAH_REV_BN_V (0)
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/* TAH Mode Register */
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#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
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#define TAH_MR_SR (0x40000000) /* Software reset */
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#define TAH_MR_ST (0x3F000000) /* Send Threshold */
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#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
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#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
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#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
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#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
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#define TAH_MR_ST_V (20)
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#define TAH_MR_TFS_V (17)
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#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
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#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
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#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
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#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
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#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
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/* TAH Segment Size Registers 0:5 */
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#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
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#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
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#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
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/* TAH Transmit Status Register */
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#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
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#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
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#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
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#define TAH_TSR_IPOP (0x10000000) /* IP option present */
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#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
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#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
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#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
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#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
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#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
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#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
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#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
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#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
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#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
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#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
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#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
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#endif /* CONFIG_440GX */
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/* Ethernet MAC Regsiter Addresses */
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#if defined(CONFIG_440)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
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#else
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#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
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#endif
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#else
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#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
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#define EMAC0_BASE 0xEF600900
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#else
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#define EMAC0_BASE 0xEF600800
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#endif
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#endif
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#if defined(CONFIG_440EPX)
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#define EMAC1_BASE 0xEF600F00
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#define EMAC1_MR1 (EMAC1_BASE + 0x04)
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#endif
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#define EMAC0_MR0 (EMAC0_BASE)
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#define EMAC0_MR1 (EMAC0_BASE + 0x04)
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#define EMAC0_TMR0 (EMAC0_BASE + 0x08)
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#define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
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#define EMAC0_RXM (EMAC0_BASE + 0x10)
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#define EMAC0_ISR (EMAC0_BASE + 0x14)
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#define EMAC0_IER (EMAC0_BASE + 0x18)
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#define EMAC0_IAH (EMAC0_BASE + 0x1c)
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#define EMAC0_IAL (EMAC0_BASE + 0x20)
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#define EMAC0_PTR (EMAC0_BASE + 0x2c)
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#define EMAC0_PAUSE_TIME_REG EMAC0_PTR
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#define EMAC0_IPGVR (EMAC0_BASE + 0x58)
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#define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
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#define EMAC0_STACR (EMAC0_BASE + 0x5c)
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#define EMAC0_TRTR (EMAC0_BASE + 0x60)
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#define EMAC0_RWMR (EMAC0_BASE + 0x64)
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#define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
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/* bit definitions */
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/* MODE REG 0 */
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#define EMAC_MR0_RXI (0x80000000)
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#define EMAC_MR0_TXI (0x40000000)
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#define EMAC_MR0_SRST (0x20000000)
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#define EMAC_MR0_TXE (0x10000000)
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#define EMAC_MR0_RXE (0x08000000)
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#define EMAC_MR0_WKE (0x04000000)
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/* on 440GX EMAC_MR1 has a different layout! */
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#if defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX)
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/* MODE Reg 1 */
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#define EMAC_MR1_FDE (0x80000000)
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#define EMAC_MR1_ILE (0x40000000)
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#define EMAC_MR1_VLE (0x20000000)
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#define EMAC_MR1_EIFC (0x10000000)
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#define EMAC_MR1_APP (0x08000000)
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#define EMAC_MR1_RSVD (0x06000000)
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#define EMAC_MR1_IST (0x01000000)
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#define EMAC_MR1_MF_1000GPCS (0x00C00000)
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#define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
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#define EMAC_MR1_MF_100MBPS (0x00400000)
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#define EMAC_MR1_RFS_MASK (0x00380000)
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#define EMAC_MR1_RFS_16K (0x00280000)
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#define EMAC_MR1_RFS_8K (0x00200000)
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#define EMAC_MR1_RFS_4K (0x00180000)
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#define EMAC_MR1_RFS_2K (0x00100000)
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#define EMAC_MR1_RFS_1K (0x00080000)
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#define EMAC_MR1_TX_FIFO_MASK (0x00070000)
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#define EMAC_MR1_TX_FIFO_16K (0x00050000)
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#define EMAC_MR1_TX_FIFO_8K (0x00040000)
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#define EMAC_MR1_TX_FIFO_4K (0x00030000)
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#define EMAC_MR1_TX_FIFO_2K (0x00020000)
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#define EMAC_MR1_TX_FIFO_1K (0x00010000)
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#define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
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#define EMAC_MR1_MWSW (0x00007000)
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#define EMAC_MR1_JUMBO_ENABLE (0x00000800)
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#define EMAC_MR1_IPPA (0x000007c0)
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#define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
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#define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
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#define EMAC_MR1_OBCI_GT100 (0x00000020)
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#define EMAC_MR1_OBCI_100 (0x00000018)
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#define EMAC_MR1_OBCI_83 (0x00000010)
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#define EMAC_MR1_OBCI_66 (0x00000008)
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#define EMAC_MR1_RSVD1 (0x00000007)
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#else /* defined(CONFIG_440GX) */
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/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
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#define EMAC_MR1_FDE 0x80000000
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#define EMAC_MR1_ILE 0x40000000
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#define EMAC_MR1_VLE 0x20000000
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#define EMAC_MR1_EIFC 0x10000000
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#define EMAC_MR1_APP 0x08000000
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#define EMAC_MR1_AEMI 0x02000000
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#define EMAC_MR1_IST 0x01000000
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#define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
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#define EMAC_MR1_MF_100MBPS 0x00400000
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#define EMAC_MR1_RFS_MASK 0x00300000
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#define EMAC_MR1_RFS_4K 0x00300000
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#define EMAC_MR1_RFS_2K 0x00200000
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#define EMAC_MR1_RFS_1K 0x00100000
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#define EMAC_MR1_RFS_512 0x00000000
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#define EMAC_MR1_TX_FIFO_MASK 0x000c0000
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#define EMAC_MR1_TX_FIFO_2K 0x00080000
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#define EMAC_MR1_TX_FIFO_1K 0x00040000
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#define EMAC_MR1_TX_FIFO_512 0x00000000
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#define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
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#define EMAC_MR1_TR0_MULTI 0x00008000
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#define EMAC_MR1_TR1_DEPEND 0x00004000
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#define EMAC_MR1_TR1_MULTI 0x00002000
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define EMAC_MR1_JUMBO_ENABLE 0x00001000
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#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
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#endif /* defined(CONFIG_440GX) */
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#define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
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#if defined(CONFIG_405EZ)
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/* 405EZ only supports 512 bytes fifos */
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#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
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#else
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/* Set receive fifo to 4k and tx fifo to 2k */
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#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
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#endif
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/* Transmit Mode Register 0 */
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#define EMAC_TMR0_GNP0 (0x80000000)
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#define EMAC_TMR0_GNP1 (0x40000000)
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#define EMAC_TMR0_GNPD (0x20000000)
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#define EMAC_TMR0_FC (0x10000000)
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/* Receive Mode Register */
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#define EMAC_RMR_SP (0x80000000)
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#define EMAC_RMR_SFCS (0x40000000)
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#define EMAC_RMR_ARRP (0x20000000)
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#define EMAC_RMR_ARP (0x10000000)
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#define EMAC_RMR_AROP (0x08000000)
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#define EMAC_RMR_ARPI (0x04000000)
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#define EMAC_RMR_PPP (0x02000000)
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#define EMAC_RMR_PME (0x01000000)
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#define EMAC_RMR_PMME (0x00800000)
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#define EMAC_RMR_IAE (0x00400000)
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#define EMAC_RMR_MIAE (0x00200000)
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#define EMAC_RMR_BAE (0x00100000)
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#define EMAC_RMR_MAE (0x00080000)
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/* Interrupt Status & enable Regs */
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#define EMAC_ISR_OVR (0x02000000)
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#define EMAC_ISR_PP (0x01000000)
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#define EMAC_ISR_BP (0x00800000)
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#define EMAC_ISR_RP (0x00400000)
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#define EMAC_ISR_SE (0x00200000)
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#define EMAC_ISR_SYE (0x00100000)
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#define EMAC_ISR_BFCS (0x00080000)
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#define EMAC_ISR_PTLE (0x00040000)
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#define EMAC_ISR_ORE (0x00020000)
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#define EMAC_ISR_IRE (0x00010000)
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#define EMAC_ISR_DBDM (0x00000200)
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#define EMAC_ISR_DB0 (0x00000100)
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#define EMAC_ISR_SE0 (0x00000080)
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#define EMAC_ISR_TE0 (0x00000040)
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#define EMAC_ISR_DB1 (0x00000020)
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#define EMAC_ISR_SE1 (0x00000010)
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#define EMAC_ISR_TE1 (0x00000008)
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#define EMAC_ISR_MOS (0x00000002)
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#define EMAC_ISR_MOF (0x00000001)
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/* STA CONTROL REG */
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#define EMAC_STACR_OC (0x00008000)
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#define EMAC_STACR_PHYE (0x00004000)
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#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
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#define EMAC_STACR_INDIRECT_MODE (0x00002000)
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#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
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#define EMAC_STACR_READ (0x00001000) /* $BUC */
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#define EMAC_STACR_OP_MASK (0x00001800)
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#define EMAC_STACR_MDIO_ADDR (0x00000000)
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#define EMAC_STACR_MDIO_WRITE (0x00000800)
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#define EMAC_STACR_MDIO_READ (0x00001800)
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#define EMAC_STACR_MDIO_READ_INC (0x00001000)
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#else
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#define EMAC_STACR_WRITE (0x00002000)
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#define EMAC_STACR_READ (0x00001000)
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#endif
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#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
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#define EMAC_STACR_CLK_66MHZ (0x00000400)
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#define EMAC_STACR_CLK_100MHZ (0x00000C00)
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/* Transmit Request Threshold Register */
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#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
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#define EMAC_TRTR_192 (0x10000000)
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#define EMAC_TRTR_128 (0x01000000)
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/* the follwing defines are for the MadMAL status and control registers. */
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/* For bits 0..5 look at the mal.h file */
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#define EMAC_TX_CTRL_GFCS (0x0200)
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#define EMAC_TX_CTRL_GP (0x0100)
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#define EMAC_TX_CTRL_ISA (0x0080)
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#define EMAC_TX_CTRL_RSA (0x0040)
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#define EMAC_TX_CTRL_IVT (0x0020)
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#define EMAC_TX_CTRL_RVT (0x0010)
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#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
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#define EMAC_TX_ST_BFCS (0x0200)
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#define EMAC_TX_ST_BPP (0x0100)
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#define EMAC_TX_ST_LCS (0x0080)
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#define EMAC_TX_ST_ED (0x0040)
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#define EMAC_TX_ST_EC (0x0020)
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#define EMAC_TX_ST_LC (0x0010)
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#define EMAC_TX_ST_MC (0x0008)
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#define EMAC_TX_ST_SC (0x0004)
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#define EMAC_TX_ST_UR (0x0002)
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#define EMAC_TX_ST_SQE (0x0001)
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#define EMAC_TX_ST_DEFAULT (0x03F3)
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/* madmal receive status / Control bits */
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#define EMAC_RX_ST_OE (0x0200)
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#define EMAC_RX_ST_PP (0x0100)
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#define EMAC_RX_ST_BP (0x0080)
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#define EMAC_RX_ST_RP (0x0040)
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#define EMAC_RX_ST_SE (0x0020)
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#define EMAC_RX_ST_AE (0x0010)
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#define EMAC_RX_ST_BFCS (0x0008)
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#define EMAC_RX_ST_PTL (0x0004)
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#define EMAC_RX_ST_ORE (0x0002)
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#define EMAC_RX_ST_IRE (0x0001)
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/* all the errors we care about */
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#define EMAC_RX_ERRORS (0x03FF)
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#endif /* _PPC4XX_ENET_H_ */
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