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132 lines
2.9 KiB
ArmAsm
132 lines
2.9 KiB
ArmAsm
/*
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* (C) Copyright 2008
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* Mark Jonas <mark.jonas@de.bosch.com>
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*
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* (C) Copyright 2007
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* board/mpr2/lowlevel_init.S
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/*
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* Set frequency multipliers and dividers in FRQCR.
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*/
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write16 WTCSR_A, WTCSR_D
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write16 WTCNT_A, WTCNT_D
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write16 FRQCR_A, FRQCR_D
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/*
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* Setup CS0 (Flash).
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*/
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write32 CS0BCR_A, CS0BCR_D
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write32 CS0WCR_A, CS0WCR_D
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/*
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* Setup CS3 (SDRAM).
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*/
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write32 CS3BCR_A, CS3BCR_D
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write32 CS3WCR_A, CS3WCR_D
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write32 SDCR_A, SDCR_D1
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write32 RTCSR_A, RTCSR_D
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write32 RTCNT_A, RTCNT_D
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write32 RTCOR_A, RTCOR_D
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write32 SDCR_A, SDCR_D2
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mov.l SDMR3_A, r1
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mov.l SDMR3_D, r0
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add r0, r1
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mov #0, r0
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mov.w r0, @r1
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rts
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nop
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.align 4
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/*
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* Configuration for MPR2 A.3 through A.7
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*/
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/*
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* PLL Settings
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*/
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FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
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WTCNT_D: .word 0x5A00 /* start counting at zero */
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WTCSR_D: .word 0xA507 /* divide by 4096 */
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.align 2
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/*
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* Spansion S29GL256N11 @ 48 MHz
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*/
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/* 1 idle cycle inserted, normal space, 16 bit */
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CS0BCR_D: .long 0x12490400
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/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
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CS0WCR_D: .long 0x00000340
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/*
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* Samsung K4S511632B-UL75 @ 48 MHz
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* Micron MT48LC32M16A2-75 @ 48 MHz
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*/
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/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
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CS3BCR_D: .long 0x10004400
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/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
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CS3WCR_D: .long 0x00000091
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/* no refresh, 13 rows, 10 cols, NO bank active mode */
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SDCR_D1: .long 0x00000012
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SDCR_D2: .long 0x00000812 /* refresh */
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RTCSR_D: .long 0xA55A0008 /* 1/4, once */
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RTCNT_D: .long 0xA55A005D /* count 93 */
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RTCOR_D: .long 0xa55a005d /* count 93 */
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/* mode register CL2, burst read and SINGLE WRITE */
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SDMR3_D: .long 0x440
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/*
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* Registers
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*/
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FRQCR_A: .long 0xA415FF80
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WTCNT_A: .long 0xA415FF84
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WTCSR_A: .long 0xA415FF86
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#define BSC_BASE 0xA4FD0000
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CS0BCR_A: .long BSC_BASE + 0x04
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CS3BCR_A: .long BSC_BASE + 0x0C
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CS0WCR_A: .long BSC_BASE + 0x24
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CS3WCR_A: .long BSC_BASE + 0x2C
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SDCR_A: .long BSC_BASE + 0x44
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RTCSR_A: .long BSC_BASE + 0x48
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RTCNT_A: .long BSC_BASE + 0x4C
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RTCOR_A: .long BSC_BASE + 0x50
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SDMR3_A: .long BSC_BASE + 0x5000
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