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https://github.com/u-boot/u-boot.git
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9ed303dfa9
This patch add base support for LX2162AQDS board. LX2162AQDS board supports LX2162A family SoCs. This patch add basic support of platform. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: hui.song <hui.song_1@nxp.com> Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Signed-off-by: Vikas Singh <vikas.singh@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
300 lines
9.1 KiB
C
300 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018-2020 NXP
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*/
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#ifndef __LX2_COMMON_H
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#define __LX2_COMMON_H
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#include <asm/arch/stream_id_lsch3.h>
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#include <asm/arch/config.h>
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#include <asm/arch/soc.h>
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_GICV3
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#define CONFIG_FSL_TZPC_BP147
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#define CONFIG_FSL_MEMAC
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_FLASH_BASE 0x20000000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* DDR */
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
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#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
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#define CONFIG_DDR_SPD
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS3 0x53
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#define SPD_EEPROM_ADDRESS4 0x54
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#define SPD_EEPROM_ADDRESS5 0x55
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#define SPD_EEPROM_ADDRESS6 0x56
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
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#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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/* SMP Definitinos */
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#define CPU_RELEASE_ADDR secondary_boot_addr
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/* Generic Timer Definitions */
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/*
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* This is not an accurate number. It is used in start.S. The frequency
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* will be udpated later when get_bus_freq(0) is available.
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*/
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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/* Serial Port */
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#define CONFIG_PL01X_SERIAL
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#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
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#define CONFIG_SYS_SERIAL0 0x21c0000
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#define CONFIG_SYS_SERIAL1 0x21d0000
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#define CONFIG_SYS_SERIAL2 0x21e0000
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#define CONFIG_SYS_SERIAL3 0x21f0000
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/*below might needs to be removed*/
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#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
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(void *)CONFIG_SYS_SERIAL1, \
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(void *)CONFIG_SYS_SERIAL2, \
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(void *)CONFIG_SYS_SERIAL3 }
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* MC firmware */
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#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
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#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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/* Define phy_reset function to boot the MC based on mcinitcmd.
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* This happens late enough to properly fixup u-boot env MAC addresses.
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*/
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#define CONFIG_RESET_PHY_R
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/*
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* Carve out a DDR region which will not be used by u-boot/Linux
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*
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* It will be used by MC and Debug Server. The MC region must be
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* 512MB aligned, so the min size to hide is 512MB.
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*/
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#ifdef CONFIG_FSL_MC_ENET
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#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
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#endif
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x8
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/* RTC */
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#define RTC
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* Qixis */
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#define CONFIG_FSL_QIXIS
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#define CONFIG_QIXIS_I2C_ACCESS
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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/* PCI */
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#ifdef CONFIG_PCI
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#define CONFIG_SYS_PCI_64BIT
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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/* SATA */
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#ifdef CONFIG_SCSI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
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#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#endif
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/* USB */
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#ifdef CONFIG_USB
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifndef CONFIG_TARGET_LX2162AQDS
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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#endif
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/* FlexSPI */
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#ifdef CONFIG_NXP_FSPI
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#define NXP_FSPI_FLASH_SIZE SZ_64M
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#define NXP_FSPI_FLASH_NUM 1
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#endif
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#ifndef __ASSEMBLY__
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unsigned long get_board_sys_clk(void);
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unsigned long get_board_ddr_clk(void);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* Initial environment variables */
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#define XSPI_MC_INIT_CMD \
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"sf probe 0:0 && " \
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"sf read 0x80640000 0x640000 0x80000 && " \
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"env exists secureboot && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000; " \
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"sf read 0x80a00000 0xa00000 0x300000 && " \
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"sf read 0x80e00000 0xe00000 0x100000; " \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define SD_MC_INIT_CMD \
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"mmc read 0x80a00000 0x5000 0x1200;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"env exists secureboot && " \
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"mmc read 0x80640000 0x3200 0x20 && " \
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"mmc read 0x80680000 0x3400 0x20 && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000 ;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define SD2_MC_INIT_CMD \
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"mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"env exists secureboot && " \
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"mmc read 0x80640000 0x3200 0x20 && " \
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"mmc read 0x80680000 0x3400 0x20 && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000 ;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x64f00000\0" \
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"kernel_start=0x1000000\0" \
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"kernelheader_start=0x600000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x81000000\0" \
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"kernelheader_size=0x40000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernelhdr_addr_sd=0x3000\0" \
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"kernel_size_sd=0x1d000\0" \
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"kernelhdr_size_sd=0x20\0" \
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"console=ttyAMA0,38400n8\0" \
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BOOTENV \
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"mcmemsize=0x70000000\0" \
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XSPI_MC_INIT_CMD \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0"
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#define XSPI_NOR_BOOTCOMMAND \
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"sf probe 0:0; " \
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"sf read 0x806c0000 0x6c0000 0x40000; " \
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"env exists mcinitcmd && env exists secureboot" \
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" && esbc_validate 0x806c0000; " \
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"sf read 0x80d00000 0xd00000 0x100000; " \
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"env exists mcinitcmd && " \
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"fsl_mc lazyapply dpl 0x80d00000; " \
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"run distro_bootcmd;run xspi_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#define SD_BOOTCOMMAND \
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"env exists mcinitcmd && mmcinfo; " \
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"mmc read 0x80d00000 0x6800 0x800; " \
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"env exists mcinitcmd && env exists secureboot " \
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" && mmc read 0x806C0000 0x3600 0x20 " \
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"&& esbc_validate 0x806C0000;env exists mcinitcmd " \
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"&& fsl_mc lazyapply dpl 0x80d00000;" \
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"run distro_bootcmd;run sd_bootcmd;" \
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"env exists secureboot && esbc_halt;"
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#define SD2_BOOTCOMMAND \
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"mmc dev 1; env exists mcinitcmd && mmcinfo; " \
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"mmc read 0x80d00000 0x6800 0x800; " \
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"env exists mcinitcmd && env exists secureboot " \
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" && mmc read 0x806C0000 0x3600 0x20 " \
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"&& esbc_validate 0x806C0000;env exists mcinitcmd " \
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"&& fsl_mc lazyapply dpl 0x80d00000;" \
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"run distro_bootcmd;run sd2_bootcmd;" \
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"env exists secureboot && esbc_halt;"
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1) \
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func(SCSI, scsi, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif /* __LX2_COMMON_H */
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