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70f05ac34e
Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c * Patch by Paul Ruhland, 24 May 2004: fix SDRAM initialization for LPD7A400 board.
213 lines
5.6 KiB
ArmAsm
213 lines
5.6 KiB
ArmAsm
/*
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* Memory Setup - initialize memory controller(s) for devices required
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* to boot and relocate
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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/* memory controller */
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#define BCRX_DEFAULT (0x0000fbe0)
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#define BCRX_MW_8 (0x00000000)
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#define BCRX_MW_16 (0x10000000)
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#define BCRX_MW_32 (0x20000000)
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#define BCRX_PME (0x08000000)
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#define BCRX_WP (0x04000000)
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#define BCRX_WST2_SHIFT (11)
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#define BCRX_WST1_SHIFT (5)
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#define BCRX_IDCY_SHIFT (0)
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/* Bank0 Async Flash */
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#define BCR0 (0x80002000)
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#define BCR0_FLASH (BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
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/* Bank1 Open */
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#define BCR1 (0x80002004)
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/* Bank2 Not used (EEPROM?) */
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#define BCR2 (0x80002008)
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/* Bank3 Not used */
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#define BCR3 (0x8000200C)
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/* Bank4 PC Card1 */
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/* Bank5 PC Card2 */
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/* Bank6 CPLD IO Controller Peripherals (slow) */
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#define BCR6 (0x80002018)
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#define BCR6_CPLD_SLOW (BCRX_DEFAULT | BCRX_MW_16)
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/* Bank7 CPLD IO Controller Peripherals (fast) */
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#define BCR7 (0x8000201C)
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#define BCR7_CPLD_FAST (BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
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/* SDRAM */
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#define GBLCNFG (0x80002404)
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#define GC_CKE (0x80000000)
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#define GC_CKSD (0x40000000)
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#define GC_LCR (0x00000040)
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#define GC_SMEMBURST (0x00000020)
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#define GC_MRS (0x00000002)
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#define GC_INIT (0x00000001)
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#define GC_CMD_NORMAL (GC_CKE)
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#define GC_CMD_MODE (GC_CKE | GC_MRS)
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#define GC_CMD_SYNCFLASH_LOAD (GC_CKE | GC_MRS | GC_LCR)
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#define GC_CMD_PRECHARGEALL (GC_CKE | GC_INIT)
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#define GC_CMD_NOP (GC_CKE | GC_INIT | GC_MRS)
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#define RFSHTMR (0x80002408)
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#define RFSHTMR_INIT (10) /* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
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#define RFSHTMR_NORMAL (1500) /* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
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#define SDCSCX_BASE (0x80002410)
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#define SDCSCX_DEFAULT (0x01220008)
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#define SDCSCX_AUTOPC (0x01000000)
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#define SDCSCX_RAS2CAS_2 (0x00200000)
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#define SDCSCX_RAS2CAS_3 (0x00300000)
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#define SDCSCX_WBL (0x00080000)
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#define SDCSCX_CASLAT_8 (0x00070000)
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#define SDCSCX_CASLAT_7 (0x00060000)
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#define SDCSCX_CASLAT_6 (0x00050000)
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#define SDCSCX_CASLAT_5 (0x00040000)
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#define SDCSCX_CASLAT_4 (0x00030000)
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#define SDCSCX_CASLAT_3 (0x00020000)
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#define SDCSCX_CASLAT_2 (0x00010000)
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#define SDCSCX_2KPAGE (0x00000040)
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#define SDCSCX_SROMLL (0x00000020)
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#define SDCSCX_SROM512 (0x00000010)
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#define SDCSCX_4BNK (0x00000008)
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#define SDCSCX_2BNK (0x00000000)
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#define SDCSCX_EBW_16 (0x00000004)
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#define SDCSCX_EBW_32 (0x00000000)
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#define SDRAM_BASE (0xC0000000)
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#define SDCSC_BANK_OFFSET (0x10000000)
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/*
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* The SDRAM DEVICE MODE PROGRAMMING VALUE
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*/
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#define BURST_LENGTH_4 (2 << 10)
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#define BURST_LENGTH_8 (3 << 10)
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#define WBURST_LENGTH_BL (0 << 19)
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#define WBURST_LENGTH_SINGLE (1 << 19)
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#define CAS_2 (2 << 14)
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#define CAS_3 (3 << 14)
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#define BAT_SEQUENTIAL (0 << 13)
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#define BAT_INTERLEAVED (1 << 13)
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#define OPM_NORMAL (0 << 17)
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#define SDRAM_DEVICE_MODE (WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
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#define TIMER1_BASE (0x80000C00)
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/*
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* special lookup flags
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*/
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#define DO_MEM_DELAY 1
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#define DO_MEM_READ 2
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_TEXT_BASE:
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.word TEXT_BASE
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.globl memsetup
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memsetup:
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mov r9, lr @ save return address
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads INITMEM_DATA out of FLASH rather than memory ! */
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/* r0 = current word pointer */
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/* r1 = end word location, one word past last actual word */
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/* r3 = address for writes, special lookup flags */
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/* r4 = value for writes, delay constants, or read addresses */
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/* r2 = location for mem reads */
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ldr r0, =INITMEM_DATA
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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add r1, r0, #112
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mem_loop:
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cmp r1, r0
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moveq pc, r9 @ Done
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ldr r3, [r0], #4 @ Fetch Destination Register Address, or 1 for delay
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ldr r4, [r0], #4 @ value
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cmp r3, #DO_MEM_DELAY
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bleq mem_delay
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beq mem_loop
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cmp r3, #DO_MEM_READ
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ldreq r2, [r4]
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beq mem_loop
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str r4, [r3] @ normal register/ram store
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b mem_loop
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mem_delay:
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ldr r5, =TIMER1_BASE
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mov r6, r4, LSR #1 @ timer resolution is ~2us
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str r6, [r5]
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mov r6, #0x88 @ using 508.469KHz clock, enable
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str r6, [r5, #8]
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0: ldr r6, [r5, #4] @ timer value
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cmp r6, #0
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bne 0b
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mov r6, #0 @ disable timer
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str r6, [r5, #8]
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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INITMEM_DATA:
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.word BCR0
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.word BCR0_FLASH
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.word BCR6
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.word BCR6_CPLD_SLOW
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.word BCR7
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.word BCR7_CPLD_FAST
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.word SDCSCX_BASE
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.word (SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
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.word GBLCNFG
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.word GC_CMD_NOP
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.word DO_MEM_DELAY
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.word 200
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.word GBLCNFG
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.word GC_CMD_PRECHARGEALL
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.word RFSHTMR
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.word RFSHTMR_INIT
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.word DO_MEM_DELAY
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.word 8
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.word RFSHTMR
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.word RFSHTMR_NORMAL
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.word GBLCNFG
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.word GC_CMD_MODE
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.word DO_MEM_READ
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.word (SDRAM_BASE | SDRAM_DEVICE_MODE)
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.word GBLCNFG
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.word GC_CMD_NORMAL
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.word SDCSCX_BASE
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.word (SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
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