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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
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*/
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#ifndef __DRIVERS_PINCTRL_IMX_H
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#define __DRIVERS_PINCTRL_IMX_H
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/**
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* @base: the address to the controller in virtual memory
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* @input_sel_base: the address of the select input in virtual memory.
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* @flags: flags specific for each soc
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* @mux_mask: Used when SHARE_MUX_CONF_REG flag is added
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*/
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struct imx_pinctrl_soc_info {
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void __iomem *base;
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void __iomem *input_sel_base;
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unsigned int flags;
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unsigned int mux_mask;
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};
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/**
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* @dev: a pointer back to containing device
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* @info: the soc info
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*/
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struct imx_pinctrl_priv {
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struct udevice *dev;
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struct imx_pinctrl_soc_info *info;
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};
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extern const struct pinctrl_ops imx_pinctrl_ops;
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#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
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#define IMX_PAD_SION 0x40000000 /* set SION */
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/*
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* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
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* 1 u32 CONFIG, so 24 types in total for each pin.
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*/
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#define FSL_PIN_SIZE 24
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#define SHARE_FSL_PIN_SIZE 20
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/* Each pin on imx8qm/qxp consists of 2 u32 PIN_FUNC_ID and 1 u32 CONFIG */
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#define SHARE_IMX8_PIN_SIZE 12
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#define SHARE_MUX_CONF_REG 0x1
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#define ZERO_OFFSET_VALID 0x2
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#define CFG_IBE_OBE 0x4
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#define IMX8_USE_SCU 0x8
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#define IOMUXC_CONFIG_SION (0x1 << 4)
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int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
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int imx_pinctrl_remove(struct udevice *dev);
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#ifdef CONFIG_PINCTRL_IMX_SCU
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int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
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u32 *pin_data, int npins);
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#else
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static inline int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
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u32 *pin_data, int npins)
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{
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return 0;
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}
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#endif
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#endif /* __DRIVERS_PINCTRL_IMX_H */
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