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2ccacf3c7f
DM_GPIO based GPIO controller driver for CAxxxx SoCs. This driver support multiple CPU architectures and Cortina Access SoC platforms. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Jason Li <jason.li@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
112 lines
2.6 KiB
C
112 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Cortina-Access
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*
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* GPIO Driver for Cortina Access CAxxxx Line of SoCs
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/compat.h>
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#include <linux/compiler.h>
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/* GPIO Register Map */
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#define CORTINA_GPIO_CFG 0x00
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#define CORTINA_GPIO_OUT 0x04
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#define CORTINA_GPIO_IN 0x08
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#define CORTINA_GPIO_LVL 0x0C
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#define CORTINA_GPIO_EDGE 0x10
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#define CORTINA_GPIO_BOTHEDGE 0x14
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#define CORTINA_GPIO_IE 0x18
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#define CORTINA_GPIO_INT 0x1C
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#define CORTINA_GPIO_STAT 0x20
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struct cortina_gpio_bank {
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void __iomem *base;
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};
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#ifdef CONFIG_DM_GPIO
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static int ca_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct cortina_gpio_bank *priv = dev_get_priv(dev);
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setbits_32(priv->base, BIT(offset));
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return 0;
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}
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static int
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ca_gpio_direction_output(struct udevice *dev, unsigned int offset, int value)
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{
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struct cortina_gpio_bank *priv = dev_get_priv(dev);
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clrbits_32(priv->base, BIT(offset));
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return 0;
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}
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static int ca_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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struct cortina_gpio_bank *priv = dev_get_priv(dev);
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return readl(priv->base + CORTINA_GPIO_IN) & BIT(offset);
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}
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static int ca_gpio_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct cortina_gpio_bank *priv = dev_get_priv(dev);
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setbits_32(priv->base + CORTINA_GPIO_OUT, BIT(offset));
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return 0;
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}
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static int ca_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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struct cortina_gpio_bank *priv = dev_get_priv(dev);
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if (readl(priv->base) & BIT(offset))
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return GPIOF_INPUT;
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else
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return GPIOF_OUTPUT;
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}
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static const struct dm_gpio_ops gpio_cortina_ops = {
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.direction_input = ca_gpio_direction_input,
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.direction_output = ca_gpio_direction_output,
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.get_value = ca_gpio_get_value,
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.set_value = ca_gpio_set_value,
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.get_function = ca_gpio_get_function,
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};
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static int ca_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct cortina_gpio_bank *priv = dev_get_priv(dev);
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priv->base = dev_remap_addr_index(dev, 0);
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if (!priv->base)
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return -EINVAL;
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uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32);
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uc_priv->bank_name = dev->name;
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debug("Done Cortina GPIO init\n");
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return 0;
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}
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static const struct udevice_id ca_gpio_ids[] = {
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{.compatible = "cortina,ca-gpio"},
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{}
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};
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U_BOOT_DRIVER(cortina_gpio) = {
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.name = "cortina-gpio",
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.id = UCLASS_GPIO,
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.ops = &gpio_cortina_ops,
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.probe = ca_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct cortina_gpio_bank),
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.of_match = ca_gpio_ids,
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};
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#endif /* CONFIG_DM_GPIO */
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