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110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*-----------------------------------------------------------------------------+
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| This source code is dual-licensed. You may use it under the terms of
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| the GNU General Public License version 2, or under the license below.
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1995
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+-----------------------------------------------------------------------------*/
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/*
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* Adapted for PIP405 03.07.01
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* TODO: Clean-up
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*/
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#include <common.h>
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#include <pci.h>
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#include "isa.h"
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#ifdef CONFIG_405GP
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#ifdef CONFIG_PCI
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DECLARE_GLOBAL_DATA_PTR;
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#include "piix4_pci.h"
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#include "pci_parts.h"
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void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *entry)
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{
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struct pci_pip405_config_entry *table;
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int i;
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table = (struct pci_pip405_config_entry*) entry->priv[0];
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for (i=0; table[i].width; i++)
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{
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#ifdef DEBUG
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printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
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table[i].index, table[i].val, table[i].width);
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#endif
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switch(table[i].width)
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{
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case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
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case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
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case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
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}
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}
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}
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static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char int_line = 0xff;
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unsigned char pin;
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/*
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* Write pci interrupt line register
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*/
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if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
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return;
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pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
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if ((pin == 0) || (pin > 4))
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return;
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int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
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#ifdef DEBUG
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printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
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PCI_DEV(dev),dev,int_line,int_line);
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#endif
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}
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extern void pci_405gp_init(struct pci_controller *hose);
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static struct pci_controller hose = {
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config_table: pci_pip405_config_table,
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fixup_irq: pci_pip405_fixup_irq,
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};
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void pci_init_board(void)
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{
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/*we want the ptrs to RAM not flash (ie don't use init list)*/
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hose.fixup_irq = pci_pip405_fixup_irq;
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hose.config_table = pci_pip405_config_table;
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#ifdef DEBUG
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printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
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#endif
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pci_405gp_init(&hose);
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}
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#endif /* CONFIG_PCI */
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#endif /* CONFIG_405GP */
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